IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`In re Inter Partes Review of:
`U.S. Patent No. 8,252,675
`Issued: August 28, 2012
`Application No.: 12/942,763
`Filing Date: November 9, 2010
`
`For: Methods of Forming CMOS Transistors with High Conductivity
`Gate Electrodes
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`
`FILED VIA PRPS
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`
`DECLARATION OF JACK LEE IN SUPPORT OF SECOND
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,252,675
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`For ease of reference, Dr. Lee refers to this second declaration as being in support
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`of the “Second ’675 Petition” challenging claims 1-8 and 10-15 of the ’675 patent.
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`NVIDIA Corp.
`Exhibit 1103
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`Page 001
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`Inter Partes Review of USP 8,252,675
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`TABLE OF CONTENTS
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`I.
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`II.
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`Introduction And Qualifications ...................................................................... 1
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`Understanding Of The Governing Law ........................................................... 5
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`A.
`B.
`C.
`D.
`E.
`
`Claim Construction ............................................................................... 5
`Invalidity by Anticipation or Obviousness ........................................... 5
`Interpreting Claims Before the Patent Office ........................................ 6
`Relevant Time Period for the Obviousness Analysis ............................ 6
`Basis for My Opinion ............................................................................ 7
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`III. Level Of Ordinary Skill In The Art In The Relevant Timeframe ................... 7
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`IV. Perspective Applied In This Declaration ......................................................... 8
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`V.
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`Technology Background .................................................................................. 8
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`A. NMOS and PMOS Transistors .............................................................. 8
`B.
`Photolithography and Etching ............................................................. 10
`C.
`Chemical-Mechanical Polishing (CMP) ............................................. 10
`D. Gate-First Versus Gate-Last ................................................................ 11
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`VI. Overview Of The ’675 Patent ........................................................................ 12
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`VII. Overview Of U.S. Patent No. 8,536,660 (“Hsu”) ......................................... 18
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`VIII. Hsu Glossary .................................................................................................. 24
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`A.
`B.
`C.
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`Claim 1 ................................................................................................ 24
`Claim 6 ................................................................................................ 26
`Hsu Figures .......................................................................................... 28
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`IX. Claim Construction ........................................................................................ 29
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`X. Differences Between Hsu And U.S. Patent No. 2009/0065809
`(“Yamakawa”) ............................................................................................... 30
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`XI. Summary Of Grounds .................................................................................... 31
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`i
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`NVIDIA Corp.
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`XII. First Ground Of Invalidity – The Challenged Claims Are Anticipated
`By U.S. Patent No. 8,536,660 (“Hsu”) .......................................................... 31
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`Inter Partes Review of USP 8,252,675
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`Claim 1 ................................................................................................ 31
`A.
`Claim 2 ................................................................................................ 43
`B.
`Claim 3 ................................................................................................ 43
`C.
`Claim 4 ................................................................................................ 44
`D.
`Claim 5 ................................................................................................ 45
`E.
`Claim 6 ................................................................................................ 45
`F.
`Claim 7 ................................................................................................ 57
`G.
`Claim 8 ................................................................................................ 58
`H.
`Claim 10 .............................................................................................. 59
`I.
`Claim 11 .............................................................................................. 63
`J.
`Claim 12 .............................................................................................. 64
`K.
`Claim 13 .............................................................................................. 68
`L.
`M. Claim 14 .............................................................................................. 68
`N.
`Claim 15 .............................................................................................. 69
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`XIII. Second Ground Of Invalidity – Claim 12 Is Rendered Obvious By
`Hsu ................................................................................................................. 69
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`A.
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`Claim 12 .............................................................................................. 69
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`XIV. Conclusion ..................................................................................................... 71
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`ii
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`NVIDIA Corp.
`Exhibit 1103
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`Page 003
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`Inter Partes Review of USP 8,252,675
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`I, Jack Lee, Professor of the Electrical and Computer Engineering
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`Department at The University of Texas at Austin, hereby declare as follows:
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`I.
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`INTRODUCTION AND QUALIFICATIONS
`1.
`
`I have been retained by NVIDIA Corporation (“NVIDIA”) to provide
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`my opinion concerning the validity of U.S. Patent No. 8,252,675 (Ex. 1101,
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`“the ’675 patent”) in support of its Second Petition for Inter Partes Review of U.S.
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`Patent No. 8,252,675 (“Petition”). I previously submitted a declaration on June 1,
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`2015 in support of Petitioner’s position in IPR2015-01318. The IPR2015-01318
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`requests institution of inter partes review on the ’675 patent based on Yamakawa
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`as the primary prior art reference. In Section X, I compare the difference between
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`the reference relied upon (Hsu) in this Petition with Yamakawa, and conclude that
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`Hsu is a stronger reference.
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`2.
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`I am an expert in the field of semiconductor process technology and
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`semiconductor design. I have over 30 years of first-hand experience as a
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`researcher, educator, and consultant in this field.
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`3.
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`I received a B.S. degree in Electrical Engineering, with highest
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`honors, in 1980, and an M.S. degree in Electrical Engineering in 1981, both from
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`University of California, Los Angeles. I received a Ph.D. degree in Electrical
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`Engineering in 1988 from University of California, Berkeley (“UC Berkeley”).
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`4.
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`From 1979 to 1984, I was a Member of Technical Staff at the
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`1
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`NVIDIA Corp.
`Exhibit 1103
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`Page 004
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`TRW Microelectronics Center, in the High‐Speed Bipolar Device Program.
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`Inter Partes Review of USP 8,252,675
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`I worked on bipolar device/circuit design, fabrication, and testing. I was promoted
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`to Engineering Group Leader level in 1983.
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`5.
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`I received several academic honors while at UC Berkeley.
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`For example, I won the Best Paper Award from the Institute of Electrical and
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`Electronics Engineers (“IEEE”) International Reliability Physics Symposium in
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`1988. I was also awarded a Lectureship with my own teaching assistant from UC
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`Berkeley.
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`6.
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`After receiving my Ph.D. in August 1988, I joined the faculty at The
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`University of Texas at Austin (“UT Austin”). As a faculty member, I have taught
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`numerous courses in semiconductor device fabrication and design, at both the
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`undergraduate and graduate levels. I have supervised 40 students who received a
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`doctoral degree under my guidance. I am currently the Cullen Trust for Higher
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`and Computer Engineering at UT Austin.
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`Education Endowed Professor in Engineering #4 in the Department of Electrical
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`7. My current research interests include: high‐K gate dielectrics and
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`metal gate
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`electrodes
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`in
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`semiconductor devices
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`(CMOS/MOSFETs);
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`semiconductor device fabrication processes, characterization and modeling;
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`dielectric processes, characterization and reliability; and alternative transistor
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`channel materials. My research has been partially supported by grants from the
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`2
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`NVIDIA Corp.
`Exhibit 1103
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`Page 005
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`Inter Partes Review of USP 8,252,675
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`National Science Foundation, the Texas Advanced Research Program, the
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`Semiconductor Research Corporation (SRC), SEMATECH, Texas Emerging
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`Technology Funds, and others.
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`8.
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`I have authored over 500 journal publications and conference
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`proceeding papers, and have coauthored one book and two book chapters on
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`semiconductor devices. Much of my research and publications since ~1998 focus
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`on the topic of gate stacks, including high-K gate dielectrics and gate-first vs. gate-
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`last processes. I am a named inventor of several U.S. patents, including:
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`• U.S. Patent No. 6,013,546 (“Semiconductor Device Having a
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`PMOS Device with a Source/Drain Region Formed Using a Heavy
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`Atom p-Type Implant and Method of Manufacture Thereof”);
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`• U.S. Patent No. 6,057,584 (“Semiconductor Device Having a
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`Tri-Layer Gate Insulating Dielectric”);
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`• U.S. Patent No. 6,146,934
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`(“Semiconductor Device with
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`Asymmetric PMOS Source/Drain
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`Implant and Method of
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`Manufacture Thereof”);
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`• U.S. Patent No. 6,306,742 (“Method for Forming a High Dielectric
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`Constant Insulator in the Fabrication of an Integrated Circuit”);
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`and
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`• U.S. Patent No. 5,891,798 (“Method for Forming a High Dielectric
`
`3
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`NVIDIA Corp.
`Exhibit 1103
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`Page 006
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`Constant Insulator in the Fabrication of an Integrated Circuit”).
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`Inter Partes Review of USP 8,252,675
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`9.
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`I have also earned many research awards including the prestigious
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`SRC Inventor Recognition Award from Semiconductor Research Corporation for
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`my work on dielectric technology and characterization.
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`understanding and development of ultra‐thin dielectrics and their application to
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`10.
`
`In 2002, I became an IEEE fellow for my “contributions to the
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`silicon devices.” I am also an IEEE Electron Devices Society Distinguished
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`Lecturer.
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`11.
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`I have served in various technology consulting and business advisor
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`roles. For example, I have taught short courses on semiconductor device physics
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`and
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`technologies at various semiconductor companies and consortiums
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`(e.g., SEMATECH). I have also organized several international conferences and
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`have given lectures at numerous conferences and symposia, including the
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`International Symposium on VLSI Technologies, the IEEE Symposia on
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`VLSI Technology, and the IEEE International Electron Devices Meeting. These
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`conferences are some of the most prestigious in the field.
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`12. My Curriculum Vitae is provided as Ex. 1104.
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`13. My work in this matter is being billed at a rate of $475 per hour, with
`
`reimbursement for necessary and reasonable expenses. My compensation is not in
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`any way contingent upon the outcome of this Inter Partes Review. I have no
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`4
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`NVIDIA Corp.
`Exhibit 1103
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`Page 007
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`interest in the outcome of this proceeding or any related litigation.
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`Inter Partes Review of USP 8,252,675
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`II. UNDERSTANDING OF THE GOVERNING LAW
`
`A. Claim Construction
`I understand that in deciding whether to institute inter partes review,
`14.
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`“[a] claim in an unexpired patent shall be given its broadest reasonable
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`construction in light of the specification of the patent in which it appears.” 37
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`C.F.R. § 42.100(b). I understand that this claim construction standard is different
`
`from—and typically broader than—that applied in district court.
`
`B.
`15.
`
`Invalidity by Anticipation or Obviousness
`
`I understand that a claim is invalid if it is anticipated. I understand
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`that anticipation of a claim requires that every element of a claim is disclosed
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`expressly or inherently in a single prior art reference, arranged as in the claim.
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`16.
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`I further understand that obviousness of a claim requires that the claim
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`be obvious from the perspective of a person of ordinary skill in the relevant art, at
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`the time the invention was made. In analyzing obviousness, I understand that it is
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`important to understand the scope of the claims, the level of skill in the relevant
`
`art, the scope and content of the prior art, the differences between the prior art and
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`the claims, and any secondary considerations. I also understand that if a technique
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`has been used to improve one device, and a person of ordinary skill in the art
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`would recognize that it would improve similar devices in the same way, using the
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`5
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`technique is obvious unless its actual application is beyond his or her skill. There
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`may also be a specific teaching, suggestion or motivation to combine any first prior
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`art reference with a second prior art reference. Such a teaching, suggestion, or
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`motivation to combine the first prior art reference with the second prior art
`
`reference can be explicit or implicit in the first or second prior art references.
`
`C.
`17.
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`Interpreting Claims Before the Patent Office
`I understand that “Inter Partes Review” is a proceeding before the
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`United States Patent & Trademark Office (“Patent Office”) for evaluating the
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`validity of an issued patent claim. I understand that in an Inter Partes Review,
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`the claims of a patent are given their broadest reasonable interpretation that is
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`consistent with the patent specification. I understand that a patent’s “specification”
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`includes all the figures, discussion, and claims in the patent. I understand that the
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`Patent Office will look to the specification to see if there is a definition for a claim
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`term, and if not, will apply the broadest reasonable interpretation from the
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`perspective of a person of ordinary skill in the art.
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`D. Relevant Time Period for the Obviousness Analysis
`I also understand that the earliest patent application leading to the
`18.
`
`’675 patent was filed in November 9, 2010, and that the patentee has claimed
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`priority back to December 8, 2009. For the purpose of this declaration, I have
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`therefore analyzed obviousness as of approximately late 2009 or slightly before,
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`6
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`NVIDIA Corp.
`Exhibit 1103
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`understanding that as time passes, the knowledge of a person of ordinary skill in
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`the art will increase.
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`E.
`19.
`
`Basis for My Opinion
`
`In forming my opinion, I have relied on the ’675 patent claims,
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`disclosure and prosecution history, the prior art exhibits to the Petition for
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`Inter Partes Review of the ’675 patent, and my own experience, expertise and
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`knowledge of a person of ordinary skill in the relevant art in the relevant
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`timeframe.
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`III. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
`20.
`
`In 2009, I believe that a relevant person of ordinary skill in the art
`
`would have had an undergraduate degree in electrical engineering (or equivalent
`
`subject) together with three to four years of post-graduate experience designing
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`semiconductor devices and fabrication processes, or a master’s degree in electrical
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`engineering (or equivalent subject) together with one to two years of post-graduate
`
`experience in designing semiconductor devices and fabrication processes. A
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`person of ordinary skill also would have been familiar with the gate-last (or gate
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`replacement) technique of forming metal gate electrodes. This description is
`
`approximate, and a higher level of education or skill might make up for less
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`experience, and vice-versa.
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`21.
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` I believe that I would qualify as at least a person of ordinary skill in
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`the art in 2009, and that I have a sufficient level of knowledge, experience and
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`education to provide an opinion in the field of the ’675 patent. I am familiar with
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`what a person of ordinary skill in the art knew in 2009 because, through my
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`professional activities, I was directly involved in the education and training of
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`individuals who were persons of ordinary skill in the art. In 2009, I was familiar
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`with the general subject material in the cited prior art in this Declaration.
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`IV. PERSPECTIVE APPLIED IN THIS DECLARATION
`22. My testimony in this declaration is given from the perspective of a
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`person of ordinary skill in the art at the time of the filing of the ’675 patent, and for
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`some time before then, unless otherwise specifically indicated. This is true even if
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`the testimony is given in the present tense. Each of the statements below is my
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`opinion based on my review of the ’675 patent and its claims, as well as the prior
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`art cited in this declaration and the prosecution history of the ’675 patent.
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`V. TECHNOLOGY BACKGROUND
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`A. NMOS and PMOS Transistors
`23. There are two basic types of metal-oxide-semiconductor (MOS)
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`transistors, in accordance with the channel type which is induced beneath the gate
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`electrode: NMOS transistors and PMOS transistors. ’675 patent at 1:24-26.
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`CMOS is a common design technique that uses complementary and matching pairs
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`of NMOS and PMOS transistors. See id. at 2:4-8. A threshold voltage is the
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`minimum gate-to-source voltage differential required to form the channel, or
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`induce the corresponding flow of charge carriers, beneath the PMOS and NMOS
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`transistors.
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`24. As shown in the figures below, when an NMOS or PMOS transistor is
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`turned on, a channel is formed in which electrons (-) or holes (+) flow through the
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`body region from source to drain, respectively. See id. at 1:24-30. An NMOS
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`transistor is turned on by applying a large enough positive voltage to the gate
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`electrode, and a PMOS transistor is turned on by applying a large enough negative
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`voltage to the gate electrode.
`
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`25. CMOS is a common design technique that uses complementary and
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`matching pairs of NMOS and PMOS transistors. See id. at 1:27-32. Each pair has
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`two gate electrodes—(1) the gate electrode that controls the channel of the NMOS
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`transistor, and (2) the gate electrode that controls the channel of the PMOS
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`transistor. Id.
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`9
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`NVIDIA Corp.
`Exhibit 1103
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`Page 012
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`
`B.
`Photolithography and Etching
`26. NMOS and PMOS transistor gates are formed using a series of
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`photolithography steps. Photolithography typically involves depositing a light
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`sensitive but etchant resistive film, called a photoresist, onto the wafer surface.
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`The photoresist is then exposed to ultraviolet (“UV”) light through a mask and the
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`areas where the photoresist was exposed to the UV light are washed away.
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`This produces a photoresist pattern. The photoresist pattern is then used as a mask
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`to etch materials in the areas where the photoresist had been washed away.
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`27. During etching, both the film being etched and other materials under
`
`or within the film being etched can be etched by the etchant. The etching occurs
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`from top to bottom because the etchant must first etch through upper layers before
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`it can reach lower layers. Thus, for example, if top, middle, and bottom layers had
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`been deposited, etching through all three layers would require etching those layers
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`sequentially, i.e., etching the top layer first, etching the middle layer second, and
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`etching the bottom layer last.
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`C. Chemical-Mechanical Polishing (CMP)
`In a CMP process, the wafer is mounted face down on a rotating
`28.
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`carrier, and is pressed against a rotating plate containing a polishing pad.
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`An abrasive aqueous slurry is continuously dripped onto the pad. CMP also
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`removes material from top to bottom because it must polish through the top layer
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`of material before the next underlying layer is exposed to the polishing pad and
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`slurry. Depending on the complexity of the materials being polished, a multi-step
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`polishing sequence with different types of slurry might be used.
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`D. Gate-First Versus Gate-Last
`In the most simple terms, gate-first and gate-last refer to whether the
`29.
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`transistor gate is formed before or after a high temperature annealing process
`
`required to form the source and drain regions of a transistor.
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`30.
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`In a gate first process, the gate is formed early in the process, and it
`
`then acts as a mask for the source and drain implants. After implanting the source
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`and drain, the wafer must be annealed to repair damage done during implantation,
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`and activate the implanted source/drain dopants to establish the desired dopant
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`profile. The main problem with a gate-first approach is that the high temperatures
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`required for this annealing step can cause undesired changes in the gate stack.
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`31. Gate-last is an approach to solving that problem. In gate-last, a
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`sacrificial gate (aka “dummy gate”) serves as the mask for the source and drain
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`implants. After the annealing process, the sacrificial gate is removed and a new
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`gate stack is formed. In other words, the real gate is built last, after the source and
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`drain have been formed. The figure below shows typical gate-first (top) and gate-
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`last (bottom) process flows.
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`11
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`NVIDIA Corp.
`Exhibit 1103
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`32. As discussed below, the ’675 patent and the Hsu reference
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`(U.S. Patent No. 8,536,660) (Ex. 1105) both disclose a process in which the
`
`bottommost layer of the NMOS and PMOS gates is formed before the source/drain
`
`annealing process, and the remaining layers are formed after removal of a dummy
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`gate and after the source/drain annealing process. Because all but one layer of the
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`gates are formed using a gate-last approach, the approach disclosed in both the
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`’675 patent and the Hsu reference is generally considered a gate-last process.
`
`VI. OVERVIEW OF THE ’675 PATENT
`In the gate-last process of the ’675 patent, gate insulating layer 18,
`33.
`
`buffer gate electrode 201, and dummy gate electrode 22 are formed on substrate 10.
`
`
`1 The second embodiment disclosed in the ’675 specification refers to layer 20 as
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`the “buffer gate electrode,” which corresponds to the “metal buffer gate electrode
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`layer” in claim 1 and the “first metal gate electrode layer” in claim 6.
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`12
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`NVIDIA Corp.
`Exhibit 1103
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`See ’675 patent at 7:1-5, Fig. 19 (annotated).
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`Inter Partes Review of USP 8,252,675
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`34. The layers are patterned by photolithography to form dummy gate
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`stack 24. Id. at 7:13-19. Dummy gate stack 24 includes gate insulating layer 18,
`
`buffer gate electrode 20, and dummy gate electrode 22. Id. at 7:15-17, Fig. 20
`
`(annotated).
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`35. Spacers 28 are formed on sidewalls of the dummy gate stack 24. Id.
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`at 7:47-48, Fig. 23 (annotated).
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`36. Source and drain regions 30 are subsequently formed using the
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`dummy gate electrodes and spacers as an implantation mask. Id. at 7:55-8:11, Fig.
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`25 (annotated).
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`37. Mold insulating layer 32 is formed and dummy gate electrode 22 is
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`removed, thus forming trench 35. Id. at 8:17-27, Fig. 27 (annotated).
`
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`
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`38. First metal layer 36 is then blanket deposited on inner sidewalls of
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`spacers 28 and on an upper surface of buffer gate electrode 20. Id. at 8:38-51, Fig.
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`28 (annotated).
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`39. Dummy fill layer 38 is formed in trench 35 and first metal layer 36 is
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`removed from mold insulating layer 32. Id. at 8:52-64. A portion of the second
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`metal gate electrode layer 36 in trench 35 is also removed. Id. at 8:64-67, Fig. 31
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`(annotated).
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`40. Next, dummy fill layer 38 is removed and second metal layer 42 is
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`deposited. Id. at 9:9-20, Fig. 33 (annotated). Second metal layer 42 “may
`
`comprise at least one of aluminum, tungsten and titanium.” Id. at 9:22-24. Second
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`metal layer 42 is removed from mold insulating layer 32 and planarized. Id. at
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`9:31-33, Fig. 34 (annotated).
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`41. Dummy gate electrode 22 is then removed, and third metal layer 44 is
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`deposited to fill the trench. Id. at 9:47-49, 9:59-61. Third metal layer 44 “may
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`comprise at least one of aluminum, tungsten, titanium and tantalum.” Id. at 9:61-
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`63. Third metal layer 44 is then removed from mold insulating layer 32 and
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`planarized. Id. at 10:1-4, Fig. 37 (annotated).
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`NVIDIA Corp.
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`VII. OVERVIEW OF U.S. PATENT NO. 8,536,660 (“HSU”)
`42. U.S. Patent No. 8,536,660 (“Hsu”) is titled “Hybrid Process for
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`Inter Partes Review of USP 8,252,675
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`Forming Metal Gates of MOS Devices,” and lists Peng-Fu Hsu, Yong-Tian Hou,
`
`Ssu-Yi Li, Kuo-Tai Huang, and Mong Song Liang as inventors. Hsu was filed
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`March 12, 2008, published September 17, 2009, and issued September 17, 2013.
`
`I understand Hsu is prior art to the ’675 patent under pre-AIA 35 U.S.C. § 102(e),
`
`and was not before the examiner during prosecution of the ’675 patent.
`
`43.
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`In the gate-last process of Hsu, two high-k dielectric layers 24 and 26
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`are formed on interfacial layer 22. Id. at 5:16-27, Fig. 1 (annotated).
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`44. Metal layer 32, polysilicon layer 34, and mask layer 36 are then
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`formed over the gate insulating layers. Id. at 5:47-48, Fig. 2 (annotated).
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`45. The deposited layers are then patterned in sequence, forming dummy
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`gate stack 138 in the NMOS region that includes high-k dielectric layers 124 and
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`126, metal layer 132, polysilicon layer 134, and mask layer 136. Id. at 6:10-18,
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`Fig. 3 (annotated). This patterning step also forms gate stack 238 in the PMOS
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`region that includes gate insulating layer 224, metal layer 232, polysilicon layer
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`234, and mask layer 236. Id.
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`46. Spacers 143 and 243 are formed on sidewalls of gate stacks 138 and
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`238. Id. at 6:19-23, Fig. 4 (annotated).
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`
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`47. Source and drain regions are subsequently formed using the gate
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`stacks and spacers as an implantation mask. See id.
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`48.
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`Inter-layer dielectric (ILD) 54 is then formed and polysilicon layer
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`234 (and an upper portion of metal layer 232) is removed. Id. at 6:32-41, Fig. 6
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`(annotated).
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`49. Polysilicon layer 134 is subsequently removed. Id. at 7:9-12, Fig. 7
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`(annotated). Although Fig. 7 shows removal of only an upper portion of
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`polysilicon layer 134, Hsu describes removing the entirety of dummy gate
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`electrode 134. Id. (“In the preferred embodiment, polysilicon layer 134 is fully
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`removed”).
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`50. A second metal layer 60 and third metal layer 62 are then deposited.
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`Hsu discloses that second metal layer 60 is formed of “tantalum or titanium
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`containing materials such as TaC, TaN, TiN, TaAlN, TaSiN, and combinations
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`thereof.” Id. at 7:24-31. Hsu further discloses that the third metal layer 62 may
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`include three sublayers: the bottom layer (621) may be formed of “tungsten-
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`containing materials such as tungsten and tungsten nitride, ruthenium-containing
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`materials such as rutheninm and ruthenium oxynitride, molybdenum-containing
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`materials such as molybdenum and molybdenum nitride, and combinations
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`thereof,” the middle layer (622) may be formed of “TiN, TaN, Ti, Ta, and the like,”
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`and the top layer (623) may be formed of “aluminum, tungsten, and the like.” Id. at
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`7:44-54, Fig. 9 (annotated and excerpted).
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`51. Metal layers 62 and 60 are planarized using CMP, creating composite
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`metal gate electrodes between the sidewalls of spacers 143 and 243. Id. at 7:57-63,
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`Fig. 10 (annotated).
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`VIII. HSU GLOSSARY
`Independent claims 1 and 6 of the ’675 patent use different
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`terminology to refer to the various layers in NMOS and PMOS gate stacks. For
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`ease of reference, I have provided tables mapping the terminology used in both
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`claims 1 and 6 to equivalent terminology used in Hsu.
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`A. Claim 1
`53. For ease of reference, I provide below a table mapping specific terms
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`in the ’675 patent claim 1 with equivalent terminology used in Hsu.
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`’675 Patent (claim 1)
`“gate insulating layer”
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`“metal buffer gate
`electrode layer”
`“dummy gate electrode
`layer”
`“electrically insulating
`spacers”
`“electrically insulating
`mold layer”
`“first metal layer”
`“second metal layer”
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`Hsu Terminology
`“first high-k dielectric
`layer”
`“metal layer 32”
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`“polysilicon layer”
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`“spacers”
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`“inter-layer dielectric
`(ILD)”
`“metal layer 60”
`“metal layer 62”
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`54. The “gate insulating layer” limitation in claim 1 corresponds to the
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`“first high-k dielectric layer” disclosed in Hsu. Gate insulators or gate dielectrics
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`are insulating materials deposited between the gate stack and the substrate of a
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`transistor. A high-k dielectric material disclosed in Hsu is, by definition, an
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`electrical insulator, and it is deposited between the semiconductor substrate and the
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`conductive layers that comprise the gate electrode. Hsu at 5:16-20.
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`55. The “metal buffer gate electrode layer” limitation in claim 1
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`corresponds to the “metal layer 32” disclosed in Hsu. The metal layer 32 disclosed
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`in Hsu is deposited during the manufacturing process to protect the insulating
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`layers. Hsu discloses that exemplary materials for metal layer 32 include TaC,
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`TaN, TiN, TaAIN, and TaSiN. Hsu at 5:55-58.
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`56. The “dummy gate electrode layer” limitation in claim 1 corresponds
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`to the “polysilicon layer” disclosed in Hsu. The polysilicon layer disclosed in Hsu
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`is patterned to form a “dummy gate” that is removed after the source/drain
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`annealing process. Hsu at 6:10-43; 7:9-12.
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`57. The “electrically insulating spacers” limitation in claim 1 corresponds
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`to the “spacers” disclosed in Hsu that are formed on side-walls of the gate stacks.
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`Hsu at 6:19-23. The Hsu spacers are electrically insulating. See ¶ 92, infra
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`(explaining that if the spacers in Hsu were not electrically insulating, the transistor
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`would malfunction).
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`58. The “electrically insulating mold layer” limitation in claim 1
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`corresponds to the “inter-layer dielectric (ILD)” disclosed by Hsu. Hsu at 6:32-35.
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`Because a dielectric is, by definition, an insulator, the inter-layer dielectric (ILD)
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`in Hsu is electrically insulating.
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`59. The “first metal layer” limitation in claim 1 corresponds to the “metal
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`layer 60” disclosed in Hsu. The metal layer 60 disclosed in Hsu comprises one or
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`more metal(s). Hsu discloses that exemplary materials for metal layer 60 include
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`TaC, TaN, TiN, TaAlN, and TaSiN. Hsu at 7:29-31.
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`60. The “second metal layer” limitation claim 1 corresponds to the “metal
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`layer 62” disclosed in Hsu. The metal layer 62 disclosed in Hsu comprises one or
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`more metal(s). Hsu discloses that metal layer 62 may comprise three sublayers and
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`also discloses exemplary materials for each sublayer, as discussed in greater detail
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`in section XII.F.9 below.
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`B. Claim 6
`61. For ease of reference, I provide below a table mapping specific terms
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`in the ’675 patent claim 6 with equivalent terminology used in Hsu.
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`‘675 Patent (claim 6)
`“gate insulating layer”
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`“first metal gate electrode
`layer” (claim 6)
`“dummy gate electrode
`layer”
`“electrically insulating
`spacers”
`“electrically insulating
`mold layer”
`“second metal