UNITED STATES pATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www .uspto.gov
`
`APPLICATION NO.
`
`12/942,763
`
`ISSUE DATE
`
`08/28/2012
`
`PATENT NO.
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`8252675
`
`5649-2985
`
`2294
`
`20792
`7590
`08/08/2012
`MYERS BIGEL SIBLEY & SAJOVEC
`POBOX 37428
`RALEIGH, NC 27627
`
`The projected patent number and issue date are specified above.
`
`ISSUE NOTIFICATION
`
`Determination of Patent Term Adjustment under 35 U.S.C. 154 (b)
`(application filed on or after May 29, 2000)
`
`The Patent Term Adjustment is 0 day(s). Any patent to issue from the above-identified application will include
`an indication of the adjustment on the front page.
`
`If a Continued Prosecution Application (CPA) was filed in the above-identified application, the filing date that
`determines Patent Term Adjustment is the filing date of the most recent CPA.
`
`Applicant will be able to obtain more detailed information by accessing the Patent Application Information
`Retrieval (PAIR) WEB site (http://pair.uspto.gov).
`
`Any questions regarding the Patent Term Extension or Adjustment determination should be directed to the
`Office of Patent Legal Administration at (571)-272-7702. Questions relating to issue and publication fee
`payments should be directed to the Application Assistance Unit (AAU) of the Office of Data Management
`(ODM) at (571)-272-4200.
`
`APPLICANT(s) (Please see PAIR WEB site http://pair.uspto.gov for additional applicants):
`
`Jongwon Lee, Hwaseong-si, KOREA, REPUBLIC OF;
`Boun Yoon, Seoul, KOREA, REPUBLIC OF;
`Sang Yeob Han, Anyang-si, KOREA, REPUBLIC OF;
`Chae Lyoung Kim, Hwaseong-si, KOREA, REPUBLIC OF;
`
`The United States represents the largest, most dynamic marketplace in the world and is an unparalleled location
`for business investment, innovation, and commercialization of new technologies. The USA offers tremendous
`resources and advantages for those who invest and manufacture goods here. Through SelectUSA, our nation
`works to encourage and facilitate business investment. To learn more about why the USA is the best country in
`the world to develop technology, manufacture products, and grow your business, visit SelectUSA.gov.
`
`IR103 (Rev. 10/09)
`
`NVIDIA Corp.
`Exhibit 1102
`Page 001
`
`

`
`PART B- FEE(S) TRANSMITTAL
`
`Complete and send this form, together with applicable fee(s), to: Mail Mail Stop ISSUE FEE
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`(571 )-273-2885
`
`or fu
`INSTRUCTIONS: This form should be used for transmitting the ISSUE lc'EE and PUBLICATION FEE (if required). Blocks l through 5 should be completed where
`appropriate. All further correspondence including the Patent, advance orders and notification of mainten;mce fees will be mailed to the current correspondence address as
`indicated unless corrected below or directed otherwise in Block l, by (a) specifying a new correspondence address; and/or (b) indicating a separate "FEE ADDRESS" for
`maintenance fee notifications.
`CURREKT CORRESPONDENCE ADDRESS (Note: Use Block t for any change of address)
`
`20792
`7590
`06/22/2012
`MYERS BIGEL SIBLEY & SAJOVEC
`PO BOX 37428
`RALEIGH, NC 27627
`
`Note: A certificate of mailing can only be used for domestic mailings of the
`Fee(s) Transmittal. This certificate cannot be used for any other accompanying
`papers. Each additional paper, such as an assi~nment or formal drawing, must
`have its own certificate of mailing or transmiss10n.
`
`Certificate of Mailing or Transmission
`I hereby certify that this Fee(s) Transmittal is being deposited with the United
`States Postal Service with sufficient postage for first class mail in an envelor,e
`addressed to the Mail Stop ISSUE FEE address above, or being facsinule
`transmitted to the USPTO (571) 273-2885, on the date indicated below.
`
`r:-.;Jgn.llllr\.'1
`
`(!),!lei
`
`I Al'l'I.J( 'A'I'ION NO.
`
`I
`
`12/')42,763
`
`HUNG DATE
`
`ll/(~)/2010
`
`I
`
`FIRST NA\1ED INVENTOR
`
`I AT'J'OlolNEY J)()( 'KI" Jl\( ), I ( 'ONI·IR.\1!\ II<)'\'\()
`
`.longwon Lee
`
`5649-29~5
`
`22'!..J
`
`TITLE OP INVENTION: METHODS OF FORMINO CMOS TRANSISTORS WITH HIGH CONDUCTIVITY GATE ELECTRODES
`
`APPLN.TYPE
`
`SMALL ENTITY
`
`ISSUE FEE DUE
`
`PUBLICATION FEE DUE PREY. PAID ISSUE FEE
`
`TOTAL FEE(S) DUE
`
`DATE DUE
`
`nonprovisional
`
`NO
`
`$1740
`
`$300
`
`$0
`
`$2040
`
`OW2..J/2012
`
`EXAMINER
`
`ART UNIT
`
`CLASS-SUBCLASS
`
`BROWJ\, VALERIEN
`
`2897
`
`438-592000
`
`I. Change of correspondence address or indication of "Pee Address'! (37
`CFR 1.363).
`0 Change of correspondence address (or Change of Correspondence
`Address form PTO/SB/122) attached.
`0 "Fee Address" indication (or "Fee Address" Indication form
`PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer
`Number is required.
`
`2. Par printing on the patent front page, list
`( l) the names of up to 3 registered patent attorneys
`or agents OR, alternatively,
`(2) the name of a single firm (having as a member a
`registered attorney or agent) and the names of up to
`2 registered patent attorneys or agents. If no name is
`listed, no name will be printed.
`
`!MYERS BIGEL SIBLEY
`& SAJOVEC ~__P. A'- __
`
`3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)
`PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the document has been filed for
`recordation as set forth in 37 CFR 3. I 1. Completion of this form is NOT a substitute for filing an assignment.
`(A) NAME OF ASSIGNEE
`(B) RESIDENCE: (CITY and STATE OR COUNTRY)
`
`Republic of Korea
`Samsung Electronics Co., Ltd.
`!'lease check the appropriate assignee category or categories (will not be printed on the patent): 0 Individual Ill Corporation or other private gnntp entity 0 (iuwrnmL·nt
`
`cia. The following fee(s) arc submitted:
`Ill Issue Fee
`~Publication Fee (No small entity discount permitted)
`0 Advance Order- #of Copies _________ _
`
`..Jb. Payment of Fee(s): (Please lirstt•capply any previously paid issm· fl'l· shown ahow)
`0 A check is enclosed.
`0 Payment by credit card. Form PT0-2038 is attached.
`!Zl The Director is hereby authorized to charge the required fee(s), any deficiency, or credit any
`overpayment, to Deposit Account Number 5 0 - 0 2 2 0( enclose an extra copy of this form).
`
`5. Change in Entity Status (from status indicated abpv )
`0 a. Applicant claims SMALL EN Y status/Se 37 CFR !.27.
`
`Date
`
`tT1l J y 2 4+ 2012
`
`Registration No. ~--225
`
`by :\7 CFR 1.:\ I I. The information is required to obtain or retain a benefit by the public which is to file (and hy the l 'S PTO to(''""'''" 1
`This rollection of information is re(Juir-
`an aprlication. Confidentiality is ~fncd by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering. prepanng, and
`submllting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to nHnpktc
`this form and/or sug~estions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Commerce, P.O
`Box 1450, Alexandna, Virginia 223I3-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. 13ox l..J50
`Alexandria, Virginia 22313-I450.
`'
`Under the Paperwork Reduction Act of 1995, no persons ;u·e required to respond to a collection of information unless it displays a valid OMB control number.
`
`PTOL-85 (Rev. 02/11) Approved for use through 08/3I/2013.
`
`OMB 0651-0033
`
`U.S. Patent and Trademark Office; U.S. DEPART:\I!ENT OF COM.\1ERCE
`
`NVIDIA Corp.
`Exhibit 1102
`Page 002
`
`

`
`Electronic Patent Application Fee Transmittal
`
`Application Number:
`
`Filing Date:
`
`12942763
`
`09-Nov-201 0
`
`Title of Invention:
`
`METHODS OF FORMING CMOS TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`First Named Inventor/Applicant Name:
`
`Jongwon Lee
`
`Filer:
`
`Grant J. Scott/Gwen Bailey
`
`Attorney Docket Number:
`
`5649-2985
`
`Filed as Large Entity
`
`Utility under 35 USC 111 (a) Filing Fees
`
`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USD($)
`
`Basic Filing:
`
`Pages:
`
`Claims:
`
`Miscellaneous-Filing:
`
`Petition:
`
`Patent-Appeals-and-Interference:
`
`Post-Allowance-and-Post-Issuance:
`
`Utility Appl issue fee
`
`Publ. Fee- early, voluntary, or normal
`
`1501
`
`1504
`
`1
`
`1
`
`1740
`
`300
`
`1740
`
`300
`
`NVIDIA Corp.
`Exhibit 1102
`Page 003
`
`

`
`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USD($)
`
`Extension-of-Time:
`
`Miscellaneous:
`
`Total in USD ($)
`
`2040
`
`NVIDIA Corp.
`Exhibit 1102
`Page 004
`
`

`
`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`13321396
`
`12942763
`
`International Application Number:
`
`Confirmation Number:
`
`2294
`
`Title of Invention:
`
`METHODS OF FORMING CMOS TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`First Named Inventor/Applicant Name:
`
`Jongwon Lee
`
`Customer Number:
`
`20792
`
`Filer:
`
`Grant J. Scott/Gwen Bailey
`
`Filer Authorized By:
`
`Grant J. Scott
`
`Attorney Docket Number:
`
`5649-2985
`
`Receipt Date:
`
`Filing Date:
`
`TimeStamp:
`
`24-JUL-2012
`
`09-NOV-201 0
`
`10:32:18
`
`Application Type:
`
`Utility under 35 USC 111 (a)
`
`Payment information:
`
`Submitted with Payment
`
`Payment Type
`
`Payment was successfully received in RAM
`
`RAM confirmation Number
`
`Deposit Account
`
`Authorized User
`
`File Listing:
`Document I
`Number
`
`yes
`
`Deposit Account
`
`$2040
`
`10996
`
`500220
`
`Document Description
`
`I
`
`File Name
`
`File Size( Bytes)/ I Multi ~I Pages
`(ifappl.)
`Message Digest
`Part /.zip
`
`I
`
`NVIDIA Corp.
`Exhibit 1102
`Page 005
`
`

`
`1
`
`Issue Fee Payment (PT0-85B)
`
`5649-2985_FeesTransmittal.pd
`
`no
`
`1
`
`155658
`
`Warnings:
`
`Information:
`
`671 d 15ac886a87f243b9f9e5f7 c702bc513c
`Odbl
`
`32380
`
`2
`
`Fee Worksheet (SB06)
`
`fee-info. pdf
`
`no
`
`2
`
`9e9ecd7c186117b4ba873376afe36c76460
`eedde
`
`Warnings:
`
`Information:
`
`Total Files Size (in bytes)
`
`188038
`
`This Acknowledgement Receipt evidences receipt on the noted date by the USPTO of the indicated documents,
`characterized by the applicant, and including page counts, where applicable. It serves as evidence of receipt similar to a
`Post Card, as described in MPEP 503.
`
`New A~~lications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary components for a filing date (see 37 CFR
`1.53(b)-(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date shown on this
`Acknowledgement Receipt will establish the filing date of the application.
`
`National Stage of an International A~~lication under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions of 35
`U.S.C. 371 and other applicable requirements a Form PCT/DO/E0/903 indicating acceptance of the application as a
`national stage submission under 35 U.S.C. 371 will be issued in addition to the Filing Receipt, in due course.
`
`New International A~~lication Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary components for
`an international filing date (see PCT Article 11 and MPEP 181 0), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/R0/1 OS) will be issued in due course, subject to prescriptions concerning
`national security, and the date shown on this Acknowledgement Receipt will establish the international filing date of
`the application.
`
`NVIDIA Corp.
`Exhibit 1102
`Page 006
`
`

`
`UNITED STA 1ES p A 1ENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`NOTICE OF ALLOWANCE AND FEE(S) DUE
`
`20792
`7590
`06/22/2012
`MYERS BIGEL SIBLEY & SAJOVEC
`PO BOX 37428
`RALEIGH, NC 27627
`
`EXAMINER
`
`BROWN, VALERIEN
`
`ART UNIT
`
`PAPER NUMBER
`
`2897
`
`DATE MAILED: 06/22/2012
`
`APPLICATION NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`12/942,763
`
`11109/2010
`
`JongwonLee
`
`5649-2985
`
`2294
`
`TITLE OF INVENTION: METHODS OF FORMING CMOS TRANSISTORS WITH HIGH CONDUCTIVITY GATE ELECTRODES
`
`APPLN. TYPE
`
`SMALL ENTITY
`
`ISSUE FEE DUE
`
`PUBLICATION FEE DUE PREV. PAID ISSUE FEE
`
`TOTAL FEE(S) DUE
`
`DATE DUE
`
`nonprovisiona1
`
`NO
`
`$1740
`
`$300
`
`$0
`
`$2040
`
`09/24/2012
`
`THE APPLICATION IDENTIFIED ABOVE HAS BEEN EXAMINED AND IS ALLOWED FOR ISSUANCE AS A PATENT.
`PROSECUTION ON THE MERITS IS CLOSED. THIS NOTICE OF ALLOWANCE IS NOT A GRANT OF PATENT RIGHTS.
`THIS APPLICATION IS SUBJECT TO WITHDRAWAL FROM ISSUE AT THE INITIATIVE OF THE OFFICE OR UPON
`PETITION BY THE APPLICANT. SEE 37 CFR 1.313 AND MPEP 1308.
`
`THE ISSUE FEE AND PUBLICATION FEE (IF REQUIRED) MUST BE PAID WITHIN THREE MONTHS FROM THE
`MAILING DATE OF THIS NOTICE OR THIS APPLICATION SHALL BE REGARDED AS ABANDONED.
`THIS
`STATUTORY PERIOD CANNOT BE EXTENDED. SEE 35 U.S.C. 151. THE ISSUE FEE DUE INDICATED ABOVE DOES
`NOT REFLECT A CREDIT FOR ANY PREVIOUSLY PAID ISSUE FEE IN THIS APPLICATION.
`IF AN ISSUE FEE HAS
`PREVIOUSLY BEEN PAID IN THIS APPLICATION (AS SHOWN ABOVE), THE RETURN OF PART B OF THIS FORM
`WILL BE CONSIDERED A REQUEST TO REAPPLY THE PREVIOUSLY PAID ISSUE FEE TOWARD THE ISSUE FEE NOW
`DUE.
`
`HOW TO REPLY TO THIS NOTICE:
`
`L Review the SMALL ENTITY status shown above,
`
`If the SMALL ENTITY is shown as YES, verify your current
`SMALL ENTITY status:
`
`A, If the status is the same, pay the TOTAL FEE(S) DUE shown
`above,
`B, If the status above is to be removed, check box 5b on Part B -
`Fee(s) Transmittal and pay the PUBLICATION FEE (if required)
`and twice the amount of the ISSUE FEE shown above, or
`
`If the SMALL ENTITY is shown as NO:
`
`A, Pay TOTAL FEE(S) DUE shown above, or
`
`B, If applicant claimed SMALL ENTITY status before, or is now
`claiming SMALL ENTITY status, check box Sa on Part B - Fee(s)
`Transmittal and pay the PUBLICATION FEE (if required) and l/2
`the ISSUE FEE shown above,
`
`IL PART B- FEE(S) TRANSMITTAL, or its equivalent, must be completed and returned to the United States Patent and Trademark Office
`(USPTO) with your ISSUE FEE and PUBLICATION FEE (if required), If you are charging the fee(s) to your deposit account, section "4b"
`of Part B - Fee(s) Transmittal should be completed and an extra copy of the form should be submitted, If an equivalent of Part B is filed, a
`request to reapply a previously paid issue fee must be clearly made, and delays in processing may occur due to the difficulty in recognizing
`the paper as an equivalent of Part B,
`
`IlL All communications regarding this application must give the application number, Please direct all communications prior to issuance to
`Mail Stop ISSUE FEE unless advised to the contrary,
`
`IMPORTANT REMINDER: Utility patents issuing on applications filed on or after Dec. 12, 1980 may require payment of
`maintenance fees. It is patentee's responsibility to ensure timely payment of maintenance fees when due.
`
`PTOL-85 (Rev, 02/11)
`
`Pagel of3
`
`NVIDIA Corp.
`Exhibit 1102
`Page 007
`
`

`
`PART B- FEE(S) TRANSMITTAL
`
`Complete and send this form, together with applicable fee(s), to: Mail
`
`or Fax
`
`Mail Stop ISSUE FEE
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`(571)-273-2885
`
`INSTRUCTIONS: This form should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks l through 5 should be completed where
`appropriate. All further correspondence including the Patent, advance orders and notification of maintenance fees will be mailed to the current correspondence address as
`indicated unless corrected below or directed otherwise in Block l, by (a) specifying a new correspondence address; and/or (b) indicating a separate "FEE ADDRESS" for
`maintenance fee notifications.
`CURRENT CORRESPONDENCE ADDRESS (Note: Use Block 1 for any change of address)
`
`20792
`7590
`06/22/2012
`MYERS BIGEL SIBLEY & SAJOVEC
`PO BOX 37428
`RALEIGH, NC 27627
`
`Note: A certificate of mailing can only be used for domestic mailings of the
`Fee(s) Transmittal. This certificate cannot be used for any other accompanying
`papers. Each additional paper, such as an assignment or formal drawing, must
`have its own certificate of mailing or transmission.
`
`Certificate of Mailing or Transmission
`I hereby certify that this Fee(s) Transmittal is being deposited with the United
`States Postal Service with sufficient postage for first class mail in an envelope
`addressed to the Mail Stop ISSUE FEE address above, or being facsimile
`transmitted to the USPTO (571) 273-2885, on the date indicated below.
`
`(Depositor's name)
`
`(Signature)
`
`(Date)
`
`I
`
`APPLICATION NO.
`
`12/942,763
`
`I
`
`FILING DATE
`
`ll/09/2010
`
`I
`
`FIRST NAMED INVENTOR
`
`I ATTORNEYDOCKETNO. I CONFIRMATION NO.
`
`JongwonLee
`
`5649-2985
`
`2294
`
`TITLE OF INVENTION: METHODS OF FORMING CMOS TRANSISTORS WITH HIGH CONDUCTIVITY GATE ELECTRODES
`
`APPLN. TYPE
`
`SMALL ENTITY
`
`ISSUE FEE DUE
`
`PUBLICATION FEE DUE PREV. PAID ISSUE FEE
`
`TOTAL FEE(S) DUE
`
`DATE DUE
`
`nonprovisional
`
`NO
`
`$1740
`
`$300
`
`$0
`
`$2040
`
`09/24/2012
`
`EXAMINER
`
`ART UNIT
`
`CLASS-SUBCLASS
`
`BROWN, VALERIEN
`
`2897
`
`438-592000
`
`l. Change of correspondence address or indication of "Fee Address" (37
`CFR 1.363).
`0 Change of correspondence address (or Change of Correspondence
`Address form PTO/SB/122) attached.
`0 "Fee Address" indication (or "Fee Address" Indication form
`PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer
`Number is required.
`
`2. For printing on the patent front page, list
`(l) the names of up to 3 registered patent attorneys
`or agents OR, alternatively,
`(2) the name of a single firm (having as a member a
`registered attorney or agent) and the names of up to
`2 registered patent attorneys or agents. If no name is
`listed, no name will be printed.
`
`2 ________________________ __
`
`3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)
`PLEASE NOTE: Unless an asstgnee 1s tdenlifted below, no asstgnee data w1ll appear on the patent. If an assignee is identified below, the document has been filed for
`recordation as set forth m 37 CFR 3.11. Completion of this form is NOT a substitute for filing an assignment.
`(A) NAME OF ASSIGNEE
`(B) RESIDENCE: (CITY and STATE OR COUNTRY)
`
`Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual 0 Corporation or other private group entity 0 Government
`
`4a. The following fee(s) are submitted:
`0 Issue Fee
`0 Publication Fee (No small entity discount permitted)
`0 Advance Order- #of Copies __________________ _
`
`4b. Payment ofFee(s): (Please first reapply any previously paid issue fee shown above)
`0 A check is enclosed.
`0 Payment by credit card. Form PT0-2038 is attached.
`0 The Director is hereby authorized to charge the required fee(s), any deficiency, or credit any
`overpayment, to Deposit Account Number
`(enclose an extra copy of this form).
`
`5. Change in Entity Status (from status indicated above)
`0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR l.27(g)(2).
`0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27.
`NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the applicant; a registered attorney or agent; or the assignee or other party in
`interest as shown by the records of the United States Patent and Trademark Office.
`
`Authorized Signature -----------------------------------------------
`
`Date ________________________________________ __
`
`Typed or printed name ----------------------------------------------
`
`Registration No. ---------------------------------
`
`This collection of information is required by 37 CFR 1.311. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to process)
`an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering, preparing, and
`submitting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you require to complete
`this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Commerce, P.O.
`Box 1450, Alexandria, Virginia 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 1450,
`Alexandria, Virginia 22313-1450.
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.
`
`PTOL-85 (Rev. 02/ll) Approved for use through 08/3112013.
`
`OMB 0651-0033
`
`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`
`NVIDIA Corp.
`Exhibit 1102
`Page 008
`
`

`
`UNITED STA 1ES p A 1ENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`12/942,763
`
`11109/2010
`
`JongwonLee
`
`5649-2985
`
`2294
`
`20792
`7590
`06/22/2012
`MYERS BIGEL SIBLEY & SAJOVEC
`PO BOX 37428
`RALEIGH, NC 27627
`
`EXAMINER
`
`BROWN, VALERIEN
`
`ART UNIT
`
`PAPER NUMBER
`
`2897
`
`DATE MAILED: 06/22/2012
`
`Determination of Patent Term Adjustment under 35 U.S.C. 154 (b)
`(application filed on or after May 29, 2000)
`
`The Patent Term Adjustment to date is 0 day(s). If the issue fee is paid on the date that is three months after the
`mailing date of this notice and the patent issues on the Tuesday before the date that is 28 weeks (six and a half
`months) after the mailing date of this notice, the Patent Term Adjustment will be 0 day(s).
`
`If a Continued Prosecution Application (CPA) was filed in the above-identified application, the filing date that
`determines Patent Term Adjustment is the filing date of the most recent CPA.
`
`Applicant will be able to obtain more detailed information by accessing the Patent Application Information Retrieval
`(PAIR) WEB site (http://pair.uspto.gov).
`
`Any questions regarding the Patent Term Extension or Adjustment determination should be directed to the Office of
`Patent Legal Administration at (571)-272-7702. Questions relating to issue and publication fee payments should be
`directed to the Customer Service Center of the Office of Patent Publication at 1-(888)-786-0 101 or (571 )-272-4200.
`
`PTOL-85 (Rev. 02/11)
`
`Page 3 of3
`
`NVIDIA Corp.
`Exhibit 1102
`Page 009
`
`

`
`Privacy Act Statement
`
`The Privacy Act of 1974 (P.L. 93-579) requires that you be given certain information in connection with
`your submission of the attached form related to a patent application or patent. Accordingly, pursuant to
`the requirements of the Act, please be advised that: (1) the general authority for the collection of this
`information is 35 U.S.C. 2(b )(2); (2) furnishing of the information solicited is voluntary; and (3) the
`principal purpose for which the information is used by the U.S. Patent and Trademark Office is to process
`and/or examine your submission related to a patent application or patent. If you do not furnish the
`requested information, the U.S. Patent and Trademark Office may not be able to process and/or examine
`your submission, which may result in termination of proceedings or abandonment of the application or
`expiration of the patent.
`
`The information provided by you in this form will be subject to the following routine uses:
`
`1. The information on this form will be treated confidentially to the extent allowed under the Freedom
`of Information Act (5 U.S.C. 552) and the Privacy Act (5 U.S.C 552a). Records from this system of
`records may be disclosed to the Department of Justice to determine whether disclosure of these
`records is required by the Freedom of Information Act.
`2. A record from this system of records may be disclosed, as a routine use, in the course of presenting
`evidence to a court, magistrate, or administrative tribunal, including disclosures to opposing counsel
`in the course of settlement negotiations.
`3. A record in this system of records may be disclosed, as a routine use, to a Member of Congress
`submitting a request involving an individual, to whom the record pertains, when the individual has
`requested assistance from the Member with respect to the subject matter of the record.
`4. A record in this system of records may be disclosed, as a routine use, to a contractor of the Agency
`having need for the information in order to perform a contract. Recipients of information shall be
`required to comply with the requirements of the Privacy Act of 1974, as amended, pursuant to 5
`U.S.C. 552a(m).
`5. A record related to an International Application filed under the Patent Cooperation Treaty in this
`system of records may be disclosed, as a routine use, to the International Bureau of the World
`Intellectual Property Organization, pursuant to the Patent Cooperation Treaty.
`6. A record in this system of records may be disclosed, as a routine use, to another federal agency for
`purposes of National Security review (35 U.S.C. 181) and for review pursuant to the Atomic Energy
`Act (42 U.S.C. 218(c)).
`7. A record from this system of records may be disclosed, as a routine use, to the Administrator,
`General Services, or his/her designee, during an inspection of records conducted by GSA as part of
`that agency's responsibility to recommend improvements in records management practices and
`programs, under authority of 44 U.S.C. 2904 and 2906. Such disclosure shall be made in accordance
`with the GSA regulations governing inspection of records for this purpose, and any other relevant
`(i.e., GSA or Commerce) directive. Such disclosure shall not be used to make determinations about
`individuals.
`8. A record from this system of records may be disclosed, as a routine use, to the public after either
`publication of the application pursuant to 35 U.S.C. 122(b) or issuance of a patent pursuant to 35
`U.S.C. 151. Further, a record may be disclosed, subject to the limitations of 37 CPR 1.14, as a
`routine use, to the public if the record was filed in an application which became abandoned or in
`which the proceedings were terminated and which application is referenced by either a published
`application, an application open to public inspection or an issued patent.
`9. A record from this system of records may be disclosed, as a routine use, to a Federal, State, or local
`law enforcement agency, if the USPTO becomes aware of a violation or potential violation of law or
`regulation.
`
`NVIDIA Corp.
`Exhibit 1102
`Page 010
`
`

`
`Notice of Allowability
`
`Application No.
`
`12/942,763
`Examiner
`
`Applicant(s)
`
`LEE ET AL.
`Art Unit
`
`VALERIEN. BROWN
`
`2897
`
`-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address-(cid:173)
`All claims being allowable, PROSECUTION ON THE MERITS IS (OR REMAINS) CLOSED in this application. If not included
`herewith (or previously mailed), a Notice of Allowance (PTOL-85) or other appropriate communication will be mailed in due course. THIS
`NOTICE OF ALLOW ABILITY IS NOT A GRANT OF PATENT RIGHTS. This application is subject to withdrawal from issue at the initiative
`of the Office or upon petition by the applicant. See 37 CFR 1.313 and MPEP 1308.
`1. [8J This communication is responsive to 02/28112.
`2. D An election was made by the applicant in response to a restriction requirement set forth during the interview on __ ;
`the restriction requirement and election have been incorporated into this action.
`3. [8J The allowed claim(s) is/are 1-5 and21-30.
`4. D Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`a) D All
`b) D Some*
`c) D None
`of the:
`1. D Certified copies of the priority documents have been received.
`2. D Certified copies of the priority documents have been received in Application No. __ .
`3. D Copies of the certified copies of the priority documents have been received in this national stage application from the
`International Bureau (PCT Rule 17.2(a)).
`* Certified copies not received: __ .
`
`Applicant has THREE MONTHS FROM THE "MAILING DATE" of this communication to file a reply complying with the requirements
`noted below. Failure to timely comply will result in ABANDONMENT of this application.
`THIS THREE-MONTH PERIOD IS NOT EXTENDABLE.
`5. 0 A SUBSTITUTE OATH OR DECLARATION must be submitted. Note the attached EXAMINER'S AMENDMENT or NOTICE OF
`INFORMAL PATENT APPLICATION (PT0-152) which gives reason(s) why the oath or declaration is deficient.
`6. D CORRECTED DRAWINGS (as "replacement sheets") must be submitted.
`(a) D including changes required by the Notice of Draftsperson's Patent Drawing Review ( PT0-948) attached
`1) D hereto or 2) D to Paper No./Mail Date __ .
`(b) D including changes required by the attached Examiner's Amendment I Comment or in the Office action of
`Paper No./Mail Date __ .
`Identifying indicia such as the application number {see 37 CFR 1.84{c)) should be written on the drawings in the front {not the back) of
`each sheet. Replacement sheet{s) should be labeled as such in the header according to 37 CFR 1.121 {d).
`7. 0 DEPOSIT OF and/or INFORMATION about the deposit of BIOLOGICAL MATERIAL must be submitted. Note the
`attached Examiner's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.
`
`Attachment(s)
`1. D Notice of References Cited (PT0-892)
`2. D Notice of Draftperson's Patent Drawing Review (PT0-948)
`3. D Information Disclosure Statements (PTO/SB/08),
`Paper No./Mail Date __
`4. D Examiner's Comment Regarding Requirement for Deposit
`of Biological Material
`
`5. D Notice of Informal Patent Application
`6. D Interview Summary (PT0-413),
`Paper No./Mail Date __ .
`7. D Examiner's Amendment/Comment
`
`8. [8J Examiner's Statement of Reasons for Allowance
`9. D Other __ .
`
`U.S. Patent and Trademark Off1ce
`PTOL-37 (Rev. 03·11)
`
`Notice of Allowability
`
`Part of Paper No./Mail Date 20120612
`
`NVIDIA Corp.
`Exhibit 1102
`Page 011
`
`

`
`Application/Control Number: 12/942,763
`Art Unit: 2897
`
`Page 2
`
`REASONS FOR ALLOWANCE
`
`1.
`
`The following is an examiner's statement of reasons for allowance: Claim 1 recites
`
`forming a metal buffer gate electrode layer on the gate insulating layer; forming a dummy gate
`
`electrode on the buffer gate electrode layer, said dummy gate electrode layer and said buffer gate
`
`electrode layer comprising different materials gate insulating layer; patterning the dummy gate
`
`electrode layer and the buffer gate electrode layer in sequence to define a buffer gate electrode
`
`on the gate insulating layer and a dummy gate electrode on the buffer gate electrode and filling a
`
`space between the inner sidewalls of the spacers by depositing a second metal layer onto a
`
`portion of the first metal layer extending between the inner sidewalls of the spacers to thereby
`
`define a metal gate electrode comprising a composite of the second metal layers layer, a portion
`
`of the first metal layer having aU -shaped cross-section and the buffer gate electrode. These
`
`limitations in combination with the other limitations as set forth in the claims are neither taught
`
`nor suggested in the prior art. Claims 2-5 depend from claim 1 and are allowable for at least that
`
`reason.
`
`2.
`
`Claim 21 recites the limitations forming a first metal gate electrode layer on the gate
`
`insulating layer; forming a dummy gate electrode layer on the first metal gate electrode layer,
`
`said dummy gate electrode layer and said first metal gate electrode layer comprising different
`
`materials; patterning the dummy gate electrode layer and the first metal gate electrode layer in
`
`sequence to define a dummy gate electrode on the patterned first metal gate electrode layer and
`
`planarizing the third metal gate electrode layer and the second metal gate electrode layer to
`
`thereby define a composite metal gate electrode of a PMOS transistor between the inner
`
`NVIDIA Corp.
`Exhibit 1102
`Page 012
`
`

`
`Application/Control Number: 12/942,763
`Art Unit: 2897
`
`Page 3
`
`sidewalls of the spacers, said composite metal gate electrode comprising a portion of the third
`
`metal gate electrode layer, a portion of the second metal gate electrode layer hav