United States Patent [19]
`Lee et al.
`
`I lllll IHllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US005761138A
`[11J Patent Number:
`[45J Date of Patent:
`
`5,761,138
`Jun.2, 1998
`
`[54) MEMORY DEVICES HAVING A FLEXIBLE
`REDUNDANT BLOCK ARCHITECTURE
`
`[75)
`
`Inventors: Kyu-Chan Lee. Seoul; Keum-Yong
`Kim. Kyungki-do. both of Rep. of
`Korea
`
`[73) Assignee: Samsung Electronics Co., Ltd •.
`Suwon, Rep. of Korea
`
`[21) Appl. No.: 754,673
`
`[22) Filed:
`
`Nov. 21, 1996
`
`[30)
`
`Foreign Application Priority Data
`
`Nov. 22, 1995
`
`[KR) Rep. of Korea .................. 42985/1995
`
`Int. CI.6
`................................. GllC 7/00; GllC 8/00
`[51)
`[52) U.S. CI ................ 365/200; 3651230.03; 365/189.08;
`365/225.7
`[58) Field of Search ............................... 3651200. 230.02.
`365/230.03. 189.02. 189.08. 225.7
`
`[56)
`
`References Cited
`
`U.S. PATENf DOCUMENfS
`
`5,045,720
`
`9/1991 Bae .................................... 365/230.06
`
`Primary Emminer-David C. Nelms
`Assistant Examiner-Trong Phan
`Attome}; Agent, or Firm-Myers Bigel Sibley & Sajovec
`ABSTRACT
`
`[57]
`
`A memory device includes a plurality of data input/output
`(110) lines and means for receiving a column address. The
`memory device also includes a plurality of primary memory
`cells. a selected primary memory cell of the plurality of
`primary memory cells being connected to a primary global
`IJO line in response to receipt of one column address. and a
`plurality of redundant memory cells. a selected redundant
`memory cell of the plurality of redundant memory cells
`being connected to a redundant global I/O line in response
`to receipt of the one column address. One of the primary
`global I/O line and the redundant global I/O line are selec(cid:173)
`tively connected to one of the plurality of data 110 lines such
`that one of the selected primary memory cell and the
`selected redundant memory cell is connected to the one data
`IJO line to thereby enable data transfer therebetween. pref(cid:173)
`erably by enabling one of a primary I/O sense amplifier and
`a redundant 110 sense amplifier connected to the primary
`and redundant global I/O lines. respectively.
`
`4,807,191
`
`2/1989 Flannagan ............................... 365/200
`
`12 Claims, 7 Drawing Sheets
`
`,_.....____
`
`,---J----.
`
`,.........._,
`
`UIOBI
`UIOBK
`~ ,--'---,
`GIOK RGIOK GIOI RGI~
`
`,..........__,
`
`UIOBi
`... ------------ ----GRli ______ ------
`r"-.
`
`UI09j
`
`GIOj
`,..,--,
`
`:sm{
`
`SIO{
`
`300
`~
`
`~{
`
`~o{i
`
`[._ __________ ----------------- ------------ _____ ...J
`
`'
`
`MICRON-1003.001
`
`

`
`Vee
`PULL-UP
`CIRCUIT
`
`e •
`
`rJJ.
`•
`
`~ ---- --- --- =~
`~ ---- --- ---
`
`4
`
`MS1
`MS2
`3 MS3
`MS4
`
`t/JSC t/JY
`~
`COL ADD
`
`1
`SPARE
`COLUMN
`DECODER
`~--00
`11
`t/JSCD
`
`<- ~-- ---~---- '
`- --- -------- ~~ 4
`MS1
`MS2
`MS3
`MS4
`
`3
`
`r- ---- --- ---- ---,
`100-J
`~·--..__~~~---lf---+--~--f--+---1
`
`I
`
`6
`
`MN1
`MN2
`MN3
`MN4
`
`FIG. 1 -r ==== === === =)
`(PRIOR ART)
`
`5
`
`11
`
`NORMAL
`COLUMN
`DECODER
`t/JNCD
`
`........,,....-i--4-4__.
`
`MN1
`MN2
`MN3
`MN4
`
`6
`
`<: --- --- ---- ~
`---- --- ---- ~
`.
`.
`.
`.
`5
`
`MICRON-1003.002
`
`

`
`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 2 of 7
`
`5,761,138
`
`u
`rl.l
`Q
`
`Q u z Q
`
`MICRON-1003.003
`
`

`
`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 3 of 7
`
`5,761,138
`
`UIOBi
`:---------~-------GiOi _____________________ RGibi------~
`i
`.
`,.._,
`RSIO
`,.._,
`---~--·------
`t(S4'1 1)~1
`,,
`SA1
`1·
`I ...
`"
`
`I
`
`SA2
`
`I
`I
`
`I
`I
`I
`I
`II
`
`I
`I
`
`I :s10{
`
`I
`
`.
`
`I
`I
`I
`I
`I
`I
`
`I :s10{
`
`'
`'
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`is10{
`
`300
`~
`
`BL/BLB
`/
`
`MCA1
`
`SA3
`
`BL/BLB
`/
`
`MCA3
`
`SAS
`
`T
`
`I
`
`MCA2 IK ~ ~1
`.
`
`~
`
`5
`
`SA4
`
`I
`
`RS~~
`~ .:
`
`I
`I
`I
`I
`II
`
`MCA4
`
`I( ~AZ
`
`E
`
`I-
`
`t.
`
`"
`
`s
`
`~
`
`I
`
`SA6
`
`--,
`
`I
`
`RSIO
`t<>- l31\'i
`"
`
`I
`I
`I
`l
`I I
`
`v _ ...
`.... ,_,_
`
`39
`
`. d•
`
`~
`
`. 41
`:
`I ~ .... ,_
`k
`I
`
`,__,_,__
`
`I
`
`44
`
`l!L\'lhu
`I I:
`'~• ~I OSE !IC t;, 1 R o~ &J 21~0: tJ 31
`IOSE
`~"" ..
`y
`IJ " E
`I~, i
`J 11
`.
`)>
`-h J4
`> s ~
`..... ;
`~I)
`~
`~ ~ J
`aJ =
`~
`
`,..._~~
`
`RO~' 41
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`!
`I
`I
`
`~ '4l
`
`I
`
`I•
`
`I
`---------------------------------------------------~
`
`FIG. 3A
`
`MICRON-1003.004
`
`

`
`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 4 of 7
`
`5,761,138
`
`UIOBj
`UIOBI
`UIOBK
`r-----------------------------------------------1 ~ ~
`:
`.
`GIOj
`.
`RGIOj
`GIOK RGIOK GIOI RGIOI
`.
`r'-.
`r'-.
`,-J-..
`,-A-,
`,.--A-.
`,.--A-.
`1111 111 I I II f 1111
`SA2
`
`I
`I
`I
`I
`I
`
`{
`
`I
`
`'SIO
`
`--i--~-----
`SA1
`
`/
`·~
`
`I
`I
`
`I
`
`RSIO
`K~~l \\
`L
`'
`
`I
`I \I
`\I
`
`MCA2 t(l ,1 11
`
`.... •••
`R~
`SA4 ~~. I
`
`I
`
`I
`I
`
`\ I
`\I
`
`I
`
`MCA4 KW
`
`~
`
`... .. •••
`~~~,
`SAS K~
`
`I
`
`I
`
`;
`
`I
`
`1.
`
`I
`
`I
`
`BL/BLB
`/
`
`MCA1
`
`~····
`SA3
`•
`-.
`
`I
`I
`I
`
`:510{
`
`BL/BLB
`/
`
`~
`
`MCA3 ......
`SAS
`-.
`
`I
`
`SIO{
`
`I
`
`3
`
`\ 00,
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`
`I
`
`1 :
`
`I
`
`-
`. L--- --- -- - --- I
`l rr 1
`~ I 'rlR:oSE ~061 1 R ):~)2 RO~ &J 3
`
`~
`
`"
`
`I I
`\/
`
`-
`
`I
`I
`I
`
`I
`I
`I
`I
`
`>: ~' 41
`
`: 41
`
`II
`
`,,
`
`1 v
`
`
`
`39
`
`h
`
`-
`b' 1
`
`,~
`
`•
`~
`13 ,
`8 IJ LI ~ ~ Ii
`J
`>1
`-~
`._.
`0
`J
`,!".( g
`>
`~~
`~ '
`~
`
`al
`r-
`(J)
`'-•
`
`3'
`4,
`I
`L-----------------------------------------------~
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`
`I
`
`.-.
`
`I
`I
`I
`I
`
`\
`I
`T
`I
`
`I
`
`I
`
`,I
`
`/
`DIOi"'DIOI
`"""'""010
`
`·~ ~-i~J
`~00
`
`FIG. 3B
`
`MICRON-1003.005
`
`

`
`63
`62
`61
`60
`r ____________________ l ___________________ , r ____________________ l ___________________ , r __ J ____ , , ___ l ___ ,
`
`d •
`\JJ. •
`
`CF1
`
`CF2
`
`CF3
`
`CF4
`
`Ai AjAk Al Ai AjAk Al Ai AjAk Al Ai AjAk Al
`I
`I
`
`I
`
`I
`
`I
`I
`I
`I
`I
`I
`I
`
`I
`I
`I
`
`CFS
`
`CF6
`
`CF7
`
`CFS
`
`: AIAkAj Ai AIAkAj Ai AIAkAj Ai Al AkAj Ai
`I
`I
`
`I
`
`I
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`6~
`
`I
`I
`I
`L
`
`_.._
`70
`
`....
`-55
`68
`'if'
`~
`~
`--- ---------- ---------- ---------- ___ J
`
`__ .._
`_ .._
`72
`74
`'i( I Y ~
`
`.._ _
`+a
`76
`1' Vi
`
`I
`I
`
`---------- ---------- ---------- ___ J
`
`L--
`
`I
`I
`I
`
`I
`I
`
`-
`
`- r_J
`
`L __ rT
`
`_ _J
`
`~~ 92 ~I
`
`(
`400
`
`I
`I
`I
`
`I
`I
`
`I
`
`I
`
`~~1t0c1e
`~t~~111r:~~
`FIG. 4
`
`ID
`I
`(./)
`fu
`
`OJ
`I
`(./)
`tD
`
`ID
`I
`<.n
`ffi
`
`CD
`I
`<.n
`CD
`
`MICRON-1003.006
`
`

`
`U.S. Patent
`
`•
`
`I
`I
`I
`
`CF1 -...J I
`
`Jun. 2, 1998
`Sheet 6 of 7
`r-------------------------------------------------1
`r--vcr.--------------1
`52 1
`i
`111
`'
`'
`I
`I
`'
`'
`I
`I
`.
`.
`! 64
`D-+-! - !
`! "'
`!
`l
`I
`'
`'
`I
`I
`_____ J
`'
`'
`L_
`-----1
`,-
`54--
`
`5,761,138
`
`Ai
`
`Aj
`
`_ ____ J
`-----1
`I
`I
`' I
`' I
`I
`I
`' I
`_ ____ J
`-----1
`
`L_
`ss-f-
`' I
`I
`' I
`' I
`' I
`' I
`' L_
`sa-f-
`' I
`' I
`I
`' I
`' .
`I .
`L_Ys!?________ _ ____ J
`REDUNDANT C(l..UMN
`RCSL
`50
`SELECT SIGNAL GENERA TING
`L-------------------------------------------------
`FIG. 5
`
`1
`
`1
`
`RESET
`
`I
`
`Ak
`
`Al
`
`MICRON-1003.007
`
`

`
`RASB
`
`CASB
`
`ADDR
`
`tl)YE
`
`RCSL
`
`RESET
`
`(BLSiB/BI.SjB/BIBkB/BIBIB)
`
`tl)RIOSEi
`
`BL/BLB
`
`RSIO/RSIOB
`
`RGIO/RGIOB
`
`DIO/DIOB
`
`Cj
`•
`r..n •
`~
`
`= "'""" ~ =
`
`"'"""
`
`~
`
`~
`N
`'°
`lo-' "" "" QO
`
`r:r.;
`t:r'
`!'D
`
`!'D ...
`........
`~
`........
`
`fJI
`-..
`.....:a
`~
`~ -..
`~
`~
`CIJ
`
`FIG. 6
`
`MICRON-1003.008
`
`

`
`1
`MEMORY DEVICES HAVING A FLEXIBLE
`REDUNDANT BLOCK ARCHITECTURE
`
`5.761.138
`
`FIELD OF THE INVENTION
`The present invention relates to microelectronic devices. 5
`more particularly. to memory devices.
`
`BACKGROUND OF THE INVENTION
`As memory devices become more highly integrated,
`including an increasing number of memory cells and asso(cid:173)
`ciated circuitry. the probability of a given device including
`one or more defective cells and/or associated circuitry
`generally has increased. Because of this increased
`likelihood. it has become desirable to use redundant struc(cid:173)
`tures to allow devices with failed cells or other circuits to be
`utilized. Conventional techniques typically involve replac(cid:173)
`ing a primary memory array having a failed cell with a spare
`array and/or replacing a failed bit line associated with a
`failed cell with a corresponding spare bit line in a spare
`array. Unfortunately. replacing an entire array with a spare 20
`array can be inefficient. wasting precious space on the chip.
`A conventional redundant memory architecture is
`described in U.S. Pat. No. 5.045.720 to Bae. FIG. 1 is
`illustrative of this architecture. showing a spare column
`selection circuit 100 in which a line switch pair lOa, lOb for
`a spare column selection is connected between normal
`input/output (I/0) lines 5 coupled to normal bit line pairs 6.
`and spare 1/0 lines 4 coupled to spare bit line pairs 3. The
`line switch pair lOa. lOb is responsive to a clock pulse $D
`output from a spare column decoder 1. A normal I/O line
`pull-up pair 20a. 20b connected between the normal 110
`lines 5 and a power supply voltage V cc is driven in response
`to the inactivation of the clock pulse cjlD. An inverter 11
`connected to the output node of the spare column decoder 1 35
`outputs a clock pulse <i>SCD which has an inverted phase
`with respect to the clock pulse cjlD. This clock pulse $SCD
`drives NMOS transistors MS1-MS4. the channels of which
`are connected between the spare I/O lines 4 and the spare bit
`line pairs 3, thereby connecting the spare I/O lines 4 to the 40
`spare bit line pairs 3.
`To access the normal bit line pairs 6. upon assertion of a
`row address strobe signal RASB and a column address
`strobe signal CASB to logic "low" levels. an externally
`applied row address and column address are latched and a 45
`clock pulse <I> Y is then generated. completing an operation of
`sensing a potential between the normal bit line pairs 6. as is
`commonly performed in memory devices and well known to
`those skilled in the art. Sensed data on the normal bit line
`pairs 6 is then transferred to the line switch pairs lOa.lOb via 50
`the NMOS transistors MN1-MN4. which are turned on in
`response to assertion of a clock pulse cjJNCD output from a
`normal column decoder 11.
`The clock pulse cjlD output from the spare column decoder
`1 remains at a logic "high." thus maintaining the line switch
`pairs lOaJOb in an "on" state. and allowing the data to be
`transferred to the I/O lines 4.
`As illustrated in FIG. 2. to access the spare bit line pairs
`3. the clock signal <i>D output from the spare column decoder
`1 is taken to a logic "low." thus turning off the line switch
`pairs 10a-10b. Thus. the normal bit line pairs 6 are isolated
`from the normal I/O lines 5. The inverted clock signal <i>SCD
`output from the inverter 11 goes to a logic "high" level.
`turning on the NMOS transistors MS1-MS4. allowing data
`on the pare bit line pairs 3 to be transferred to the spare I/O
`lines 4. Typically. the operation of the spare column decoder
`1 and the normal column decoder 11 is controlled by fuses
`
`2
`or other programmable elements. Because the decoding
`operations in the spare column decoder 1 and the normal
`column decoder 11 can occur in parallel. loss in speed in
`using the spare decoder 1 and associated structures can be
`reduced. In addition. during the read mode of the device. the
`spare bit line pair 3 and the normal bit line pair 6 can be
`isolated. providing for a reduced loading effect and enabling
`high speed operation. However. the flexibility of the redun(cid:173)
`dancy offered by this and similar conventional techniques
`10 may be limited due to the shared path between the normal
`IJO lines 5 and the spare I/O lines 4.
`
`SUMMARY OF THE INVENTION
`
`In light of the foregoing. it is an object of the present
`15 invention to provide memory devices which offer greater
`flexibility in providing redundant memory capacity.
`This and other objects. features and advantages are pro-
`vided according to the present invention by memory devices
`including a plurality of blocks of primary cells which are
`selectively connected to a corresponding plurality of pri(cid:173)
`mary input/output (I/0) sense amplifiers which drive a data
`110 bus. and a plurality of blocks of redundant memory cells
`which are selectively connected to a plurality of blocks of
`25 redundant 110 sense amplifiers connected to the data 110.
`and in which the primary 110 sense amplifiers and the
`redundant 110 sense amplifiers are selectively enabled
`according to a received column address and a predetermined
`mapping. The mapping allows substitution of a redundant
`30 memory cell from any of the blocks of redundant memory
`cells. and its associated data path. to substitute for a defec(cid:173)
`tive primary memory cell in any one of the blocks of primary
`memory cells. Memory devices with a flexible. redundant
`block architecture are thereby provided.
`In particular. according to the present invention. a
`memory device includes a plurality of data input/output
`(110) lines and means for receiving a column address. The
`memory device also includes a plurality of primary memory
`cells. a selected primary memory cell of the plurality of
`primary memory cells being connected to a primary global
`IJO line in response to receipt of one column address. and a
`plurality of redundant memory cells. a selected redundant
`memory cell of the plurality of redundant memory cells
`being connected to a redundant global I/O line in response
`to receipt of the one column address. Means selectively
`connecting one of the primary global I/O line and the
`redundant global YO line to one of the plurality of data 1/0
`lines such that one of the selected primary memory cell and
`the selected redundant memory cell is connected to the one
`data YO line to thereby enable data transfer therebetween.
`The means for selectively connecting preferably include a
`primary YO sense amplifier connected to the primary global
`YO line and one of the data 1/0 lines. the primary YO sense
`amplifier having an enabled state and a disabled state. the
`55 primary YO sense amplifier connecting the connected pri(cid:173)
`mary global YO line and the connected data YO line in the
`enabled state to thereby enable data transfer therebetween.
`the primary 1/0 sense amplifier disconnecting the connected
`global YO line and the connected data YO line in the
`6(J disabled state to thereby disable data transfer therebetween.
`The means for selectively connecting also preferably
`includes a redundant 110 sense amplifier connected to the
`redundant global 1/0 line and one of the data YO lines. the
`redundant YO sense amplifier having an enabled state and a
`65 disabled state. the redundant YO sense amplifier connecting
`the connected redundant global line and the connected data
`YO line in the enabled state to thereby enable data transfer
`
`MICRON-1003.009
`
`

`
`5.761.138
`
`3
`therebetween. the redundant J/O sense amplifier disconnect(cid:173)
`ing the connected global J/O line and the connected data J/O
`line in the disabled state to thereby disable data transfer
`therebetween. Means store a predetermined mapping of the
`redundant memory cell and the primary memory cell to the
`one column address. and means. responsive to the means for
`receiving a column address and the means for storing a
`predetermined mapping. selectively enable one of the pri(cid:173)
`mary I/O sense amplifier and the redundant I/O sense
`amplifier in response to the received column address and the
`stored predetermined mapping.
`The primary J/O sense amplifier preferably includes
`means for receiving a primary J/O sense amplifier output
`enable signal. the primary I/O sense amplifier being respon(cid:173)
`sive to the primary J/O sense amplifier output enable signal
`to enable the primary I/O sense amplifier when the primary
`J/O sense amplifier output enable signal has a first value and
`to disable the primary J/O sense amplifier when the primary
`J/O sense amplifier output enable signal has a second value.
`The redundant I/O sense amplifier preferably includes
`means for receiving a redundant J/O sense amplifier output
`enable signal. the redundant J/O sense amplifier being
`responsive to enable the redundant I/O sense amplifier when
`the redundant I/O sense amplifier output enable signal has a
`first value and to disable the redundant J/O sense amplifier
`when the redundant I/O sense amplifier output enable signal
`has a second value. The means for selectively enabling
`preferably includes means. responsive to the means for
`receiving a column address and the means for storing a
`predetermined mapping. for generating a primary block
`select signal and a redundant block select signal from the
`received column address and the stored predetermined
`mapping. means. responsive to the means for receiving a
`column address and the means for generating primary and
`redundant block select signals, for generating the primary
`J/O sense amplifier output enable signal according to the
`received column address signal and the primary block select
`signal, and means. responsive to the means for receiving a
`column address and the means for generating primary and
`redundant block select signals. for generating the redundant
`J/O sense amplifier output enable signal according to the
`received column address signal and the redundant block
`select signal. The primary block select signal and the redun(cid:173)
`dant block select signal are complementary to one another
`such that one of the primary I/O sense amplifier and the
`redundant J/O sense amplifier is enabled for the received
`column address.
`The means for generating primary and redundant block
`select signals preferably includes means for storing a pre(cid:173)
`determined column select mapping which maps the selected
`primary cell and the selected redundant memory cell to the
`one column address. as well as means, responsive to the
`means for receiving a column address and the means for
`storing a predetermined column select mapping, for gener(cid:173)
`ating a primary column select signal having one of an
`enabled value and a disabled value and a redundant column
`select signal having one of an enabled value and a disabled
`value, according to the received column address and the
`stored predetermined column select mapping. The means for
`generating primary and redundant block select signals also 60
`includes means for storing a predetermined block select
`mapping. and means. responsive to the means for receiving
`a column address. to the means for generating primary and
`redundant column select signals and to the means for storing
`a predetennined block select mapping, for generating the 65
`primary block select signal and the redundant block select
`signal according to the received column address. the values
`
`4
`of the primary and redundant column select signals. and the
`stored predetermined block select mapping. The means for
`storing a predetermined column select mapping preferably
`includes a plurality of fuses which program the means for
`5 storing a predetermined column select mapping to produce
`predetermined values for the primary and redundant column
`select signals from the received column address. The means
`for storing a predetermined block select mapping preferably
`includes a plurality of fuses which program the means for
`10 storing a predetermined block select mapping to produce
`predetermined values for the primary and redundant block
`select signals from the received column address and the
`redundant column select signal
`According to a preferred embodiment, a memory device
`15 includes means for receiving a column address. and means.
`responsive to the means for receiving a column address. for
`generating a plurality of primary column select signals and
`a plurality of redundant column select signals in response to
`the received address. each of the primary column select
`20 signals having one of a enabled and a disabled value. each
`of the redundant column select signals having one of an
`enabled and a disabled value. such that one of the primary
`column select and one of the redundant column select
`signals is enabled for each block for a received address. The
`25 memory device also includes a data input/output (I/0) bus
`including a plurality of data I/O lines, a plurality of blocks
`of primary memory cells. and a plurality of blocks of
`redundant memory cells. The memory device also includes
`plurality of blocks of primary I/O sense amplifiers. a respec-
`30 tive one of the plurality of blocks of primary I/O sense
`amplifiers being connected to a respective one of the data
`IIO lines. memory cells of a respective one of the plurality
`of blocks of primary memory cells being selectively con(cid:173)
`nected to I/O sense amplifiers of a respective one of the
`35 plurality of primary I/O sense amplifiers according to the
`values of the primary column select signals. and a plurality
`of blocks of redundant I/O sense amplifiers. a respective one
`of the redundant J/O sense amplifiers of plurality of blocks
`of redundant I/O sense amplifiers connected to a respective
`40 one of the data I/O lines. memory cells of a respective one
`of the plurality of blocks of redundant memory cells being
`selectively connected to redundant I/O sense amplifier of a
`respective one of the plurality of blocks of redundant J/O
`sense amplifiers according to the values of the redundant
`45 column select signals. Means. responsive to the means for
`generating the primary column select signals and the redun(cid:173)
`dant column select signals and to the means for receiving a
`column address. selectively enable one I/O sense amplifier
`of one of the plurality of blocks of J/O sense amplifiers and
`50 the plurality of blocks of redundant I/O sense amplifiers
`according to the received column address and the values of
`the primary column select and redundant column select
`signals, to thereby transfer data between the data I/O line
`and the memory cell connected to the enabled sense ampli-
`55 fier.
`The means for generating a column select signal and a
`redundant column select signal preferably includes a pro(cid:173)
`grammable column select signal generator programmable to
`produce one column select signal having an enabled value in
`response to receipt of a first column address and to produce
`one redundant column select signal having an enabled value
`in response to receipt of a second column address. The
`programmable column select signal generator preferably
`includes fuses operable to program the programmable col(cid:173)
`umn select signal generator to produce predetermined values
`for the primary and redundant column select signals from a
`received address.
`
`MICRON-1003.010
`
`

`
`5.761.138
`
`5
`The means for selectively enabling preferably includes a
`plurality of primary block I/O controllers. a respective one
`of the plurality of primary block I/O controllers controlling
`a respective one of the blocks of I/O sense amplifiers. each
`primary block I/O controller responsive to the received 5
`column address and including means for receiving an indi(cid:173)
`vidual associated block select signal having one of a first
`value and a second value. the primary I/O block controller
`disabling the primary I/O sense amplifiers in the associated
`block of primary I/O sense amplifiers when the associated 10
`primary block select signal has the second value and the
`primary I/O block controller selectively enabling one of the
`primary I/O sense amplifiers in the associated block of
`primary 1/0 sense amplifiers according to the received
`column address when the associated primary block select 15
`signal has the first value. The means for selectively enabling
`also preferably includes a plurality of redundant block I/O
`controllers. a respective one of the plurality of redundant
`block 1/0 controllers controlling a group of the plurality of
`blocks of redundant I/O sense amplifiers. each individual 20
`redundant block 1/0 controller responsive to the received
`column address and including means for receiving a com(cid:173)
`mon plurality of redundant block 110 select signals. each of
`the redundant block I/O signals having one of a first value
`and a second value. the redundant block 1/0 controller 25
`disabling all of the associated group of blocks of redundant
`I/O sense amplifiers when all of the common plurality of
`redundant block 1/0 select signals have the second value. the
`redundant block 1/0 controller selectively enabling one
`redundant I/O sense amplifier of one block of the associated 30
`group of blocks of redundant I/O sense amplifiers according
`to the received address and the common plurality of redun(cid:173)
`dant block 1/0 select signals when one of the redundant
`block 1/0 select signals has the first value.
`A programmable block select signal generator is respon- 35
`sive to the column select signal generator and programmable
`to produce the second value for one of the primary block
`select signals and to produce the first value for a redundant
`block select signal of the common plurality of redundant
`block select signals when one of the redundant column 40
`select signals has the first value. The programmable block
`select signal generator preferably includes fuses operable to
`program the programmable block select signal generator to
`produce predetermined values for the primary block select
`signals and the redundant block select signals in response to 45
`the redundant column select signals.
`The memory device may further include a plurality of
`split word line drivers disposed in row and column
`directions. a plurality of primary sense amplifier blocks
`disposed in the row and column directions. and a plurality of 50
`redundant sense amplifier blocks disposed in the row and
`column directions. a respective one of the redundant sense
`amplifier blocks being disposed adjacent a respective one of
`the primary sense amplifier blocks in the row direction. A
`plurality of primary global I/O lines extend in the column 55
`direction, overlying a first group of the split word line
`drivers and connected to the primary JJO sense amplifiers,
`while a plurality of redundant global 1/0 lines extend in the
`column direction. overlying a second group of the split word
`line drivers and connected to the redundant 1/0 sense 60
`amplifiers. A plurality of primary sub 1/0 lines extend in the
`row direction. overlying the primary sense amplifier blocks.
`which are switchably connected to the primary global J/O
`lines and to primary memory cells in an adjacent primary
`memory cell array. and a plurality of redundant sub J/O lines 65
`extend in the row direction. overlying the redundant sense
`amplifier blocks. which are switchably connected to the
`
`6
`redundant global JJO lines and to redundant memory cells in
`an adjacent redundant memory cell array. Each block of
`primary memory cells is arranged as a plurality of primary
`memory cell arrays. a respective one the plurality of primary
`memory cell arrays being disposed between a respective pair
`of the split word line drivers in the row direction and
`between a respective pair of the sense amplifier blocks in the
`column direction, and each block of redundant memory cells
`is arranged as a plurality of redundant memory cell arrays.
`a respective one of the redundant memory cell arrays being
`disposed between a respective one of the primary memory
`cell arrays and a respective one of the split word line drivers
`in the row direction and between a respective pair of the
`redundant sense amplifier blocks in the column direction. A
`flexible redundant memory architecture is thereby provided.
`
`BRIEF DESCRIPfION OF THE DRAWINGS
`
`Some of the objects and advantages of the present inven(cid:173)
`tion having been stated. others will be more fully understood
`from the detailed description that follows and by reference
`to the accompanying drawings in which:
`FIG. 1 is a schematic block diagram illustrating a redun(cid:173)
`dant memory architecture according to the prior art;
`FIG. 2 is a timing diagram illustrating operation of a
`redundant memory architecture according to the prior art;
`FIGS. 3A-3B are schematic block diagrams illustrating a
`memory device having a flexible redundant architecture
`according to the present invention;
`FIG. 4 is a schematic block diagram illustrating a pro(cid:173)
`grammable circuit for mapping primary memory cells and
`redundant memory cells to a column address according to
`the present invention;
`FIG. 5 is a schematic block diagram illustrating a fuse
`programmable circuit for programming redundant block
`selection according to the present invention; and
`FIG. 6 is a timing diagram illustrating operations for
`accessing a redundant memory cell according to the present
`invention.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`The present invention now will be described more fully
`hereinafter with reference to the accompanying drawings. in
`which embodiments of the invention are shown. This inven(cid:173)
`tion may. however, be embodied in many different forms and
`should not be construed as limited to the embodiments set
`forth herein; rather. these embodiments are provided so that
`this disclosure will be thorough and complete, and will fully
`convey the scope of the invention to those skilled in the art.
`In the drawings. the sizes of regions are exaggerated for
`clarity. and like numbers refer to like elements throughout.
`FIGS. 3A and 3B are schematic diagrams illustrating a
`memory device 300 according to the present invention
`having a flexible. redundant block architecture. In the figure.
`each of the JJO unit blocks UIOBi. UIOBj. UIOBk. UIOBl
`input/output data via corresponding data JJO terminals DQi.
`DQj. DQk. DQl has a primary J/O path and a redundant J/O
`path which are independent of one another. Referring to
`FIG. 3A. primary global J/O lines GIOi. GIOj. GIOk. GIOl
`are connected to data J/O lines DIOi. DIOj. DIOk. DIOl via
`primary J/O sense amplifier blocks IOSA. Each of the blocks
`of primary J/O sense amplifiers IOSA is shown as including
`four primary J/O sense amplifiers 30. 32. 34. 36. The data
`IJO lines DIOi, DIOj, DIOk. DIOl are shown as being
`connected to data J/O terminals DQi. DQj. DQk. DQl via
`
`MICRON-1003.011
`
`

`
`5.761.138
`
`7
`multiplexers/amplifters MXP. The redundant global 1/0
`paths RGIOi. RGIOj. RGIOk. RGIOl are connected to
`redundancy 1/0 sense amplifier blocks RIOSAl-4. each of
`which is shown including four redundant 1/0 sense ampli(cid:173)
`fiers 38. 40. 42. 44. The redundant 1/0 sense amplifiers are
`connected to the data 1/0 lines DIOi. DIOj. DIOk. DIOI.
`respectively. As shown. each of the normal global 1/0 line
`GIOi. GIOj. GIOk. GIOl and redundancy global 1/0 paths
`RGIOi. RGIOj. RGIOk and RGIOl may include a line pair.
`Although four-wide data paths are illustrate in FIGS.
`3A-B. those skilled in the art will appreciate that global 1/0
`busses. redundant 1/0 busses and data 1/0 busses having
`fewer or greater numbers of individual lines may also be
`used with the present invention.
`The memory device 300 as illustrated in FIGS. 3A and 3B
`includes a block architecture including unit 110 blocks
`UIOBi-1. each of which include a block of primary memory
`cells in primary memory cell arrays MCAl-4 and a block of
`redundant memory cells in redundant memory cell arrays
`RCAl-2. Each unit 1/0 block UIOBi-1 has a hierarchical
`structure of data paths. with a primary path including
`primary sub 1/0 bus SIO and primary global 1/0 bus GIOi
`connected to the block of primary memory cells in primary
`memory cell arrays MCAl-4, and a redundant 110 path
`including redundant sub 1/0 bus RSIO and redundant global
`I/O bus RGIOi connected to the block of redundant memory
`cells in redundant memory cell arrays RCAl-2. with the
`redundant path being independent of the primary path.
`The primary global 1/0 bus GIOi preferably is formed
`overlying a split word line driver SWD positioned between
`the primary memory cell arrays MCAl-4 as shown. The
`redundant global 110 bus RGIOi may be formed overlying
`split word line drivers SWD positioned between the redun(cid:173)
`dant memory cell array RCAl and the primary memory cell
`array MCAl in the adjacent 110 unit block UIOBj. and
`between the redundant memory cell array RCA2 and the
`normal memory cell array MCA3 in the adjacent 110 unit
`block UIOBj. In each of the I/O unit blocks UIOBi. UIOBj.
`UIOBk and UIOBI. the primary sub 110 lines SIOi-1 pref(cid:173)
`erably are formed overlying primary sense amplifier blocks
`SAl-6 and redundant sub I/O lines RSIOi-1 are formed
`overlying redundant sense amplifier blocks RSA. Using this
`preferred layout. different paths may be provided for pri(cid:173)
`mary and redundant operations. help to reduce parasitic bit
`line loading and increasing the :flexibility of the architecture
`without an undesirable increase in size of the cell