(12) United States Patent
`Hid aka
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006233181Bl
`US 6,233,181 B1
`May 15,2001
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`(75)
`
`Inventor: Hideto Hidaka, Hyogo (JP)
`
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/251,352
`
`(22) Filed:
`
`Feb. 17, 1999
`
`(30)
`
`Foreign Application Priority Data
`
`5,892,718 * 4/1999 Yamada ................................ 366/200
`
`FOREIGN PATENT DOCUMENTS
`
`6-232348
`6-237164
`
`8/1994 (JP) ............................... H01L/27/04
`8/1994 (JP) ........................... H03K/19/0948
`
`OTHER PUBLICATIONS
`
`"A Flexible Redundancy Technique for High-Density
`DRAM's", by Horiguchi, et al., IEEE Journal of Solid State
`Circuits, vol. 26, No.1, Jan. 1991, pp. 12-17.
`"Ultra LSI Memory", Kiyoo ITO, Advanced Electronics
`Series I-9, published by Baifukan, pp. 350-371, Nov. 5,
`1994.
`
`* cited by examiner
`
`Jun. 9, 1998
`Oct. 15, 1998
`
`(JP) ................................................. 10-160466
`(JP) ................................................. 10-293421
`
`Primary Examiner-Andrew Q. Tran
`(74) Attorney, Agent, or Firm-McDermott, Will & Emery
`
`Int. Cl? ....................................................... GllC 7/00
`(51)
`(52) U.S. Cl. .................... 365/200; 365/230.03; 365/190;
`365/225.7
`(58) Field of Search ............................... 365!200, 230.03,
`365/190, 208, 225.7
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,761,138 * 6/1998 Lee eta!. ............................. 365/200
`
`(57)
`
`ABSTRACT
`
`A spare memory array having spare memory cells common
`to a plurality of normal sub-arrays having a plurality of
`normal memory cells is provided. A spare line in the spare
`array can replace a defective line in the plurality of normal
`sub-array. The defective line is efficiently repaired by
`replacement in an array divided into blocks or sub-arrays.
`
`7 Claims, 31 Drawing Sheets
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`MICRON-1001.002
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 2 of 31
`
`US 6,233,181 B1
`
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`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 3 of 31
`
`US 6,233,181 B1
`
`F I G. 3 A
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`MICRON-1001.004
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`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 4 of 31
`
`US 6,233,181 B1
`
`F I G. 4
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`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 6 of 31
`
`US 6,233,181 B1
`
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`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 7 of 31
`
`US 6,233,181 B1
`
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`MICRON-1001.008
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`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 8 of 31
`
`US 6,233,181 B1
`
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`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 9 of 31
`
`US 6,233,181 B1
`
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`MICRON-1001.010
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 10 of 31
`
`US 6,233,181 B1
`
`F I G. 1 5
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`MICRON-1001.011
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 12 of 31
`
`US 6,233,181 B1
`
`F I G. 1 8 A
`IN NORMAL MODE;
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`EACH MEMORY BLOCK GROUP
`
`RAi ~ TO ADDRESS MEMORY MAT
`
`RAj ~ TO DEGENERATE
`
`SUB ARRAY IS
`ADDRESSED FROM
`EACH OF TWO
`BLOCK GROUPS
`IN ONE MAT
`(SENS AMPL I F I ER
`BAND IS NOT SHARED)
`
`F I G. 1 9
`
`TE
`
`GT
`
`RAj ----::;L __ >----+c/>B
`
`MICRON-1001.012
`
`

`
`1--"
`;
`~
`~ -..
`~
`'N
`0'1
`rJJ
`
`e
`
`~
`0
`'"""' ~
`m_
`'JJ. =-
`
`'"""'
`c
`~
`'"""' Ul
`'-<
`~
`
`::;_
`
`~
`......
`;F
`~
`d •
`
`(RAi=l)
`B#1
`
`(RAi=O)
`B#O
`
`IN TEST
`
`DEGENERATED
`
`_ __ B~J:.~C_E_B_!tlL_~-SPX#11 } RB#11
`
`--MB#11-N
`
`B#11
`
`'/////..0
`
`{ SPX#01-___ B_~.b~CE_B.ilQ.1___
`
`B#01
`
`MB#01-N --
`
`1
`
`RB#0
`
`,r MB#1 0-N
`
`B#1 0
`
`I
`
`r MB#1 o-2
`
`r MB# 11-1
`r-MB#1 Q-1
`r MB#11-0
`
`:
`
`B#1 0
`
`B# 11
`
`B#1 0
`
`B#11
`
`I
`
`I
`
`1
`
`I
`
`I
`
`I
`
`I
`
`1
`
`I
`
`I
`
`B#OO
`
`:
`
`B#OO
`
`B#O 1
`
`B#OO
`
`B#01
`
`MB#O 1-1 -..J
`
`MB#00-1 -.I
`
`{r.tl#Oa.-o~ ~ MB#1Q-O
`
`--REPLAcE-sill 0--t= SPX#1 o } RB#J 0
`
`--REPLAcE -s#Oo---
`
`RB#OO SPX#OO
`
`SENSE AMPLIFIER BAND
`
`SENSE AMPLIFIER BAND
`
`F I G. 2 0
`
`MICRON-1001.013
`
`

`
`1--"
`;
`~
`~
`~
`'N
`
`~
`
`'"""'
`;;
`'"""' 0
`'"""'
`a
`'JJ. =-
`
`'"""'
`c c
`~
`'"""'
`'-<
`~
`
`a
`
`~
`
`~ ......
`~
`~
`d
`
`(RAi=1)
`8#1
`
`(RAi=O)
`B#O
`
`[,:::::J¥.!}~:::,~,;1= ~:~: ~) RB#11
`
`I ...-MB# 1 0-N
`
`I
`r MB#lo-2
`r MB#11-1
`r-MB#1 0-1
`r MB#11-o
`
`.. ~ -
`
`-
`
`.
`.
`
`B#1o
`
`B#11
`
`B# 1 0
`
`B#11
`
`I
`
`I
`
`I
`
`1
`
`0
`
`.
`.
`
`0
`
`I
`
`I 1 I
`I
`I
`I
`
`0
`
`1
`
`I
`
`B#OO
`
`.
`.
`
`B#01
`
`B#OO
`
`B#01
`
`RB#01 G:~~~~
`
`MB#01-1 -J
`
`MB#00-1 --I
`
`o ~=;~;J~~;;=t ::!~o) RB#1 o
`RAj
`
`I
`
`SENSE AMPLIFIER BAND
`
`RB#oo G:~~--i'~~~;;~ol£';0~":'~1
`
`SENSE AMPLIFIER BAND
`
`F I G. 1 7
`
`MICRON-1001.014
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 14 of 31
`
`US 6,233,181 B1
`
`F I G. 2 1 A
`Vr
`
`3a
`
`ROW-RELATED ROW-RELATED
`PER I PlfRAL CKT PER I PlfRAL CKT
`
`MEMORY ARRAY MEMORY ARRAY
`BLOCK
`BLOCK
`
`2a
`
`¢Ba
`
`2b
`
`¢Bn
`
`SR
`
`POWER SUPPLY
`BLOCK DECODER
`
`AD
`
`FIG. 218
`
`MEMORY ARRAY
`BLOCK
`
`2n
`
`3
`
`15n
`
`¢Bin-1
`
`16
`P-- ¢Bip
`
`..------. \_, H I GI-l Vth
`
`15p
`
`12m
`
`11m ~t
`LOW Vth
`
`~HIGH Vth
`
`BL
`
`WLa
`
`2
`
`WLm
`
`MICRON-1001.015
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 15 of 31
`
`US 6,233,181 B1
`
`FIG. 22
`
`(RA2, RA3) :
`
`(1, 1)
`
`(0, 1)
`
`(1' 0)
`
`(0, 0)
`
`RA1=1
`
`MEMORY
`BLOCK
`MAB5
`(¢85)
`SW5
`...... P(MER SUPPLY
`SWITCH
`SWl
`
`RA1=0
`
`MAB1
`
`(¢ 81)
`
`MAB6
`(¢86)
`
`SW6
`
`SW2
`
`MAB2
`
`(¢82)
`
`MAB7
`(¢87)
`
`SW7
`
`SW3
`
`MAB8
`(¢88)
`
`SW8
`
`SW4
`
`MAB3
`
`MAB4
`
`(¢83)
`
`(¢84)
`
`}~1
`
`}~a
`
`FIG.23A
`NORMAL MODE
`GABO
`
`GAB1
`
`FIG. 238
`
`MAB5
`
`(1' 1)
`
`MAB6
`
`(0, 1)
`
`RA1 ~~~~~:,--D-EF-1-NE_D_
`
`I
`
`¢81-4 ~--
`
`1
`
`MAB7
`
`(1, 0)
`
`~ DEFINED
`RAl-3
`__ _.I
`
`I
`I
`
`MAB8
`
`(0, 0)
`
`4> 82 - - - r - - - - J ' -+ ROW-RELATED
`~ CKT OPERATION
`
`RA1:
`
`0
`
`1
`
`(RA2, RA3)
`
`I
`'
`HIGH SPEED OPERATION
`
`I
`
`'
`
`VOLTAGE
`STABILIZED
`
`MICRON-1001.016
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 16 of 31
`
`US 6,233,181 B1
`
`F I G. 2 5
`
`24
`I
`
`CMD
`
`'
`REFRESH MODE
`DETECTION CKT
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I ______________ _
`
`20
`I
`------L .....
`/22
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`REFRESH ADDRESS ~~---,-------'
`COUNTER
`c/J CUP
`QACT
`~--~'
`
`~5
`
`RACT
`
`QA
`
`MULTI PLEXERt-----.
`RA--~ ...
`
`ROW-RELATED ~ 27
`CONTROL CKT
`. ~ .
`c/JWL
`
`.......
`
`. TO POWER SUPPLY
`... RA 1 ,
`QA1-3 "BLOCK DECODER
`
`' AD
`TO ROW-RELATED CKT IN
`EACH MEMORY BLOCK
`
`MICRON-1001.017
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 17 of 31
`
`US 6,233,181 B1
`
`¢Bi
`i=1-8
`
`6
`
`F I G. 26
`
`RA1, (/RA1)
`
`(QACT)
`SR
`
`QA1-3,
`/OA1-3
`
`6b
`
`F I G. 27
`
`6c
`
`6c
`
`(QACT)
`SR ----41-----t
`
`/QA1,
`/OA2,
`QA3
`
`6b
`
`F I G. 2 8
`
`25
`I
`REFRESH ADDRESS
`COUNTER
`
`QA
`
`26
`I
`
`OA1-3 } TO POWER SUPPLY
`RA
`DECODE CKT
`---+
`
`1
`
`MULTIPLEXER
`
`TO ROW-RELATED
`PERIPHERAL CKT
`
`RA
`
`MICRON-1001.018
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 18 of 31
`
`US 6,233,181 B1
`
`F I G. 29
`
`32
`
`/SR
`
`31
`
`DELAY
`CKT
`
`QACT
`
`RACT
`
`WORD LINE
`ACTIVATION
`SIGNAL
`GENERATING
`CKT
`
`ct>RX
`
`<PWL
`
`I
`~'-- ........
`
`__ ...
`/SR
`
`. 33
`
`27
`
`FIG. 30
`
`RACT
`
`QACT
`
`ct>RX
`
`-----~
`
`ct>WL ----J
`WL _ __ __,/
`
`ACTIVE
`CYCLE
`
`POWER SUPPLY
`BLOCK SELECTED,
`,.. ;: VOLT AGE STAB I Ll ZED
`
`I
`
`I
`
`\ __ \_
`
`I
`
`''---'-------'~
`NORMAL MODE
`
`>:<
`
`I
`
`SELF-REFRESH MODE
`
`MICRON-1001.019
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 19 of 31
`
`US 6,233,181 B1
`
`F I G. 3 1
`
`40
`
`cbWL
`
`Xm
`
`WORD LINE
`DECODE SIGNAL
`GENERATING
`CKT
`
`(Vpp~Vss)
`sox
`
`/SOX
`
`Vpp
`
`"L" IN STAND-BY STATE
`
`I Vee
`
`Xi, j, k
`
`42
`
`WL
`
`ROW DECODE CKT
`
`WORD LINE
`DRIVE CKT
`
`FIG.32A
`GABO
`
`GAB1
`
`MAB5
`
`MAB6
`
`MA87
`
`MAB8
`
`:NORMAL MODE
`
`FIG. 328
`GABO
`
`GAB1
`
`(1, 1 )
`
`MAB1
`
`SW1 SW5
`
`MAB5
`
`)
`(0, 1
`
`MAB2 --
`
`(1, 0
`~
`
`~ ~ /WL
`I ~ ~
`MAB6
`
`WL
`
`MAB3
`
`513 S'ff7
`
`MAB7
`
`)
`(0, 0
`
`MAB4
`
`SW4 SW8
`
`MAB8
`
`(QA2, 3)
`
`:REFRESH MODE
`
`MICRON-1001.020
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 20 of 31
`
`US 6,233,181 B1
`
`l/>Bi
`i=1-8
`
`6
`
`F
`
`I G. 33
`
`RA1, (/RA1)
`
`(QACT)
`SR
`
`QA2, 3,
`/QA2,3
`
`6f
`
`F
`
`I G. 34
`
`6c
`
`6c
`
`(QACT)
`SR--4----f
`
`/QA2
`QA3
`
`6f
`
`FIG. 35
`
`l/>WL
`
`Ad
`
`ROW-RELATED
`SELECTING CKT
`
`•
`
`•
`
`WLO
`
`WLm
`
`50
`
`3
`
`MICRON-1001.021
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 21 of 31
`
`US 6,233,181 B1
`
`FIG. 36
`CUP
`
`REFRESH ADDRESS
`COUNTER
`
`6
`I
`~---------L----1
`60
`I
`I
`POWER SUPPLY
`:
`:
`.__---~~ BLOCK DECODE
`1
`CKT
`:
`I
`I
`I CUP
`
`¢CUP
`
`REGISTER
`
`65
`
`QA
`
`QACT
`
`I .----L-_........._......,
`I
`I
`
`SR
`
`I
`
`I_ ____ --------.J
`¢81-¢88
`:TO POWER SUPPLY SWITCH CKT
`
`26
`
`TO ROW-RELATED PERIPHERAL CKT
`
`F I G. 3 7
`
`QACT
`
`CUP
`
`¢CUP
`
`QA
`
`WL
`
`N+1
`
`I
`
`~ NOT NECESSARY TO WA I T
`FOR STAB I Ll ZA Tl ON 0 F
`POWER SUPPLY
`
`MICRON-1001.022
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 22 of 31
`
`US 6,233,181 B1
`
`FIG. 3 8
`
`FIG. 3 9
`
`FROM
`REFRESH >------~
`ADDRESS
`COUNTER
`
`QACT
`
`65d
`
`65e
`
`QAi
`
`65
`
`65c
`
`F I G.
`
`40
`
`QACT
`
`67
`
`DELAY CKT
`
`69
`
`68
`
`ONE-SHOT PULSE
`GENERATING CKT
`
`CUP
`
`70
`
`ONE-SHOT PULSE
`GENERATING CKT
`
`¢CUP
`
`_f
`
`_f
`
`MICRON-1001.023
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 23 of 31
`
`US 6,233,181 B1
`
`FIG. 41
`MAB5
`I
`NORMAL
`MEMORY
`BLOCK
`NMAB5
`SW5
`SW1
`NORMAL :
`MEMORY :
`BLOCK
`1SPB
`I
`I
`I
`I
`
`NMAB1
`
`'
`
`/
`
`v
`MAB1
`(RBX#)
`
`MASS
`I
`NORMAL
`MEMORY
`BLOCK
`NMAB6
`SW6
`SW2
`NORMAL
`MEMORY
`BLOCK
`NMAB2
`\
`MAB2
`
`MAB7
`I
`NORMAL
`MEMORY
`BLOCK
`NMAB7
`SW7
`SW3
`NORMAL
`MEMORY
`BLOCK
`NMAB3
`\
`MAB3
`
`MASS
`I
`NORMAL
`MEMORY
`BLOCK
`NMABS
`swa
`SW4
`NORMAL
`MEMORY
`BLOCK
`NMA84
`\
`MAB4
`
`F I G. 4 2
`
`RA1
`
`0
`
`1
`
`MAB1
`
`MAB2
`
`MAB5
`
`(1' 1)
`
`MAB6
`
`(0, 1)
`
`MAB3
`
`SW3 SYfl
`
`MAB7
`
`(1, 0)
`
`MAB4
`
`SW4 SWS
`
`MASS
`
`(0, 0)
`
`:NORMAL MODE
`
`(RA2, RA3)
`
`MICRON-1001.024
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 24 of 31
`
`US 6,233,181 B1
`
`FIG. 43
`
`RACT ---~;
`
`RA
`
`q, 81 --------~
`
`SPARE HIT ----+-lr-LJ..-:------o~.----:-=---­
`~~-----"\..v- HIT
`q, 82-8 ----f-H__,__.:,,_ __ ---:-........__ ___ _
`
`MVL
`
`SWL
`
`SPARE DETERMINATION
`NOT HIDDEN
`
`I
`;)I
`
`I
`'(
`
`: : "'-..SPARE DETERMINATION
`T I ME CAN BE HIDDEN
`
`I
`
`I
`
`F I G. 4 4
`
`QAl
`
`0
`
`1
`
`MABl
`
`SPB
`
`---
`
`SWL
`r----1----
`
`SW1 SW5
`
`MAB5
`
`(1 1 1)
`
`MAB2
`
`...........
`
`\
`NWL
`
`SW2 816
`
`MAB6
`
`(0, 1)
`
`MAB3
`
`SW3 SYf7
`
`MAB7
`
`(1, 0)
`
`MA84
`
`SW4 SW8
`
`MAB8
`
`(01 0)
`
`(QA2, QA3)
`:REFRESH MODE
`SPARE DETERMINATION -+ SW SELECTION
`
`MICRON-1001.025
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 25 of 31
`
`US 6,233,181 B1
`
`FIG. 45
`\...___ ___ _
`QACT - - - -
`QA ------~~----~X~--------
`,.....-----"""'\.t.=- HIT
`SPARE HIT ----------L""'+-------~~.....-------­
`,.....-------~-.. MISS
`tP 81- 4> 88 -------f......L...-------...l...------
`
`NWL
`
`SWL
`
`FIG.46A
`
`72
`
`71
`
`FIG.46B
`
`NORMAL MODE~ REFRESH MODE
`
`I
`I
`
`/RACT
`
`QA
`
`t/181
`
`OUTPUT OF
`NAND71
`
`MICRON-1001.026
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 26 of 31
`
`US 6,233,181 B1
`
`FIG. 47A
`
`75
`
`RA1,/RA1
`RA2, /RA2 - - - - - t
`RA3,/RA3
`(/QACT)
`/SR---...------'
`
`73
`
`SR (QACT)
`
`QA1,/QA1
`
`QA3,/QA3
`
`/HIT
`
`¢Bj
`
`j=2-8
`
`FIG. 478
`
`NORMAL MODE
`
`,.;(
`
`I
`I
`
`SELF-REFRESH MODE
`
`/RACT
`
`FIG. 48
`
`78
`
`_""*WORD Ll NE DRIVE
`¢ RX
`T I M I NG CONTROL CKT
`
`¢WL
`
`SR
`
`MICRON-1001.027
`
`

`
`1--"
`~
`1--"
`00
`1--"
`~ -..
`~
`'N
`0'1
`rJ'l
`
`e
`
`'"""'
`~
`0 ......,
`-..J
`N
`~ .....
`'JJ. =(cid:173)~
`
`'"""'
`N c c
`'"""'
`~Ul
`'-<
`~
`~
`
`~ = ......
`~ ......
`~
`•
`\Jl
`d •
`
`:TO POWER SUPPLY SWITCH CKT
`
`TO ROW-RELATED PERIPHERAL CKT
`
`( i =1-8)
`l/J Bi
`
`HIT
`
`Ad
`
`86
`
`89
`
`83
`
`CKT
`BLOCK DECODE
`POWER SUPPLY
`
`87
`
`HIT
`
`SR
`
`26
`
`6
`
`MUX I
`
`311
`
`RA
`
`SR
`
`QA
`
`65
`
`1+-l/J CUP
`
`REGISTER
`
`SR
`
`82
`
`MUX I • :ti DETERM I NAT I ON
`
`CKT
`
`SPARE
`
`80
`
`COUNTER
`REFRESH ADDRESS
`
`CUP--, ,.---RACT
`
`CUP
`F I G. 4 9
`
`MICRON-1001.028
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 28 of 31
`
`US 6,233,181 B1
`
`F I G. 50 A
`
`Al
`
`0
`
`MAB1
`
`SPB
`
`MAB2
`
`SW5
`
`MAB5
`
`(1, 1)
`
`SW6
`
`MAB6
`
`(0, 1)
`
`MA83
`
`SW3 S'K7
`
`MA87
`
`(1, 0)
`
`MAB4
`
`SW4 SWS
`
`MASS
`
`(0, 0)
`
`(A2, A3)
`:BEFORE SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`F I G.
`
`508
`
`RA1
`
`0
`
`SWL
`~---}_---
`~-- ----
`
`SW1 SW5
`
`MAB5
`
`(1, 1)
`
`~
`SW2 SW6
`~
`SW3 S'K7
`
`\
`NWL
`
`MAB3
`
`MASS
`
`(0, 1)
`
`MA87
`
`(1, 0)
`
`MAB1
`
`---
`
`- .
`
`SPB
`
`MAB2
`
`.........
`
`MA84
`
`SW4 sws
`
`MAB8
`
`(0, 0)
`
`(RA2, RA3)
`:AFTER SPARE DETERMINATION DEFINED
`NORMAL MODE
`
`MICRON-1001.029
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 29 of 31
`
`US 6,233,181 B1
`
`F I G. 51 A
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`MICRON-1001.030
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 30 of 31
`
`US 6,233,181 B1
`
`F I G 0 5 3
`
`PRIOR ART
`
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`PRIOR ART
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`MICRON-1001.031
`
`

`
`U.S. Patent
`
`May 15,2001
`
`Sheet 31 of 31
`
`US 6,233,181 B1
`
`F I G. 55 PRIOR ART
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`MICRON-1001.032
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`

`
`US 6,233,181 B1
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to semiconductor
`memory devices, and more particularly, to a semiconductor
`memory device having a memory array divided into a
`plurality of memory blocks. More specifically, the present
`invention relates to a redundancy circuit for repairing a 10
`defective memory cell in a semiconductor memory device
`having such an array-divided arrangement and a power
`supply circuit provided corresponding to each block.
`2. Description of the Background Art
`In the semiconductor memory device, a defective memory
`cell is replaced with a spare memory cell in order to
`equivalently repair the defective memory cell to raise the
`yield of the products. A flexible redundancy scheme has
`been proposed in order to improve the use efficiencies of
`spare lines (word lines or bit lines) and spare decoders for
`selecting spare lines in a redundancy circuit configuration
`including spare memory cells (spare word lines and bit lines)
`for repairing such defective memory cells (see, for example,
`"A Flexible Redundancy Technique for High-Density
`DRAM's", Horiguchi et al., IEEE Journal of Solid-State
`Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
`FIG. 53 is a schematic diagram of the general configu(cid:173)
`ration of a semiconductor memory device having a conven(cid:173)
`tional flexible redundancy scheme. In FIG. 53, the semicon- 30
`ductor memory device includes four memory arrays MAO to
`MA3. In each of memory arrays MAO to MA3, a spare word
`line to repair a defective memory cell row is provided. In
`memory array MAO, spare word lines SWOO and SWOl are
`provided, and in memory array MAl, spare word lines 35
`SWll and SWll are provided. In memory array MA2, spare
`word line SW20 and SW21 are provided, and in memory
`array MA3, spare word lines SW30 and SW31 are provided.
`Row decoders XO to X3 each for decoding an address
`signal to drive a normal word line provided corresponding to 40
`an addressed row into a selected state are provided corre(cid:173)
`sponding to memory arrays MAO to MA3. A column
`decoder YO is provided between memory arrays MAO and
`MAl to decode a column address signal to select an
`addressed column, and also a column decoder Yl is pro- 45
`vided between memory arrays MA2 and MA3.
`The semiconductor memory device further includes spare
`decoders SDO to SD3 to store a row address at which a
`defective memory cell is present, maintain a word line
`(defective normal word line) corresponding to this defective 50
`row address in a non-selected state when the defective row
`is addressed and drive a corresponding spare word line into
`a selected state, an OR circuit GO to receive output signals
`from spare decoders SDO and SDl, and an OR circuit Gl to
`receive output signals from spare decoders SD2 and SD3. 55
`The output signals of OR circuits GO and Gl are provided
`in common to spare word line driving circuits included in
`row decoders XO to X3. Spare decoders SDO to SD3 are
`commonly provided with array address signal bits an-2 and
`an-1 to address one of memory arrays MAO to MA3 and 60
`with intra-array address signals bits aO to an-3 to address a
`row in the memory array. Row decoders XO to X3 are
`provided with array address signal bits an-2 and an-1, and a
`row decoder is activated when a corresponding memory
`array is addressed. OR circuits GO and Gl each correspond 65
`to two spare word lines provided for each of memory arrays
`MAO to MA3.
`
`2
`Let us assume that normal word lines WO and Wl are
`defective in memory array MAO, that a normal word line W2
`in memory array MAl is defective, and that a normal word
`line W3 in memory array MA2 is defective. In this state, the
`5 address of word line WO is programmed in spare decoder
`SDO, while the address of word line Wl is programmed in
`spare decoder SD2. The address of normal word line W2 is
`programmed in spare decoder SD3, and the address of
`normal word line W3 is programmed in spare decoder SDl.
`OR circuit GO selects one of spare word lines SWOO,
`SWlO, SW20 and SW30, and the output signal of OR circuit
`Gl selects one of spare word lines SWOl, SWll, SW21 and
`SW31.
`When normal word line WO is addressed, the output
`15 signal of spare decoder SDO is driven into a selected state,
`and the output of OR circuit GO is activated. In this state,
`array address signal bits an-2 and an-1 activate row decoder
`XO, and the remaining row decoders Xl to X3 are main(cid:173)
`tained in a non-active state. Thus, a word line driving circuit
`20 included in row decoder XO drives spare word line SWOO
`into a selected state in response to the output signal of OR
`circuit GO. At this time, in row decoder XO, a decode circuit
`provided corresponding to normal word line WO is main(cid:173)
`tained in a non-active state. As a result, defective normal
`25 word line WO is replaced with spare word line SWOO.
`If defective normal word line Wl is addressed, the output
`signal of spare decoder SD2 attains an H level in a selected
`state, the output signal of OR circuit Gl attains an H level,
`and spare word line SWOl is selected. If defective normal
`word line W2 is addressed, the output signal of spare
`decoder SD3 attains an H level in a selected state, the output
`signal of OR circuit Gl attains an H level, and spare word
`line SWll is selected. If defective normal word line W3 is
`addressed, the output signal of spare decoder SDl attains an
`H level in a selected state, and spare word line SW20 is
`selected by OR circuit GO accordingly. More specifically,
`defective normal word lines WO, Wl, W2 and W3 are
`replaced with spare word lines SWOO, SWOl, SWll and
`SW20, respectively.
`In this flexible redundancy scheme shown in FIG. 53, a
`single spare word line can be activated by any of a plurality
`of spare decoders. For example, spare word line SW20 can
`be driven into a selected state by spare decoder SDO or SDl.
`A single spare decoder can drive any of a plurality of spare
`word line into a selected state. For example, spare decoder
`SDO can drive any of spare word lines SWOO, SWlO, SW20
`and SW30 into a selected state. Thus, the spare word line and
`spare decoders do not correspond in one-to-one relation, and
`therefore the spare word lines and spare decoders can be
`more efficiently utilized. The number of spare word lines
`and the number of spare row decoders in a single memory
`array may be selected independently from each other as long
`as the numbers satisfy the following relation:
`
`L~R~M·L/m
`
`wherein M is the number of physical memory arrays, m the
`number of memory arrays whose defective normal word
`lines are replaced with spare word lines simultaneously, R
`the number of spare row decoders, and L the number of
`spare word lines in a single memory array. More specifically,
`M/m is the number of memory arrays which are logically
`independent from one another. As a result, M·L/m represents
`the number of spare word lines which are logically inde(cid:173)
`pendent from one another for the entire memory. Herein, the
`logically independent spare word lines are spare word lines
`selected by different row addresses. For example, in FIG. 53,
`
`MICRON-1001.033
`
`

`
`US 6,233,181 B1
`
`3
`if a normal word line is simultaneously selected in memory
`arrays MAO and MA2, memory arrays MAO and MA2 are
`not logically independent from each other. In the arrange(cid:173)
`ment shown in FIG. 53, L=2, R=4, M=4 and m=l.
`By providing a spare row decoder common to memory 5
`arrays, a spare decoder does not have to be provided for each
`of spare word lines, which can restrain the chip area from
`increasing.
`The flexible redundancy scheme shown in FIG. 53 may be
`employed for repairing a defective column as well. In
`repairing a defective column, the previously mentioned prior
`art document describes a method of repairing a defective
`column where a memory array is divided into a plurality of
`sub-arrays. The document particularly describes the way of
`repairing a defective column in multi -divided bit lines in a
`shared-sense amplifier arrangement and in a shared 1!0
`scheme.
`FIG. 54 is a schematic diagram of the configuration of an
`array portion in a semiconductor memory device according
`to a conventional flexible redundancy scheme. In FIG. 54,
`two memory blocks MBi and MBi+l are shown. Memory
`blocks MBi and MBi+l each include a normal bit line pair
`BL and /BL provided corresponding to each memory cell
`column and a spare bit line (spare column) for repairing a
`defective column. In FIG. 54, the spare bit line included in
`the spare column is not clearly shown.
`Normal bit lines BLand/BLat the same column address
`in memory blocks MBi and MBi+l share a sense amplifier
`SA A bit line isolation gate ILG is provided between sense
`amplifier SA and memory blocks MBi and MBi+l. Sense
`amplifier SA is connected to an internal data line pair 1!0
`through an 10 gate lOG which conducts in response to a
`column selecting signal YS from column decoder Y. A
`memory block including a selected memory cell (MBi, for
`example) is connected to sense amplifier SA and data is read 35
`out therefrom. In this case, a non-selected memory block
`(MBi+l) is disconnected from sense amplifier SA
`In the above-described shared-sense amplifier
`arrangement, a defective column address must be pro(cid:173)
`grammed for each of defects in normal bit lines, in a single 40
`memory block column selecting lines (YS lines) and sense
`amplifiers SA For a normal bit line defect, the defective
`column address is programmed on a memory block basis.
`For a sense amplifier defect, the defective column address is
`so programmed as to use a spare column for each of memory 45
`blocks MBi and MBi+l which share this defective sense
`amplifier. For a column selecting line (YS line) defect, the
`defective column address is programmed for each of the
`memory blocks connected to this column selecting line (YS
`line).
`At the time of programming, in order to use a single spare
`column decoder for a normal bit line defect, a sense ampli(cid:173)
`fier defect and a column selecting line (YS line) defect,
`"Don't care" is programmed at the time of programming a
`defective column address, an address to specify a memory 55
`block is invalidated, and spare columns are replaced simul(cid:173)
`taneously in a plurality of memory blocks.
`In the previously mentioned document, a defective row is
`repaired by replacing the defective row with a spare word
`line provided within a memory array including that defective 60
`row. Thus, a spare word line must be provided for each of
`memory arrays, and the spare word lines are not efficiently
`utilized. If a defective normal word line in one memory
`array is replaced with a spare word line in another memory
`array, the control of the memory array related circuits will be 65
`complicated, and therefore such arrangement must be
`avoided and is not considered at all.
`
`4
`In repairing a defective column, a spare column is pro(cid:173)
`vided for each of memory blocks, and spare columns are
`similarly not efficiently used. Although the shared 1!0
`scheme has been considered for internal data line
`arrangement, the way to repair a defective column in a
`memory array having a local/global hierarchical data line
`arrangement used in a recent block-divided arrangement has
`never been considered.
`Meanwhile, in a conventional CMOS (Complimentary
`10 MOS) type semiconductor device, the size of components
`(MOS transistor: insulated gate type field effect transistor) is
`reduced to increase the integration density. In order to secure
`the reliability of the components thus miniaturized and to
`reduce the current consumed by the entire device, the power
`15 supply voltage is reduced. In order to allow the components
`to operate at a high spe