UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`MICRON TECHNOLOGY, INC.
`Petitioner
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 6,233,181
`________________________
`
`Corrected Declaration of R. Jacob Baker, Ph.D. in
`Support of Petition For Inter Partes Review
`of U.S. Patent No. 6,233,181
`Under 37 C.F.R. § 1.68
`
`MICRON-1007.001
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`
`TABLE OF CONTENTS
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`
`
`Page
`
`I.
`INTRODUCTION AND QUALIFICATIONS ............................................... 1
`II. MATERIALS RELIED ON IN FORMING MY OPINION........................... 4
`III. UNDERSTANDING OF THE GOVERNING LAW ..................................... 4
`A.
`Invalidity by Obviousness ..................................................................... 4
`IV. LEVEL OF ORDINARY SKILL IN THE ART ............................................. 6
`V. OVERVIEW OF THE TECHNOLOGY AND THE 181 PATENT............... 7
`A.
`Technology Background ....................................................................... 7
`B.
`The 181 Patent .....................................................................................13
`181 PATENT PROSECUTION HISTORY ..................................................20
`VI.
`VII. CLAIM CONSTRUCTIONS ........................................................................24
`A.
`Legal Standard .....................................................................................24
`B.
`“word lines” (claims 1-7) ....................................................................24
`C.
`“spare memory cells” (claims 1-7) ......................................................25
`D.
`“sense amplifier bands” (claims 3 and 5) ............................................26
`VIII. THE PRIOR ART ..........................................................................................27
`A.
`Sukegawa (U.S. Patent No. 5,487,040) ...............................................27
`B. Walck (U.S. Patent No. 4,967,1.397) ..................................................35
`C. Motivations to Combine Sukegawa and Walck ..................................36
`Betty Prince, Semiconductor Memories (2d ed. 1992) .......................37
`D.
`E. Motivations to Combine Sukegawa and Prince ..................................38
`F.
`Oh (U.S. Patent No. 5,355,339) ..........................................................39
`G. Motivations to Combine Sukegawa and Oh........................................41
`IX. GROUNDS OF INVALIDITY .....................................................................42
`X. Ground #1: Claim 1 is obvious over Sukegawa .............................................. 1
`XI. Ground #1: Claim 2 is obvious over Sukegawa ............................................25
`XII. Ground #2: Claim 3 is obvious over Sukegawa in view of Prince ...............30
`XIII. Ground #3: Claim 4 is obvious over Sukegawa in view of Prince ...............36
`
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`ii
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`MICRON-1007.002
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`XIV. Ground #4: Claim 5 is obvious over Sukegawa in view of Walck ...............39
`XV. Ground #1: Claim 6 is obvious over Sukegawa ............................................45
`XVI. Ground #5: Claim 7 is obvious over Sukegawa in view of Oh .....................52
`
`ii
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`
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`MICRON-1007.003
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`I, R. Jacob Baker, hereby declare as follows:
`
`I.
`
`INTRODUCTION AND QUALIFICATIONS
`
`1. My name is R. Jacob Baker. My findings, as set forth herein, are
`
`based on my education and background in the fields discussed below.
`
`2.
`
`I have been retained on behalf of Petitioner Micron Technology, Inc.
`
`(“Micron”) to provide this Declaration concerning technical subject matter relevant
`
`to the inter partes review petition (“Petition”) concerning U.S. Patent No.
`
`6,233,181 (“the 181 Patent”). I reserve the right to supplement this Declaration in
`
`response to additional evidence that may come to light.
`
`3.
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this Declaration and could testify competently to them if asked to do so.
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`4. My compensation is not based on the resolution of this matter. My
`
`findings are based on my education, experience, and background in the fields
`
`discussed below.
`
`5.
`
`I currently serve as a Professor of Electrical and Computer
`
`Engineering at the University of Nevada, Las Vegas (UNLV). I have been
`
`teaching electrical engineering at UNLV since 2012. Prior to this position, I was a
`
`Professor of Electrical and Computer Engineering at Boise State University from
`
`2000. Prior to my position at Boise State University, I was an Associate Professor
`
`Electrical Engineering between 1998 and 2000 and Assistant Professor of
`
`
`
`1
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`MICRON-1007.004
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`Electrical Engineering between 1993 and 1998 at the University of Idaho. I have
`
`been teaching electrical engineering since 1991.
`
`6.
`
`I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
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`from UNLV in 1988 and 1986, respectively.
`
`7.
`
`As described
`
`in my CV (MICRON-1008), I am a
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`licensed
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`Professional Engineer in the state of Idaho and have more than 25 years of
`
`experience, including extensive experience in circuit design and manufacture of
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`Dynamic Random Access Memory (DRAM) integrated circuit chips and CMOS
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`Image Sensors (CISs) at Micron in Boise, Idaho. I also spent considerable time
`
`working on the development of Flash Memory while at Micron. My efforts
`
`resulted in more than a dozen Flash-memory related patents. Among other
`
`experiences, I led development of the Delay-Locked Loop (DLL) in the late 90s so
`
`that Micron products could transition to the DDR memory standard. I have
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`worked as a consultant at other companies designing memory chips, including Sun,
`
`Oracle, and Contour Semiconductor. I have also worked as a consultant at other
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`companies designing CISs, including OmniVision and Lockheed Martin.
`
`8.
`
`I have taught courses in integrated circuit design (analog, digital,
`
`mixed-signal, etc.), linear circuits, microelectronics, communication systems, and
`
`
`
`2
`
`MICRON-1007.005
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`fiber optics. As a professor, I have been the main advisor to five Doctoral students
`
`and over 50 Masters students.
`
`9.
`
`I am the author of several books covering the area of integrated circuit
`
`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
`
`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
`
`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and co-
`
`authored, more than 75 papers and presentations in the areas of solid-state circuit
`
`design, and I am the named inventor on over 135 granted U.S. patents in integrated
`
`circuit designs including flash memory and DRAM.
`
`10.
`
`I have received numerous awards for my work, including the
`
`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
`
`Award is bestowed annually upon an outstanding young electrical/computer
`
`engineering educators in recognition of the educator’s contributions to the
`
`profession.
`
`11.
`
`I am a Fellow of the IEEE for contributions to memory circuit design.
`
`I have also received the IEEE Circuits and Systems Education Award (2011).
`
`12.
`
`I have received the President’s Research and Scholarship Award
`
`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
`
`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`
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`3
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`MICRON-1007.006
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`University. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor award the three years I have been at UNLV.
`
`II. MATERIALS RELIED ON IN FORMING MY OPINION
`In addition to reviewing U.S. Patent No. 6,233,181, I also reviewed
`13.
`
`and considered the prosecution history of the 181 Patent. U.S. Patent No.
`
`5,487,040 (“Sukegawa”), U.S. Pat. No. 4,967,397 (“Walck”), U.S. Pat. No.
`
`5,355,339 (“Oh”), and Betty Prince, Semiconductor Memories (2d ed. 1992)
`
`(“Prince”).
`
`III. UNDERSTANDING OF THE GOVERNING LAW
`I understand that a patent claim is invalid if it is anticipated or obvious
`14.
`
`in view of the prior art. I further understand that invalidity of a claim requires that
`
`the claim be anticipated or obvious from the perspective of a person of ordinary
`
`skill in the relevant art at the time the invention was made.
`
`A.
`15.
`
`Invalidity by Obviousness
`
`I have been informed that a patent claim is invalid as “obvious” under
`
`35 U.S.C. § 103 if it would have been obvious to one of ordinary skill in the art,
`
`taking into account (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the claims, (3) the level of ordinary skill in the art, and
`
`(4) any so called “secondary considerations” of non-obviousness, which include:
`
`(i) “long felt need” for the claimed invention, (ii) commercial success attributable
`
`to the claimed invention, (iii) unexpected results of the claimed invention, and (iv)
`
`
`
`4
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`MICRON-1007.007
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`“copying” of the claimed invention by others. I further understand that it is
`
`improper to rely on hindsight in making the obviousness determination. My
`
`analysis of the prior art is made as of the time the invention was made.
`
`16.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. I further understand that
`
`exemplary rationales that may support a conclusion of obviousness include:
`
`(A) Combining prior art elements according to known methods to yield
`
`predictable results;
`
`(B) Simple substitution of one known element for another to obtain
`
`predictable results;
`
`(C) Use of known technique to improve similar devices (methods, or
`
`products) in the same way;
`
`(D) Applying a known technique to a known device (method, or product)
`
`ready for improvement to yield predictable results;
`
`(E) “Obvious to try” – choosing from a finite number of identified,
`
`predictable solutions, with a reasonable expectation of success;
`
`(F) Known work in one field of endeavor may prompt variations of it for use
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`in either the same field or a different one based on design incentives or other
`
`market forces if the variations are predictable to one of ordinary skill in the art;
`
`
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`5
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`MICRON-1007.008
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
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`(G) Some teaching, suggestion, or motivation in the prior art that would
`
`have led one of ordinary skill to modify the prior art reference or to combine prior
`
`art reference teachings to arrive at the claimed invention.
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`In my opinion, a person of ordinary skill in the art at the time of the
`17.
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`claimed inventions would have had a bachelor’s degree in computer engineering,
`
`electrical engineering, computer science, or a closely related field, along with at
`
`least 2-3 years of experience in the development and use of memory devices and
`
`systems. An individual with an advanced degree in a relevant field, such as
`
`computer or electrical engineering, would require less experience in the
`
`development and use of memory devices and systems.
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`18.
`
`I reserve the right to amend or supplement this declaration if the
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`Board adopts a definition of a person of ordinary skill other than that described
`
`above, which may change my conclusion or analysis.
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`19. My opinion below explains how a person of ordinary skill in the art
`
`would have understood the technology described in the references I have identified
`
`herein around the 1998 time period, which is the approximate date when the
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`application to which the 181 Patent claims priority was filed. I was a person of at
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`least ordinary skill in the art in 1998.
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`
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`6
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`MICRON-1007.009
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`V. OVERVIEW OF THE TECHNOLOGY AND THE 181 PATENT
`20. The 181 Patent was filed on February 17, 1999, and claims priority to
`
`two Japanese patent applications, the earliest of which was filed on June 9, 1998. I
`
`have seen no evidence that the 181 Patent is entitled to an earlier priority date than
`
`June 9, 1998. The 181 Patent issued on May 15, 2001.
`
`21. The 181 Patent relates generally to a semiconductor memory device
`
`having memory arrays that are further subdivided into a plurality of memory
`
`blocks. MICRON-1001, 181 Patent at 1:6-9 (“The present invention relates
`
`generally to semiconductor memory devices, and more particularly, to a
`
`semiconductor memory device having a memory array divided into a plurality of
`
`memory blocks.”).
`
`22. Before discussing the details of the specification of the 181 Patent, I
`
`will provide a brief background on the technology of semiconductor memory
`
`devices.
`
`A. Technology Background
`23. The basic component of a semiconductor memory device is a memory
`
`cell, which is a structure capable of storing a bit of digital data (a 1 or a 0). The
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`structure of a memory cell varies slightly depending on the type of semiconductor
`
`memory device. In a Dynamic Random Access Memory (DRAM) semiconductor
`
`device, for example, the memory cell consists of one capacitor for storing the
`
`
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`7
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`MICRON-1007.010
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
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`digital bit and one transistor. See MICRON-1009, Excerpts from Betty Prince,
`
`Semiconductor Memories (2d ed. 1992) (“Prince”), at .023. The Prince textbook
`
`was a well-known resource in the field of semiconductor memory devices. The
`
`excerpts produced at MICRON-1009 are from a copy of the textbook that was
`
`stamped by the Library of Congress on March 26, 1992. See id. at .005.
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`24. The gate of the transistor of the memory cell is connected to a
`
`conductive material that runs horizontally through the memory device called a
`
`“word line.” The drain of the transistor, for example, is connected to a conductive
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`material that runs vertically through the memory device called a “bit line.” The
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`source of the transistor, for example, is connected to the capacitor, which stores the
`
`digital bit.1 A diagram of a basic DRAM memory cell from the Prince textbook is
`
`reproduced below:
`
`
`1 The above example is for the case of writing a logical 1 to the memory cell.
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`However, when writing a logical zero, the capacitor of the memory cell is
`
`discharged so current flows from the capacitor to the bit line. Thus, in this case,
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`the drain is connected to the capacitor and the source is connected to the bit line.
`
`
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`8
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`MICRON-1007.011
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`
`Figure 2.14: Basic MOS memory storage cells. (a) Dynamic RAM
`
`MICRON-1009, Prince at .024 (annotated).
`
`In the semiconductor industry, the term “word line” is synonymous
`
`25.
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`with “row line.” The terms “digitline,” “bit line,” and “column line” are also
`
`synonymous. In this declaration, I will use the terms “word line” and “bit line”
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`because the 181 Patent uses this terminology.
`
`26. Memory cells aligned in the horizontal (row) direction are connected
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`to the same word line and memory cells aligned in the vertical (column) direction
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`are connected to the same bit line. In this way, an array of interconnected memory
`
`cells is formed. A diagram of a basic DRAM architecture from the Prince textbook
`
`is reproduced below:
`
`
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`9
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`MICRON-1007.012
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`MICRON-1009, Prince at .029 (annotated).
`
`
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`27. As shown in this figure, in a typical memory structure, an array of
`
`
`
`memory cells is formed at intersections of the 2N rows of word lines and 2M
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`columns of bit lines. In normal operations, data can be read to and written to the
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`cells in the memory array. For example, to read data from a cell, a row address is
`
`input and decoded to select one of the 2N word lines. MICRON-1009, Prince at
`
`.029. Because all of the memory cells aligned in the row direction are connected to
`
`the same word line, all 2M cells in the selected word line are activated. See id. The
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`column decoder then addresses one bit line out of the 2M cells that have been
`
`activated and routes the stored data in the cell to a sense amplifier. See id.
`
`
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`10
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`MICRON-1007.013
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`28. The sense amplifier is a component that compares the data in the cell
`
`to a reference cell and determines if the cell stored a 1 or a 0. See id. at .037.
`
`Because the read out from the cell discharges the capacitor such that it no longer
`
`stores the data that has been read, the sense amplifier also must restore the original
`
`charge to the cell. See id.
`
`29. Adjacent memory cells in an array may further be subdivided into
`
`memory blocks. See, e.g., id. at .047 (“Mostek [40] dealt with the RC delay and
`
`capacitive coupling effects by using an innovative divided bit-line architecture
`
`which was evolved from a combination of the folded-bit line techniques and the
`
`shared sense amplifier concept as shown in Figure 6.25. This bit-line architecture
`
`divided the long columns into 16 polysilicon bit-line segments of 64 cells each
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`with eight segments arranged end to end in a line on either side of a central column
`
`decoder. Adjacent segments were grouped into pairs of open bit-lines to form
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`eight memory blocks of 128k bits each.”). 2
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`30.
`
`In such an arrangement, the sense amplifier can be shared between
`
`two or more blocks. This is shown in Figure 6.25(b) of Prince:
`
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`2 All emphases are added unless otherwise noted.
`
`
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`11
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`MICRON-1007.014
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`
`
`MICRON-1009, Prince at .048 (annotated).
`
`In the above figure, the shared sense amplifier is shaded in purple.
`
`
`
`31.
`
`Note that in the figure, the bit lines are shown to run in the horizontal direction.
`
`Thus, the memory blocks on each side of the sense amplifier are aligned in the
`
`column direction (the column direction is the bit line direction).
`
`32.
`
`In addition, other components, such as a column decoder, may be
`
`shared among multiple memory arrays or blocks. See, e.g., id. at .047 (describing a
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`DRAM semiconductor device and stating that “[t]he column decoder and I/O bus
`
`lines are shared by eight 64k memory arrays.”).
`
`
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`12
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`MICRON-1007.015
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`The 181 Patent
`
`B.
`33. The 181 Patent concerns the field of repairing defective memory cells
`
`in a semiconductor memory device. MICRON-1001, 181 Patent at 1:9-13 (“More
`
`specifically, the present invention relates to a redundancy circuit for repairing a
`
`defective memory cell in a semiconductor memory device having such an array-
`
`divided arrangement and a power supply circuit provided corresponding to each
`
`block.”). Each memory cell in a block/array may be a (1) normal memory cell; or
`
`(2) a spare/redundant cell. A normal memory cell is simply a cell that stores a bit
`
`in the normal operation of the memory device. A spare/redundant memory cell is a
`
`memory cell that is capable of replacing a defective memory cell. As was known
`
`in the art, when a memory cell becomes defective, the memory cell can be replaced
`
`with spare/redundant memory cells. See id. at 1:15-18 (“In the semiconductor
`
`memory device, a defective memory cell is replaced with a spare memory cell in
`
`order to equivalently repair the defective memory cell to raise the yield of the
`
`products.”). In describing conventional schemes for repairing defective memory
`
`with spare/redundant memory, the 181 Patent explains that the spare memory cells
`
`would be provided as spare word lines (extra rows of spare memory cells) or spare
`
`column/bit lines (extra columns of spare memory cells) in each memory block.
`
`the general
`is a schematic diagram of
`FIG. 53
`configuration of a semiconductor memory device having
`a conventional flexible redundancy scheme. In FIG. 53,
`
`
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`13
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`MICRON-1007.016
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`the semiconductor memory device includes four memory
`arrays MA0 to MA3. In each of memory arrays MA0 to
`MA3, a spare word line to repair a defective memory cell
`row is provided. In memory array MA0, spare word
`lines SW00 and SW01 are provided, and in memory
`array MA1, spare word lines SW11 and SW11 [sic] are
`provided. In memory array MA2, spare word line SW20
`and SW21 are provided, and in memory array MA3,
`spare word lines SW30 and SW31 are provided.
`
`See MICRON-1001, 181 Patent at 1:28-38.
`
`
`FIG. 54 is a schematic diagram of the configuration of an
`array portion
`in a semiconductor memory device
`according to a conventional flexible redundancy scheme.
`In FIG. 54, two memory blocks MBi and MBi+1 are
`shown. Memory blocks MBi and MBi+1 each include a
`normal bit line pair BL and /BL provided corresponding
`to each memory cell column and a spare bit line (spare
`column) for repairing a defective column. In FIG. 54, the
`spare bit line included in the spare column is not clearly
`shown.
`
`Id. at 3:18-26.
`
`
`34. The alleged problem, however, with these techniques was that
`
`providing spare word lines/bit lines in each memory block resulted in the spare
`
`memory cells being utilized inefficiently:
`
`
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`14
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`MICRON-1007.017
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`In the previously mentioned document, a defective row is
`repaired by replacing the defective row with a spare word
`line provided within a memory array including that
`defective row. Thus, a spare word line must be provided
`for each of memory arrays, and the spare word lines are
`not efficiently utilized. If a defective normal word line
`in one memory array is replaced with a spare word line in
`another memory array, the control of the memory array
`related circuits will be complicated, and therefore such
`arrangement must be avoided and is not considered at all.
`
`Id. at 3:58-67.
`
`
`In repairing a defective column, a spare column is
`provided for each of memory blocks, and spare columns
`are similarly not efficiently used. Although the shared
`I/O scheme has been considered for internal data line
`arrangement, the way to repair a defective column in a
`memory array having a local/global hierarchical data line
`arrangement used in a recent block-divided arrangement
`has never been considered.
`
`Id. at 4:1-8.
`
`
`35. The 181 Patent purports to disclose an improved redundancy scheme
`
`for repairing defective memory cells. In particular, the alleged point of novelty of
`
`the 181 Patent is the ability to use spare memory in one memory block to replace
`
`defective memory in other blocks. This allegedly improves the efficiency with
`
`
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`15
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`MICRON-1007.018
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`which the spare memory is utilized. MICRON-1001, 181 Patent at Abstract (“A
`
`spare memory array having spare memory cells common to a plurality of normal
`
`sub-arrays having a plurality of normal memory cells is provided. A spare line in
`
`the spare array can replace a defective line in the plurality of normal sub-array. The
`
`defective line is efficiently repaired by replacement in an array divided into blocks
`
`or sub-arrays.”).
`
`36. Although numerous embodiments of the alleged invention are
`
`disclosed, the challenged claims are directed to the third embodiment, which
`
`concerns repairing defective memory cells in a particular memory block within a
`
`group of memory blocks aligned in the column (vertical and bit line) direction.
`
`The third embodiment is depicted in Figure 9 and described at 16:12-17:25. Figure
`
`9 is reproduced below:
`
`MICRON-1001, 181 Patent at Figure 9 (annotated).
`
`
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`16
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`
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`MICRON-1007.019
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`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`37.
`
`In Figure 9, the memory array is divided into a row blocks RBX#0 to
`
`
`
`RBX#m along the column direction. See id. at 16:14-16. The row blocks RBX#1
`
`to RBX#m are formed by “normal memory sub-arrays MA#1 to MA#m,” which
`
`consist of normal memory cells arranged in a matrix of rows and columns. Id. at
`
`16:16-19. As shown, in this embodiment, the row blocks are aligned in the column
`
`direction—i.e., the row blocks are aligned vertically along the bit line direction.
`
`38. Row block RBX#0 includes a normal memory sub-array MA#0 with
`
`memory cells arranged in a matrix of rows and columns and a spare array SPX#
`
`having spare memory cells arranged in a plurality of rows and sharing the columns
`
`with normal memory sub-array MA#0:
`
`Row block RBX0 includes a normal memory sub-array
`MA#0 having normal memory cells arranged in a matrix
`of rows and columns, and a spare array SPX# having
`spare memory cells arranged in a plurality of rows and
`sharing the columns with normal memory sub-array
`MA#0.
`
`MICRON-1001, 181 Patent at 16:19-24.
`
`
`39. Thus, in Figure 9, each “row block” consists of sub-arrays of normal
`
`memory cells and, in the case of RBX#0, a spare array of memory cells. The 181
`
`Patent discloses that “[t]he number of spare word lines SWL included in spare
`
`array SPX# is arbitrary.” MICRON-1001, 181 Patent at 17:18-19. Further, row
`
`
`
`17
`
`MICRON-1007.020
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`decoders X0 to Xm are provided for normal memory sub-arrays MA#0 to MA#m,
`
`and a spare row decoder circuit SPDX is provided for spare array SPX#. See id. at
`
`16:27-30.
`
`40.
`
`In this embodiment, the “plurality of spare rows (spare word lines)
`
`included in spare array SPX# can replace defective normal word lines included in
`
`normal memory sub-arrays MA#0 to MA#m.” Id. at 16:24-27. Id. at 16:31-33
`
`(“In the configuration shown in FIG. 9, spare array SPX# is provided in common
`
`to normal memory sub-arrays MA#0 to MA#m.”).
`
`41. The 181 Patent alleges that allowing the spare rows in SPX# to
`
`replace the memory cells in MA#0 to MA#m will improve the efficiency with
`
`which the spare lines are used and simplify the control operations when replacing
`
`defective memory cells:
`
`As a result, if defective rows concentrate in one normal
`memory sub-array, spare word lines included in spare
`array SPX# can be used for repairing by replacement,
`and therefore the yields of the products can be improved.
`A spare row decoder is shared among a plurality of
`normal memory sub-arrays (row blocks) and therefore
`the number of spare decoders can be reduced.
`
`MICRON-1001, 181 Patent at 16:33-39.
`
`
`
`
`18
`
`MICRON-1007.021
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`Since spare word lines are shared among normal memory
`sub-arrays MA#0 to MA#m, and therefore the use
`efficiency of spare word lines can be improved.
`
`Id. at 17:2-4.
`
`
`By providing spare array SPX# in common to normal
`memory sub-arrays MA#0 to MA#m in row block
`RBX#0, spare word line SWL included in spare array
`SPX# can be used by an arbitrary normal memory sub-
`array, and the use efficiency of spare word lines can be
`improved.
`
`Id. at 17:5-9.
`
`
`Since spare array SPX# is included in normal memory
`sub-array MA#0, a sense amplifier provided for row
`block RBX0 has only to be activated when one of spare
`decoders SDX0 to SDX3 is selected, and therefore the
`control operation of the sense amplifier is simplified.
`
`Id. at 17:10-14.
`
`
`As in the foregoing, according to the third embodiment
`of the invention, spare word lines are collectively
`provided in a single spare array for common use among a
`plurality of normal memory sub-arrays, the number of
`spare row decoders is reduced, and the use efficiency of
`spare word lines is improved.
`
`Id. at 17:20-25.
`
`
`
`19
`
`MICRON-1007.022
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`
`VI. 181 PATENT PROSECUTION HISTORY
`I have reviewed the prosecution history of the 181 Patent.
`42.
`
`43. The application that led to the issuance of the 181 Patent was
`
`originally filed with 20 claims. MICRON-1002, 181 Patent File History, 2-17-
`
`1999 Original Claims at .140-.147.
`
`44. On January 10, 2000, the Examiner found that Figures 1, 5, 9, 11, 17,
`
`21A, and 41 were each patentably distinct species of the claimed invention and
`
`issued a restriction requirement. See id., 1-10-2000 Office Action at .449.
`
`45.
`
`In response, the Applicant elected the species of Figure 9, which
`
`corresponded to original claims 4-6. See id., 2-10-2000 Response to Election
`
`Requirement at .452. Original claims 4-6 ultimately issued as claims 1-3. In the
`
`discussion below, I will refer to original claims 4-6 as claims 1-3 for convenience.
`
`46. On April 12, 2000, the Examiner issued a non-final rejection finding
`
`claims 1-3 anticipated by the disclosure of two prior art references: (1) Figures 3A
`
`and 3B of U.S. Patent No. 5,761,138 (“Lee”) (MICRON-1003); and (2) Figure 3 of
`
`U.S. Patent No. 5,892,718 (“Yamada”) (MICRON-1004). MICRON-1002, 181
`
`Patent File History, 4-12-2000 Non-Final Rejection at .456.
`
`47.
`
`In a October 11, 2000 Amendment, the Applicant made several
`
`amendments to the claims. Notably, the Applicant amended claim 1 to require that
`
`the plurality of first memory blocks were aligned in the column direction. See id.,
`
`
`
`20
`
`MICRON-1007.023
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`10-11-2000 Amendment at .460. The Applicant also added dependent claims 21-
`
`24. For reference, the following is a table listing the original claim numbers and
`
`issued claim numbers:
`
`Original Claim Issued Claim
`4
`1
`5
`2
`6
`3
`21
`6
`22
`7
`23
`4
`24
`5
`
`48.
`
`In the remarks, the Applicant asserted that claim 1 “recites that (a) the
`
`
`
`first memory blocks are aligned in the column direction, and (b) each row of the
`
`plurality of first spare memory cells are [sic] capable of replacing a defective row
`
`including a defective normal memory cell in the plurality of first memory blocks.”
`
`See id., 10-11-2000 Amendment at .464 (underline in original). The Applicant
`
`further stated that these features are shown in Figure 9. See id.
`
`49. With respect to Lee (MICRON-1003), the Applicant argued that,
`
`although Figures 3A and 3B disclosed a redundant memory cell array that could
`
`replace memory cells in a plurality of arrays aligned in the row direction, they did
`
`not disclose redundant memory cells that could replace memory cells in a plurality
`
`of arrays aligned in the column direction:
`
`In this regard, in Figs. 3A and 3B of Lee, et al., memory
`cell arrays MCA1 and MCA3 are aligned in the column
`
`
`
`21
`
`MICRON-1007.024
`
`

`
`Petition for Inter Partes Review of 6,233,181
`Ex. 1007 (“Baker Decl.”)
`
`
`direction, and memory cell arrays MCA2 and MCA4 are
`also aligned in the column direction. While redundant
`memory cell arrays RCA1 and RCA2 are provided to the
`memory cells array MCA2 and MCA4, no redundant
`memory cell array is provided to the memory cell arrays
`MCA1 and MCA3. Thus, Lee, et al. fails to describe the
`claimed feature of a plurality of first spare memory cells,
`of which each rows is capable of replacing a defective
`row including a detective memory cell in a plurality of
`memory blocks (MCA1, MCA3) aligned in the column
`direction.
`
`MICRON-1002, 181 Patent File History, 10-11-2000 Amendment at .464-.465
`
`(underline in original).
`
`50. With respect to Yamada (MICRON-1004), the Applicant argued that
`
`claim 1 requires “‘a plurality of first spare memory cells arranged in a matrix of
`
`rows and columns in a particular one of said plurality of first memory blocks.’” Id.
`
`at .465 (underline in original). The Applicant explained that Figure 9 “shows spare
`
`array SPX# arranged in a particular one (normal memory sub-array MA#0) of the
`
`first memory