UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Declaration of R. Jacob Baker, Ph.D. in Support of
`Petition For Inter Partes Review
`of U.S. Patent No. 5,894,441
`Under 37 C.F.R. § 1.68
`
`
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.
`Petitioner
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 5,894,441
`Title: SEMICONDUCTOR MEMORY DEVICE
`WITH REDUNDANCY CIRCUIT
`________________________
`
`MICRON-1003.001
`
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Declaration of R. Jacob Baker, Ph.D. in Support of
`Petition For Inter Partes Review
`of U.S. Patent No. 5,894,441
`Under 37 C.F.R. § 1.68
`
`
`
`
`
`
`
`
`MICRON TECHNOLOGY, INC.
`Petitioner
`
`v.
`
`LIMESTONE MEMORY SYSTEMS LLC
`Patent Owner
`
`________________________
`
`Case IPR. No. Unassigned
`U.S. Patent No. 5,894,441
`Title: SEMICONDUCTOR MEMORY DEVICE
`WITH REDUNDANCY CIRCUIT
`________________________
`
`MICRON-1003.001
`
`
`
`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`
`
`TABLE OF CONTENTS
`
`I.
`INTRODUCTION ........................................................................................... 3
`BACKGROUND AND QUALIFICATIONS ................................................. 3
`II.
`III. UNDERSTANDING OF THE GOVERNING LAW ..................................... 6
`A. Anticipation ........................................................................................... 6
`B.
`Obviousness ........................................................................................... 7
`IV. MATERIALS RELIED ON IN FORMING MY OPINION........................... 8
`V. OVERVIEW OF THE 441 PATENT .............................................................. 9
`A.
`Background Technology Overview ...................................................... 9
`B.
`The 441 Patent .....................................................................................13
`VI. PROSECUTION HISTORY .........................................................................21
`VII. CLAIM CONSTRUCTION ..........................................................................21
`A.
`“transfer gate” ......................................................................................22
`VIII. LEVEL OF ORDINARY SKILL IN THE ART ...........................................23
`IX. DESCRIPTION OF THE PRIOR ART ........................................................24
`A. McAdams ............................................................................................24
`B. Minami ................................................................................................31
`X. GROUNDS OF INVALIDITY .....................................................................35
`A. Ground #1: Claims 1-3 and 5 are anticipated by McAdams ...............35
`B.
`Ground #2: Claims 3 and 6-15 are obvious over McAdams in
`view of Minami ...................................................................................35
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`2
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`MICRON-1003.002
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`
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`
`I, R. Jacob Baker, hereby declare as follows:
`INTRODUCTION
`I.
`
`1. My name is R. Jacob Baker. My findings, as set forth herein, are
`
`based on my education and background in the fields discussed below.
`
`2.
`
`I have been retained on behalf of Petitioner Micron Technology, Inc.
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`(“Micron”) to provide this Declaration concerning technical subject matter relevant
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`to the inter partes review petition (“Petition”) concerning U.S. Patent No.
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`5,894,441 (“the 441 Patent,” MICRON-1001). I reserve the right to supplement
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`this Declaration in response to additional evidence that may come to light.
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`3.
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`I am over 18 years of age. I have personal knowledge of the facts
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`stated in this Declaration and could testify competently to them if asked to do so.
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`4. My compensation is not based on the resolution of this matter.
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`II. BACKGROUND AND QUALIFICATIONS
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`5.
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`I currently serve as a Professor of Electrical and Computer
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`Engineering at the University of Nevada, Las Vegas (UNLV). I have been
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`teaching electrical engineering at UNLV since 2012. Prior to this position, I was a
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`Professor of Electrical and Computer Engineering at Boise State University from
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`2000. Prior to my position at Boise State University, I was an Associate Professor
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`Electrical Engineering between 1998 and 2000 and Assistant Professor of
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`3
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`MICRON-1003.003
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`
`
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`Electrical Engineering between 1993 and 1998 at the University of Idaho. I have
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`been teaching electrical engineering since 1991.
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`6.
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`I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
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`from UNLV in 1988 and 1986, respectively.
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`7.
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`As described
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`in my CV (MICRON-1004), I am a
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`licensed
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`Professional Engineer in the state of Idaho and have more than 25 years of
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`experience, including extensive experience in circuit design and manufacture of
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`Dynamic Random Access Memory (DRAM) integrated circuit chips and CMOS
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`Image Sensors (CISs) at Micron in Boise, Idaho. I also spent considerable time
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`working on the development of Flash Memory while at Micron. My efforts
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`resulted in more than a dozen Flash-memory related patents. Among other
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`experiences, I led development of the delay-locked loop (DLL) in the late 90s so
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`that Micron products could transition to the DDR memory standard. I have
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`worked as a consultant at other companies designing memory chips, including Sun,
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`Oracle, and Contour Semiconductor. I have also worked as a consultant at other
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`companies designing CIS’s, including OmniVision and Lockheed Martin.
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`8.
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`I have taught courses in integrated circuit design (analog, digital,
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`mixed-signal, etc.), linear circuits, microelectronics, communication systems, and
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`4
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`MICRON-1003.004
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`
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`fiber optics. As a professor, I have been the main advisor to five Doctoral students
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`and over 50 Masters students.
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`9.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
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`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
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`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and co-
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`authored, more than 75 papers and presentations in the areas of solid-state circuit
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`design, and I am the named inventor on over 135 granted U.S. patents in integrated
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`circuit designs including flash memory and DRAM.
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`10.
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`I have received numerous awards for my work, including the
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`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
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`Award is bestowed annually upon an outstanding young electrical/computer
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`engineering educators in recognition of the educator’s contributions to the
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`profession.
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`11.
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`I am a Fellow of the IEEE for contributions to memory circuit design.
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`I have also received the IEEE Circuits and Systems Education Award (2011).
`
`12.
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`I have received the President’s Research and Scholarship Award
`
`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
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`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`5
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`MICRON-1003.005
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`
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`University. I have also received the Tau Beta Pi Outstanding Electrical and
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`Computer Engineering Professor award the three years I have been at UNLV.
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`III. UNDERSTANDING OF THE GOVERNING LAW
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`13.
`
`I have been asked to provide my opinions regarding whether claims 1-
`
`3 and 5-15 of the 441 Patent are anticipated or would have been obvious to a
`
`person having ordinary skill in the art at the time of the alleged invention, in light
`
`of the prior art.
`
`A. Anticipation
`I have been informed that a patent claim is invalid as anticipated
`14.
`
`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
`
`is found either explicitly or inherently in a single prior art reference.
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`15.
`
`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
`
`if the claimed invention was known or used by others in the U.S., or was patented
`
`or published anywhere, before the applicant's invention. I further have been
`
`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
`
`patented or published anywhere, or was in public use, on sale, or offered for sale in
`
`this country, more than one year prior to the filing date of the patent application
`
`(critical date). I further have been informed that a claim is invalid under 35 U.S.C.
`
`§ 102(e) if an invention described by that claim was disclosed in a U.S. patent
`
`6
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`MICRON-1003.006
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`
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`granted on an application for a patent by another that was filed in the U.S. before
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`the date of invention for such a claim.
`
`B. Obviousness
`I have been informed that a patent claim is invalid as “obvious” under
`16.
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`35 U.S.C. § 103 if it would have been obvious to one of ordinary skill in the art,
`
`taking into account (1) the scope and content of the prior art, (2) the differences
`
`between the prior art and the claims, (3) the level of ordinary skill in the art, and
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`(4) any so called “secondary considerations” of non-obviousness, which include:
`
`(i) “long felt need” for the claimed invention, (ii) commercial success attributable
`
`to the claimed invention, (iii) unexpected results of the claimed invention, and (iv)
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`“copying” of the claimed invention by others. I further understand that it is
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`improper to rely on hindsight in making the obviousness determination. My
`
`analysis of the prior art is made as of the time the invention was made.
`
`17.
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`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. I further understand that
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`exemplary rationales that may support a conclusion of obviousness include:
`
`(A) Combining prior art elements according to known methods to yield
`
`predictable results;
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`(B) Simple substitution of one known element for another to obtain
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`predictable results;
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`7
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`MICRON-1003.007
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`(C) Use of known technique to improve similar devices (methods, or
`
`products) in the same way;
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`(D) Applying a known technique to a known device (method, or product)
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`ready for improvement to yield predictable results;
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`(E) “Obvious to try” – choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success;
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`(F) Known work in one field of endeavor may prompt variations of it for use
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`in either the same field or a different one based on design incentives or other
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`market forces if the variations are predictable to one of ordinary skill in the
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`art;
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`(G) Some teaching, suggestion, or motivation in the prior art that would
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`have led one of ordinary skill to modify the prior art reference or to combine
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`prior art reference teachings to arrive at the claimed invention.
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`IV. MATERIALS RELIED ON IN FORMING MY OPINION
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`18.
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`In addition to reviewing U.S. Patent No. 5,894,441, I also reviewed
`
`and considered:
`
`The prosecution history of the 441 Patent (MICRON-1002);
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`U.S. Patent No. 5,270,975 (“McAdams”) (MICRON-1005);
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`Japanese Patent Application No. H06-052696 (“Minami”) (MICRON-1006);
`
`8
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`MICRON-1003.008
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`
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`Excerpts from Betty Prince, Semiconductor Memories (2d ed. 1992)
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`
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`(“Prince”) (MICRON-1007).
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`
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`V. OVERVIEW OF THE 441 PATENT
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`A. Background Technology Overview
`19. The basic component of a semiconductor memory device is a memory
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`cell, which is a structure capable of storing a bit of digital data (a 1 or a 0). The
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`structure of a memory cell varies slightly depending on the type of semiconductor
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`memory device. In a dynamic random access memory (DRAM) semiconductor
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`device, for example, the memory cell consists of one capacitor for storing the
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`digital bit and one transistor. See MICRON-1007, Prince at .023. The Prince
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`textbook was a well-known resource in the field of semiconductor memory
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`devices. The excerpts produced at MICRON-1007 are from a copy of the textbook
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`that was stamped by the Library of Congress on March 26, 1992. See id. at .005.
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`20. The gate of the transistor of the memory cell is connected to a
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`conductive material that runs horizontally through the memory device called a
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`“word line.” The drain of the transistor is connected to a conductive material that
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`runs vertically through the memory device called a “bit line.” The source of the
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`9
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`MICRON-1003.009
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`
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`transistor, for example, is connected to the capacitor, which stores the digital bit.1
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`A diagram of a basic DRAM memory cell from the Prince textbook (MICRON-
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`1007) is reproduced below:
`
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`Figure 2.14: Basic MOS memory storage cells. (a) Dynamic RAM.
`MICRON-1007, Prince at .024 (annotated).
`
`21.
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`In the semiconductor industry, the term “word line” is synonymous
`
`
`
`with “row line.” The terms “bit line” and “column line” are also synonymous.
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`22. Memory cells aligned in the horizontal (row) direction are connected
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`to the same word line and memory cells aligned in the vertical (column) direction
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`can be connected to the same bit line. However, for divided bit line architectures,
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`1 The above example is for the case of writing a logical 1 to the memory cell.
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`However, when writing a logical zero, the capacitor of the memory cell is
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`discharged so current flows from the capacitor to the bit line. Thus, in this case,
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`the drain is connected to the capacitor and the source is connected to the bit line.
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`10
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`MICRON-1003.010
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`multiple bit lines exist within a single column. In a divided bit line architecture,
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`column selection lines activate the bit lines in the column. The 441 Patent relates
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`to a divided bit line architecture, and this architecture is discussed in more detail
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`below.
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`23.
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`In normal operations, data can be read to and written to the cells in the
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`memory array. For example, to read data from a cell, a row address is input and
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`decoded to select one of the 2N word lines. MICRON-1007, Prince at .029.
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`Because all of the memory cells aligned in the row direction are connected to the
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`same word line, all 2M cells in the selected word line are activated. See id. The
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`column decoder then addresses one bit line out of the 2M cells that have been
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`activated and routes the stored data in the cell to a sense amplifier. See id. In a
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`divided bit line architecture, the column decoded activates a column selection line,
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`which activates the bit lines along that column.
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`24. Memory cells in an array may further be subdivided into memory
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`blocks. See, e.g., id. at .047 (“Mostek [40] dealt with the RC delay and capacitive
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`coupling effects by using an innovative divided bit-line architecture which was
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`evolved from a combination of the folded-bit line techniques and the shared sense
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`amplifier concept as shown in Figure 6.25. This bit-line architecture divided the
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`long columns into 16 polysilicon bit-line segments of 64 cells each with eight
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`segments arranged end to end in a line on either side of a central column decoder.
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`11
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`MICRON-1003.011
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`Adjacent segments were grouped into pairs of open bit-lines to form eight
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`memory blocks of 128k bits each.”)2.
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`MICRON-1007, Prince at .048.
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`
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`25. Components, such as a column decoder, may be shared among
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`multiple memory arrays or blocks. See, e.g., id. at .047 (describing a DRAM
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`semiconductor device and stating that “[t]he column decoder and I/O bus lines are
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`shared by eight 64k memory arrays.”).
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`2 All emphases are added unless otherwise noted.
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`12
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`MICRON-1003.012
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`The 441 Patent
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`B.
`26. The 441 Patent is directed to a semiconductor memory device that
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`purportedly enhances the relief efficiency of defective bit lines by means of
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`redundant bit lines. MICRON-1001, 441 Patent at Abstract.
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`27. As described above, in a semiconductor memory device, a memory
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`array is essentially a matrix. Specifically, memory cells (“MC”) are located in a
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`grid at the intersection of word lines and bit lines, as shown in annotated Figure 1
`
`below.
`
`MICRON-1001, 441 Patent at Figure 1 (annotated).
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`
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`28. The figures of the 441 Patent generally have the rows shown
`
`horizontal whereas the columns are vertical (e.g., Figure 2). Figure 3 is an
`
`exception where the row is shown in a vertical orientation and the columns are
`
`shown horizontally. Accordingly, in many cases below, I rotate Figure 3 and place
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`13
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`MICRON-1003.013
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`
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`it next to Figure 2 so that two figures properly correspond to one another. Below is
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`an example where I rotate Figure 3 and place it to the right of Figure 2 in order to
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`show how the two figures correspond.
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`MICRON-1005, McAdams at Figures 2 and 3 (annotated).
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`
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`29. Almost all semiconductor memory devices
`
`include defective
`
`components (memory cells, word lines, bit lines, etc.) which are, of course,
`
`undesirable but artifacts of the manufacturing process. MICRON-1001, 441 Patent
`
`at 1:14-17. This is a natural result of fabricating semiconductor devices. Defective
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`14
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`MICRON-1003.014
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`components are expected since it is nearly impossible to fabricate a multi-million
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`transistor device without some defects. So that the memory can operate with the
`
`defects, it is and was the general practice to include redundancy circuits that allow
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`the manufacturer to disable the use of a defective component and replace it with a
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`redundant one. MICRON-1001, 441 Patent at 1:20-22. Furthermore, it was well
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`known to those of ordinary skill that in order to replace the maximum number of
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`defective word lines and/or bit lines, it was desirable to include as many redundant
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`components as practicable. This allows for higher yields, where “yields” refer to
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`the percentage of fabricated parts that can be sold, because a fabricated part with
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`numerous defective memory cells could still operate normally using redundancy
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`circuits. Thus, it was well known to provide many different types of redundant
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`components, such as redundant column and bit lines, and/or redundant row and
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`word lines, and to provide corresponding redundancy circuitry to activate and
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`utilize those redundant components. The 441 Patent specifically relates to
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`providing redundant bit lines (and column selection lines to activate the bit lines).
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`30. There is a known tradeoff when providing redundancy circuits with
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`redundant components. Specifically, while providing additional redundancy
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`circuits may increase yield, the redundant components, such as word and bit lines,
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`and their corresponding redundancy circuitry require additional silicon space and
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`thus come at a cost. MICRON-1001, 441 Patent at 1:37-41. The 441 Patent
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`15
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`MICRON-1003.015
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`purports to increase the relief efficiency of the redundant bit lines so that less
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`redundant lines are needed, thus reducing cost. MICRON-1001, 441 Patent at 2:8-
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`13. In other words, the 441 Patent allegedly teaches using redundant word and bit
`
`lines more efficiently.
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`31. As I noted above, in my opinion, the alleged invention is directed to a
`
`semiconductor device with a divided bit line architecture. MICRON-1001, 441
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`Patent at 3:1-2. This means that, “in the same column, a bit line is divided into
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`plural parts . . .” MICRON-1001, 441 Patent at 3:23-27. That is, there are multiple
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`bit lines along a single column. This architecture is called a “divided bit line”
`
`architecture because rather than a single bit line in the column direction, it is
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`divided into different bit lines. This structure is depicted in Figure 1 seen below.
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`MICRON-1001, 441 Patent at Figure 1 (annotated).
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`MICRON-1003.016
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`32. The above annotated Figure 1 depicts a single column selection line
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`
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`(122) that is connected to multiple sense amplifiers (124, 126). MICRON-1001,
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`441 Patent at 3:22-34. The column selection line activates the bit lines along the
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`column. These sense amplifiers are each connected to different bit lines (the sense
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`amplifiers detect, i.e., “sense,” the data that the respective memory cells are
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`storing). These bit lines intersect two different word lines (118, 120). MICRON-
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`1001, 441 Patent at 3:18-34. The memory cells are at the intersection of the word
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`lines and the bit lines. MICRON-1001, 441 Patent at 3:18-34.
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`33.
`
`In the conventional manner, the 441 Patent describes that when a
`
`memory cell is written or read, a column and row address are provided that specify
`
`the particular memory cell. MICRON-1001, 441 Patent at 3:6-9. As shown above
`
`in Figure 1, the prior art approach is that (1) the row address X is provided to the
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`row decoder 106 which activates the appropriate word line, and (2) the column
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`address Y is provided to the column decoder 108 which activates the designated
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`column select line. Id. at 3:9-16. “[W]hen the column selection line 122 is
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`activated in response to a Y address, [multiple] sense amplifiers are selected
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`simultaneously.” MICRON-1001, 441 Patent at 3:28-31. “However, only the data
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`corresponding to an activated word line is selected finally out of the [multiple]
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`selected.” MICRON-1001, 441 Patent at 3:32-34.
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`MICRON-1003.017
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
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`34. Regarding redundancy, as shown in Figure 1, the column address Y is
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`
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`also provided to a redundancy column decoder 116. MICRON-1001, 441 Patent at
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`3:6-9.
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`MICRON-1001, 441 Patent at Figure 1 (annotated).
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`
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`35.
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`If the column address corresponds to a column with a defective bit
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`line, then the column redundancy decoder will cause a redundant column selection
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`line (with redundant bit lines) to be activated. Id. at 3:53-60. This redundancy
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`decoder simply determines whether there was a defective column (by using its
`
`address), and if that is the case, it activates a redundant column. The regular
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`column decoder 108 is also inhibited from activating the column with a defective
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`bit line. Id. As I describe below, whether or not to inhibit the regular column is a
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`18
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`MICRON-1003.018
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`design tradeoff, as it reduces power consumption but increases the complexity of
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`Petition for Inter Partes Review of 5,894,441
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`the logic circuitry.
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`36. According to the 441 Patent, the problem with the prior art approach
`
`depicted in Figure 1 is that all of the bit lines along a single column are replaced
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`even if only one of the bit lines is defective. MICRON-1001, 441 Patent at 3:62-
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`65. That is, even though there are multiple bit lines along a column, if any of them
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`are defective, the entire column is replaced. This may be inefficient because
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`perhaps only one of a plurality of bit lines is defective.
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`37. The 441 Patent purports to correct this inefficiency by enabling a
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`single redundant column selection line to partially replace components from
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`different columns. See, e.g., MICRON-1001, 441 Patent at 7:25-29 (“In other
`
`words, half of the single redundant column selection line 230 replaces half of the
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`column selection line 222, and the remaining half of the same redundant column
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`selection line 230 replaces half of the column selection line 290.”). In other words,
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`a redundant column including, for example, 8 bit lines, could potentially replace 8
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`defective bit lines—even if those bit lines are in different columns.
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`38. The 441 Patent teaches using a portion of the row address in addition
`
`to the column address when determining whether to activate a redundant column
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`selection line. See MICRON-1001, 441 Patent at Figure 2 (showing XA0 and
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`19
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`MICRON-1003.019
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`
`
`
`XA1, part of the row address X, being passed to the column redundancy decoder
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`216 along with the column address Y).
`
`MICRON-1001, 441 Patent at Figure 2 (annotated).
`
`
`
`39.
`
`If the portion of the row address is associated with a selection of rows
`
`connected to a defective bit line and the column address is associated with a
`
`defective bit line, then the redundant column selection line is activated. However,
`
`if the portion of the row address is not associated with a selection of rows
`
`connected to a defective bit line and the column address is associated with a
`
`defective bit line, then the regular column selection line is activated. Using the
`
`20
`
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`MICRON-1003.020
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`
`
`
`row address enables isolating the specific bit line along the column (or a subset of
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`bit lines) that is defective, and thus the entire column does not require replacing.
`
`40.
`
`In sum, the 441 Patent teaches that only the portion of the column
`
`select line with the defective bit line needs to be replaced with a portion of the
`
`redundant column selection line as opposed to replacement of the entire line. This
`
`allows the other portions of the redundant column selection line to be used to
`
`correct other defects in other lines, thus increasing efficiency. Again, going back
`
`to the above, a redundant column including, for example, 8 bit lines, could
`
`potentially replace 8 defective bit lines—even if those bit lines are in different
`
`columns.
`
`VI. PROSECUTION HISTORY
`
`41.
`
`42.
`
`I have reviewed the prosecution history of the 441 Patent.
`
`It is my understanding that the examiner allowed all 15 claims in the
`
`first office action without any rejections. The examiner noted in the Reasons for
`
`Allowance that “[t]he PRIOR ART fails to disclose or suggest such a column
`
`redundant circuit responsive to the row address as described above . . .”
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`MICRON-1002, 11-23-1998 Notice of Allowability at .090.
`
`VII. CLAIM CONSTRUCTION
`
`43.
`
`I understand that in deciding whether to institute inter partes review,
`
`“[a] claim in an unexpired patent shall be given its broadest reasonable
`
`21
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`MICRON-1003.021
`
`
`
`
`construction in light of the specification of the patent in which it appears.” 37
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`C.F.R. § 42.100(b). I understand that this claim construction standard is different
`
`from—and typically broader than—that applied in district court. I further
`
`understand that “the broader standard serves to identify ambiguities in the claims
`
`that can then be clarified through claim amendments.” Final Rule, 77 Fed. Reg.
`
`48680, 48699 (Aug. 14, 2012).
`
`44.
`
`I applied this broadest reasonable construction standard to my review
`
`of the claims of the 441 Patent discussed below.
`
`“transfer gate”
`
`A.
`45. One of ordinary skill in the art would have understood at the time of
`
`filing of the 441 Patent that the plain and ordinary meaning of “transfer gate” is
`
`“logic that transfers the logic value of a signal.”
`
`46. The specification and claims describes the operation of the transfer
`
`gates disclosed in the patent as transferring a signal. For example, claim 13
`
`requires that the “first transfer gate being activated to transfer said first matching
`
`signal to said redundant column selection line . . .”. Further, the specification
`
`describes the functionality of transfer gate 310 as outputting “the matching signal
`
`306 as the YRED when XAO is at the high level” and the functionality of the transfer
`
`gate 312 as outputting “the matching signal 308 as the YRED when XA1 is at the
`
`high level.” MICRON-1001, 441 Patent at 5:55-61.
`
`22
`
`
`MICRON-1003.022
`
`
`
`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`47. The pictorial representations of the transfer gates in the Figures appear
`
`
`
`to be a pair of transistors which pass a signal 310 or 312 from the drain to the
`
`source of the transistors as controlled by a row address XA0, XA1.
`
`MICRON-1001, 441 Patent at Figure 3.
`
`
`
`48. However, there is nothing in the specification that limit the claimed
`
`“transfer gates” to that particular embodiment. Many different types of logic
`
`arrangements may “transfer” a signal. For example, a signal may turn on a
`
`transistor that pulls a signal high or low, thereby transferring the logical value of its
`
`signal to additional circuitry.
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`
`49.
`
`In my opinion, a person having ordinary skill in the art at the time of
`
`the claimed inventions would have had a bachelor’s degree in computer
`
`engineering, electrical engineering, computer science, or a closely related field,
`
`23
`
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`MICRON-1003.023
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`
`
`
`along with at least 2-3 years of experience in the design of memory devices. An
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`individual with an advanced degree in a relevant field, such as computer or
`
`electrical engineering, would require less experience in the design of memory
`
`devices.
`
`50. My opinion below explains how one of ordinary skill in the art would
`
`have understood the technology described in the references I have identified herein
`
`around the 1997 time period. I had at least ordinary skill in the art in 1997.
`
`IX. DESCRIPTION OF THE PRIOR ART
`
`A. McAdams
`51. U.S. Patent No. 5,270,975 (“McAdams”, MICRON-1005) entitled
`
`“Memory Device Having A Non-Uniform Redundancy Decoder Arrangement”
`
`issued to Hugh McAdams, and was assigned to Texas Instruments Incorporated.
`
`McAdams was filed with the USPTO on August 13, 1992 and issued on December
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`14, 1993. I have been informed that McAdams is prior art to the 441 Patent under
`
`at least (pre-AIA) 35 U.S.C. § 102(b) because the patent issued more than one year
`
`before the application that led to the 441 Patent was filed on March 31, 1998.
`
`52. Like the 441 Patent, McAdams is directed to a semiconductor
`
`memory device with redundant column select lines and redundant bit lines.
`
`MICRON-1005, McAdams at 5:57-60, 6:43-48. Both McAdams and the 441
`
`Patent are directed towards solving the same problem of space efficiency for
`
`24
`
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`MICRON-1003.024
`
`
`
`
`redundancy schemes, and both are within the context of a divided bit line
`
`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`architecture. Id. at 3:3-7.
`
`53. The semiconductor memory device of McAdams has an array of
`
`memory cells arranged into addressable rows and columns along row lines and
`
`column lines. MICRON-1005, McAdams at 22:28-32. The array is broken up into
`
`16 sub-blocks of a specified number of rows as shown in Figure 2.
`
`
`MICRON-1005, McAdams at Figure 2 (annotated).
`
`54. Each one of the different sub-blocks (14) has separate bit line
`
`segments. MICRON-1005, McAdams at Figure 3. However, the column select
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`lines YS and YRS run through each of the sub-blocks as shown in Figures 2 and 3
`
`below (two copies of Figure 3 to illustrate the two blocks):
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`25
`
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`MICRON-1003.025
`
`
`
`
`
`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`MICRON-1005, McAdams at Figures 2 and 3 (annotated).
`
`
`
`55. Each of the annotations below with regards to Figure 2 shows the
`
`column select lines as being connected.
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`26
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`MICRON-1003.026
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`
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`Petition for Inter Partes Review of 5,894,441
`MICRON-1003 (“Baker Decl.)
`
`MICRON-1005, McAdams at Figure 2 (annotated).
`
`
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`56. There is a single column selection line because, for example, there is a
`
`single column decoder at the bottom as seen above in Figure 2. In other words,
`
`there is only a single column decoder, so it would have been understood to activate
`
`a single column selection line that runs the lengths of the entire column.
`
`Otherwise, only the bottom block, for example, would be functional. Again, like
`
`the 441 Patent, McAdams teaches a divided bit line architecture because there are
`
`multiple bit lines along a single column that are selected by a single co
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