United States Patent [19]
`Nakazawa
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`WITH REDUNDANCY CIRCUIT
`
`[75]
`
`Inventor: Shigeyuki Nakazawa, Tokyo, Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 09/050,354
`
`[22] Filed:
`
`Mar. 31, 1998
`
`[30]
`
`Foreign Application Priority Data
`
`[JP]
`
`Japan .................................... 9-081203
`
`Mar. 31, 1997
`Int. Cl.6
`....................................................... GllC 7/00
`[51]
`[52] U.S. CI ................. 365/200; 365/230.03; 365/230.06
`[58] Field of Search ..................................... 365/200. 201.
`365/230.03, 230.06
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Ill
`
`11111111111111~ 11111111111111111
`5,894,441
`Apr. 13, 1999
`
`US005894441A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,359,560 10/1994 Sub et al ................................. 365/200
`5,798,974
`8/1998 Yamagata ................................ 365/200
`9/1998 Kim et al ................................ 365/200
`5,808,948
`
`Pri11Wry Examiner-Vu A. Le
`Attorney, Agent, or Fi~ugluue. Mion, Zion. Macpeak
`& Seas, PLLC
`
`[57]
`
`ABSTRACT
`
`A semiconductor memory device which enhances the relief
`efficiency of defective bit lines by means of redundant bit
`lines is disclosed. To a column redundancy decoder are
`supplied not only a Y address but also a part of an X address.
`When a Y address corresponding to a defective bit line is
`supplied to the column redundancy decoder. the column
`redundancy decoder generates a detection signal. In this
`case, replacement by means of a redundant bit line is carried
`out if the part of the X address indicates a region where the
`defective bit line exists. and the replacement by means of a
`redundant bit line will not take place if it indicates a region
`where the defective bit line does not exists.
`
`9/1994 Lee .......................................... 365/200
`5,349,556
`5,355,339 10/1994 Oh et al .................................. 365/200
`
`15 Claims, 8 Drawing Sheets
`
`216' 616'
`'
`;
`
`XAO
`
`y
`
`--.
`.
`.
`l .
`
`.
`.
`• .
`
`XA1
`
`.
`.
`.
`.
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`
`308
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`
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`
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`I
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`~
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`I
`I
`I
`
`I
`I
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`I
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`I
`I
`
`r
`
`:-;t-:
`:~r .. -312
`f
`
`~-- --'
`
`YRED
`
`MICRON-1001.001
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 1 of 8
`
`5,894,441
`
`X
`
`112
`
`106
`
`100
`
`
`-~
`
`118
`
`120
`
`•
`•
`
`•
`
`•
`•
`•
`
`•
`•
`
`FIG.1
`
`104
`
`102
`
`MC
`\124
`
`122
`
`130
`
`114
`
`MICRON-1001.002
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 2 of 8
`
`5,894,441
`
`200
`~
`
`206
`
`-
`
`•
`
`•
`•
`•
`•
`
`•
`•
`
`X
`
`FIG.2
`
`202
`
`218
`
`y
`
`XAO
`
`XA1
`
`XA0=1
`
`XA1=1
`
`YRED
`
`216
`
`MICRON-1001.003
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 3 of 8
`
`5,894,441
`
`FIG.3
`
`216' 616'
`'
`;
`
`XAO
`
`y
`
`.
`.
`.
`.
`
`.
`. .
`.
`
`XA1
`
`.
`.
`.
`.
`
`.
`.
`.
`.
`
`1'302
`
`~·
`
`: ;::::- ~--310
`1--l-
`: h:
`306 :~l
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`.0.
`
`t-- - - ..
`
`I
`I
`
`I
`
`I
`I
`
`YRED
`
`308
`~
`
`\.304
`
`I
`I
`I
`
`I
`
`:-t-:
`I
`I
`I
`--!---
`: h:
`: \$) r-- 312
`--- --·
`t
`
`I
`
`FIG.4
`
`y
`
`--- ------------------ -------------------,
`
`I
`I
`
`--402
`
`------------~-----------------------------'
`I \ 302,304,902,904
`
`MICRON-1001.004
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 4 of 8
`
`5,894,441
`
`FIG.5
`
`XAO _ ___,
`
`XA1
`
`-----~----------~
`
`306 - - - - f - - -1
`
`308 ___ ~~-------+-~
`
`YRED
`
`----------~
`
`230 ___ ---'
`
`MICRON-1001.005
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 5 of 8
`
`5,894,441
`
`FIG.6
`
`600
`
`/
`
`x·
`XAO
`
`XA1
`
`XAO
`
`y
`
`MICRON-1001.006
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 6 of 8
`
`5,894,441
`
`FIG.?
`
`/
`
`700
`
`706
`
`702
`
`718
`
`• VL - - - - - - , X'
`XAO
`•
`
`730
`
`XA1
`
`y
`
`XAIO
`
`XAI1
`
`750
`
`MICRON-1001.007
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 7 of 8
`
`5,894,441
`
`FIG.8
`
`750
`
`XAO o-----+-+----1
`802
`XAR 1 o-------1 ~t--'---+------.
`804
`XARO o----'1 ~r----'----.
`XA 1 o----------1
`
`810
`
`FIG.9
`
`XAIO
`
`y
`
`.
`.
`.
`.
`
`.
`.
`.
`.
`
`XAI1
`
`.
`.
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`
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`
`?
`906
`
`908
`~
`
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`
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`;
`
`I
`I
`
`I
`I
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`: 7:.= ~'- 91 0
`f-.1-
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`I
`I~:
`
`I
`I
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`
`YRED
`
`~
`
`I
`I
`
`--t-i
`+---:
`~f'-912
`-- __ I
`t
`
`MICRON-1001.008
`
`

`
`U.S. Patent
`
`Apr. 13, 1999
`
`Sheet 8 of 8
`
`5,894,441
`
`FIG.1 0
`
`I u
`
`\
`
`I u
`
`\
`
`XAO
`
`XA1
`
`XARO
`
`XAR1
`
`XAIO
`
`XAI1
`
`906
`
`908
`
`YRED
`
`730
`
`MICRON-1001.009
`
`

`
`5.894.441
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH REDUNDANCY CIRCUIT
`
`FIELD OF THE INVENTION
`The present invention relates to a semiconductor memory
`device equipped with a redundancy circuit, and more
`particularly, to a semiconductor memory device having an
`enhanced relief efficiency of a defective bit line by means of
`a redundant bit line.
`
`BACKGROUND OF THE INVENTION
`Accompanying fine geometry, high integration, and large
`capacity of the semiconductor memory devices in recent
`years, it is becoming extremely difficult to obtain perfect
`products which are absolutely free from defects. In other
`words, almost all of the produced semiconductor memory
`devices include defective memory cells, defective work
`lines. or defective bit lines. In order to make it possible to
`deliver semiconductor memory devices that include such
`defects as acceptable products, it is a general practice to
`provide the semiconductor memory device with a redun(cid:173)
`dancy circuit.
`The redundancy circuit is for disabling the use of a
`defective word or bit line when there exists one. and
`replacing the defective word or bit line with a redundant 25
`word or bit line. By designing a circuit configuration such
`that a defective word line or a defective bit line can be
`replaced by a redundant word line or a redundant bit line, as
`in the above, it is possible to deliver a semiconductor
`memory device as if it is absolutely free from defectiveness. 30
`Accordingly. a redundancy circuit contributes significantly
`to the enhancement of the yield of the semiconductor
`memory devices.
`In order to relieve as many defective word lines or
`defective word lines or defective bit lines as possible. it is 35
`most effective to incorporate as many redundant word lines
`or redundant bit lines as its practicable. However, since the
`redundancy circuit is a superfluous circuit in the sense that
`it is useless unless there exists defectiveness in the manu(cid:173)
`factured semiconductor memory device, it is not recom- 40
`mended to provide a large scale redundancy circuit within
`the semiconductor memory device. For this reason, it is
`desirable to relieve as many defective word lines or defec(cid:173)
`tive bit lines as possible with a minimum number of redun(cid:173)
`dant word lines or redundant bit lines.
`Under those circumstances, a variety of methods for
`improving the relief efficiency of defective word lines or
`defective bit lines by means of a redundant circuit have been
`proposed. As examples, there may be mentioned methods
`disclosed in U.S. Pat. No. 5349,556, U.S. Pat. No. 5355.
`339, U.S. Pat. No. 5.359.560. and U.S. Pat. No. 5.414.660.
`The method described in these patents is what is called the
`row flexible redundancy method. The row flexible redun(cid:173)
`dancy method is a technique for efficiently relieving the
`word line defects, which has a feature in that the range of
`replacement covered by one redundant word line is broad.
`However, according to the row flexible redundancy
`method. the relief efficiency for defective bit lines remains
`unchanged, although the relief efficiency for defective word
`lines can be improved. Because of this, a method which can
`also improve the relief efficiency for defective bit lines is in
`demand.
`
`2
`It is another object of this invention to provide a semi(cid:173)
`conductor memory device by which defective bit lines can
`be relieved by a smaller number of redundant bit lines.
`It is still another object of this invention to provide a
`5 semiconductor memory device which is capable of relieving
`a larger number of defective bit lines while minimizing the
`increase in the chip area.
`It is still another object of this invention to provide a
`semiconductor memory device equipped with a redundant
`10 circuit which is capable of improving the relief efficiency for
`defective bit lines while employing a row flexible redun(cid:173)
`dancy circuit.
`The semiconductor memory device according to this
`invention comprises a plurality of column selection lines, at
`15 least one redundant column selection line, a column decoder
`which activates one line out of the plurality of column
`selection lines in response to a column address. a first circuit
`which generates a detection signal when the column address
`of a defect-related column selection line is supplied, and a
`20 second circuit which receives at least a part of a row address.
`and activates the redundant column selection line in
`response to at least a part of the row address and the
`detection signal. With this arrangement. when defect occurs
`in one bit line, instead of replacing all of the many bit lines
`included in the column selection line to which the defective
`bit line belongs. it is possible to relieve a larger number of
`defective bit lines using a single redundant column selection
`line by replacing only a part of these bit lines.
`
`BRIEF DESCRJPTION OF THE DRAWINGS
`The above and other objects. advantages and features of
`the present invention will be apparent from the following
`description taken in conjunction with the accompanying
`drawings, in which:
`FIG. 1 is a block diagram showing a semiconductor
`memory device 100 with divided bit lines, which is an object
`of this invention;
`FIG. 2 is a block diagram showing a semiconductor
`memory device 200 according to a first embodiment of this
`invention;
`FIG. 3 is a circuit diagram showing a part of a column
`redundancy decoder 216 in FIG. 2;
`FIG. 4 shows a fuse blocks 302 and 304 shown in FIG. 3;
`FIG. S is a timing chart showing the timings for bit line
`replacement by the semiconductor memory device 200;
`FIG. 6 is a block diagram showing a semiconductor
`memory device 600 according to a second embodiment of
`this invention;
`FIG. 7 is a block diagram showing a semiconductor
`memory device 700 according to a third embodiment of this
`invention;
`FIG. 8 is a circuit diagram of a control circuit 750 in FIG.
`55 7;
`FIG. 9 is a circuit diagram showing a part of a column
`redundancy decoder 716 in FIG. 7; and
`FIG. 10 is a timing chart showing the timings for bit line
`replacement according to the semiconductor memory device
`60 700.
`
`50
`
`45
`
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a 65
`semiconductor memory device equipped with a redundancy
`circuit having a high relief efficiency.
`
`DErAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`First, referring to FIG. 1. the semiconductor memory
`device 100 which is the object of application of this inven(cid:173)
`tion will be described prior to detailed description of the
`semiconductor memory device of this invention.
`
`MICRON-1001.010
`
`

`
`20
`
`25
`
`30
`
`5.894.441
`
`10
`
`3
`A semiconductor memory device lot shown in FIG. 1 is
`a semiconductor memory device with divided bit lines. The
`cell array region of the semiconductor memory device 100
`consists of a normal cell array region 102 and a redundant
`cell array region 104.
`An X address (row address) is supplied to a row decoder
`106 and a row redundancy decoder 112. and a Y address
`(column address) is supplied to a column decoder 108 and
`a column redundancy decoder 116. Upon receipt of the X
`address the row decoder 106 activates one word line corre(cid:173)
`sponding to the X address out of a plurality of word lines.
`In FIG. 1. only word lines 118 and 120 are indicated for
`convenience. On the other hand. upon receipt of a Y address.
`the column decoder 108 activates one column selection line
`corresponding to the Y address out of a plurality of column 15
`selection lines. In FIG. 1. only the column selection line 122
`is indicated for convenience.
`Many memory cells MC are connected to each of the
`word lines 118 and 120. and respective memory cells MC
`are connected to sense amplifiers 124. 126, and the like.
`Here. it is to be noted that the column selection line 122
`activates the plurality of sense amplifiers 124. 126. and the
`like. That is. in the same column. a bit line is divided into
`plural parts. and the column decoder 108 selects all the sense
`amplifiers connected to the plurality of divided bit lines. in
`response to the Y address. Although only two bit lines are
`indicated in FIG. 1 for convenience, it will be assumed that
`the number of divided bit lines is actually 16. In other words.
`when the column selection line 122 is activated in response
`to a Y address, 16 sense amplifiers are selected simulta(cid:173)
`neously. However. only the data corresponding to an acti(cid:173)
`vated word line is selected finally out of the 16 selected
`sense amplifiers. and is readout.
`The row redundancy decoder 112 detects the supply of the 35
`X address corresponding to a defective word line. The row
`redundancy decoder 112 includes a plurality of fuse
`elements. and stores the X address corresponding to a
`defective word line according to whether or not these fuses
`are blown out. Namely, when the X address corresponding 40
`to a defective word line is supplied. the row redundancy
`decoder 112 supplies an inhibit signal 132 to the row
`decoder 106 to deactivate the row decoder 106. and activates
`a redundant word line driver 110 to activate a specified
`redundant word line 128. In this way. the defective word line 45
`is replaced by the redundant word line 128.
`On the other hand, the column redundancy decoder 116
`detects the supply of the Y address corresponding to a
`defective bit line. The column redundancy decoder 116 also
`includes a plurality of fuse elements. and stores the Y 50
`address corresponding to a defective bit line according to
`whether or not these fuses are blown out. In other words.
`when theY address corresponding to the defective bit line is
`supplied, the decoder 116 deactivates the column decoder
`108 by supplying an inhibit signal 134 to the column 55
`decoder 108. and activates the redundant column selection
`driver 114 in order to activate a specified redundant column
`selection line 130. In this way, the defective bit line is
`replaced by a redundant bit line (not shown) corresponding
`to the redundant column selection line 130.
`However, such a semiconductor memory device 100 has
`the following problem. Namely. if one bit line is defective.
`not only the defective bit line but also other bit lines that
`share the column selection line are replaced to the redundant
`bit lines. More specifically. as a result of defect in a bit line.
`for example. the bit line corresponding to the sense amplifier
`124. all of the 16 bit lines selected by the same column
`
`4
`selection line 122 are disabled. and all of the 16 bit lines are
`replaced to the redundant bit lines. Thus. many redundant bit
`lines will be wasted for a small number of bit line defects.
`In effect. it leads to the problem of deterioration of the relief
`5 efficiency of the defective bit lines.
`In the semiconductor memory devices according to each
`of the embodiments that will be described in the following.
`the above problem is resolved to realize a high relief
`efficiency.
`The semiconductor memory device according to a first
`embodiment of this invention 200 has a feature in that a
`column redundancy decoder 216 receives not only a Y
`address but also a part of an X address. as shown in FIG. 2.
`The remaining portions are basically the same as that of the
`semiconductor memory device 100 shown in FIG. 1.
`Namely. the semiconductor memory device 2M shown in
`FIG. 2 is a semiconductor memory device with divided bit
`lines. and the cell array region consists of a normal cell array
`region 202 and a redundant cell array region 204.
`In addition to an X address being supplied to a row
`decoder 206 and a row redundancy decoder 212. XAO and
`XA1 which show the logical level of the most significant bit
`of the X address are supplied also to the column redundancy
`decoder 216. As mentioned above. XAO and XAl are signals
`showing the logical level of the most significant bit of the X
`address. in which XAO is "1" and XAl is "0" when the most
`significant bit of the X address is 0. and on the contrary. XAO ·
`is "0" and XA1 is "1" when the most significant bit of the
`X address is 1. In short. XAO and XA1 are mutually
`complementary signals.
`On the other hand. a Y address is supplied to a column
`decoder 208 and the column redundancy decoder 216.
`Upon receipt of the X address. the row decoder 206
`activates one word line corresponding to the X address out
`of a plurality of word lines. In FIG. 2. only word line 218
`and word line 220 are indicated for convenience. On the
`other hand. upon receipt of the Y address. the column
`decoder 208 activates one column selection line correspond(cid:173)
`ing to the Y address out of a plurality of column selection
`lines. In FIG. 2. column selection lines 222 and 290 alone
`are indicated for convenience.
`Each of the word lines 218. 220, and the like is connected
`to a memory cell MC. and each memory cell MC is
`connected to a corresponding one of sense amplifiers 224.
`226. and the like.
`In the semiconductor memory device 200 shown in FIG.
`2. the column selection line 222 activates. as before. a
`plurality of sense amplifiers 224. 226, and the like. That is.
`analogous to the semiconductor memory device lot. a bit
`line is divided into plural parts in the same column. and the
`column decoder 208 selects all the sense amplifiers con(cid:173)
`nected to a plurality of divided bit lines in response to the Y
`address. Although only two bit lines are indicated in FIG. 2
`for convenience. it will be assumed that a bit line is actually
`divided into 16 parts as before. Namely. when the column
`selection line 222. 290. or the like is activated in response to
`a Y address. 16 sense amplifiers are selected simultaneously.
`Data corresponding only to the activated word line is
`60 selected finally out of the 16 sense amplifiers. and is read
`out.
`The row redundancy decoder 212 detects the supply of the
`X address corresponding to a defective word line. The row
`redundancy decoder 212 contains a plurality of fuse
`65 elements. and stores the X address corresponding to defec(cid:173)
`tive word lines depending upon whether or not these fuses
`are blown out. Typically. polysilicon is used for these fuses,
`
`MICRON-1001.011
`
`

`
`5.894.441
`
`25
`
`5
`but the present invention is not limited to this choice, and
`permits the use of any kind of material for the fuses. In
`addition, although laser irradiation is employed typically as
`the method of fuse bow-out, this invention is not limited to
`this case, and permits the use of any type of blow-out 5
`method. For example, the fuse may be blown out by the
`passing of a large current in the fuse.
`When an X address corresponding to a defective word
`line is received, the row redundancy decoder 212 deactivates
`the row decoder 206 by supplying an inhibit signal 232 to
`the row decoder 206, and activates a redundant word line
`driver 210 in order to activate a specified redundant word
`line 228. As a result, the defective word line is replaced to
`the redundant word line 228. Accordingly, it will look as if
`there exists no defect when seen from the outside.
`In the meantime, the column redundancy decoder 216
`detects that a Y address corresponding to a defective bit line
`is supplied. Referring to FIG. 3, a specific circuit diagram
`and the operation of the column redundancy decoder 216
`will be described.
`FIG. 3 shows a specific circuit configuration of the
`column redundancy decoder 216. but it does not show the all
`circuit parts that are included in the column redundancy
`decoder 216. Namely, the column redundancy decoder 216'
`shown in FIG. 3 illustrates only the circuit part correspond(cid:173)
`ing to one redundant column selection line YRED of the
`column redundancy decoder 216. According, in the decoder
`216, there actually exist as many column redundancy decod(cid:173)
`ers 216' as equals to the number of the redundant column
`selection lines YRED. For example. if there exist 8 redun(cid:173)
`dant column selection lines YRED, 8 column redundancy
`decoders 216' are needed, and if there exist 16 redundant
`column selection lines YRED, then 16 column redundancy
`decoders 216' are needed.
`As shown in FIG. 3, two fuse blocks 302 and 304 are
`included in the column redundancy decoder 216'. and theY
`address is supplied in common to these fuse blocks 302 and
`304. A specific circuit configuration of these fuse blocks 302
`and 304 is as shown in FIG. 4. As shown in FIG. 4. in the 40
`fuse blocks 302 and 304 are included a plurality of fuses
`402. and the Y address of a defective bit line is stored by
`programming the Y address of the defective bit line in these
`fuses 402. Namely, when theY address of a defective bit line
`is supplied to the fuse blocks 302 and 304 where the Y
`address of the defective bit line is programmed, a wiring 404
`goes to the ground potential, and matching signals 306 and
`308 go to a high level (active level). In contrast, when an
`address different from theY address of the defective bit line
`is supplied to the fuse blocks 302 and 304, the wiring 404
`is held at a potential V cc, and the matching signals 306 and
`308 are held at a low level (inactive level).
`That the material and the blow-out method to be
`employed by the fuse 402 are not limited is similar to the
`case of the row redundancy decoder 212.
`As shown in FIG. 3. the column redundancy decoder 216'
`further includes two transfer gates 310 and 312. The transfer
`gate 310 outputs the matching signal306 as the YRED when
`XAO is at the high level. and the transfer gate 312 outputs
`the matching signal 308 as the YRED when XA1 is at the
`high level. As mentioned above. XAO and XA1 are comple(cid:173)
`mentary signals showing the logical level of the most
`significant bit of the X address. so that either one of the
`transfer gates 310 or 312 is necessarily in the energized state
`and the other is in the deenergized state.
`Although it is not explicitly indicated in FIG. 3. when a
`YRED goes to the high level (active level). the inhibit signal
`
`6
`234 goes to the active level. and inhibits the operation of the
`column decoder 208.
`Next. the replacement operation of a defective bit line is
`the semiconductor memory device 200 will be described.
`As an example, the case in which a bit line corresponding
`to the sense amplifier 224 is defective will be described. In
`this case, the bit line corresponding the column selection line
`222 is defective, so the Y address corresponding to the
`column selection line 222 is programmed in the column
`10 redundancy decoder 216. What is important at this time is to
`program this Y address in the fuse block 302 within the
`column redundancy decoder 216.
`After programming in this manner. when the memory cell
`MC corresponding to the defective bit line is accessed. the
`15 fuse block 302 brings the matching signal 306 to the high
`level by detecting the matching of the Y signals. Further,
`since the defective bit line belongs to the cell array region
`where the most significant bit of the X address is 0. XAO is
`"1". and the transfer gate 310 goes to the energized state.
`20 Accordingly. the YRED goes to the active level. and corre(cid:173)
`sponding to this. the redundant column selection line drive
`214 activates the specifies redundant column selection line
`230. On the other hand. the operation of the column decoder
`208 is inhibited by the inhibit signal 234.
`As a result. the defective bit line is replaced to a redundant
`bit line belonging to the redundant column selection line.
`On the other hand. when a memory cell connected to a bit
`line belonging to a cell array region where the most signifi-
`30 cant bit of the X address is "1". among the other bit lines
`corresponding to the column selection line 222. is accessed,
`the replacement of the bit line is not carried out. The reason
`for this is that, although the fuse block 302 activates the
`matching signal 306 as a result of matching of the Y
`35 addresses, the transfer gate 310 is deenergized in this case.
`and the YRED is not activated. As a result of the nonacti(cid:173)
`vation of the YRED, the inhibit signal 234 is not activated
`either, and the column decoder 208 carries out the normally
`operation.
`In this connection. it should be noted that the above fact
`means that only half of the bit lines. namely, only those bit
`lines belonging to the cell array region where the most
`significant bit of the X address is "1 ", out of the bit lines
`corresponding to the column selection line 222. are replased
`45 to the redundant bit lines.
`Here. the case in which another bit line, for example, a bit
`line belonging to the cell array region where the most
`significant bit of the X address is "1" among the bit lines
`belonging to the column selection line 290. is defective. will
`so be described. In this case, since a bit line corresponding to
`the column selection line 290 is defective. the Y address
`corresponding to the column selection line 290 is pro(cid:173)
`grammed in the column redundancy decoder 216. What is
`important at this time is to program theY address in the fuse
`55 block 304 in the column redundancy decoder 216.
`After programming as in the above. when the memory cell
`corresponding to the defective bit line is accessed, the fuse
`block 304 brings the matching signal 308 to the high level
`by detecting the matching of the Y addresses. Since the
`60 defective bit line belongs to the cell array region where the
`most significant bit of the X address is "1" as mentioned
`above. XA1 is "1" so that the transfer gate 312 is energized.
`As a result. the YRED is activated, and in response to this,
`the redundant column selection line driver 214 activates the
`65 specified redundant column selection line 230. On the other
`hand, the operation of the column decoder 208 is inhibited
`by the inhibit signal 234.
`
`MICRON-1001.012
`
`

`
`5,894.441
`
`25
`
`30
`
`7
`In contrast to the above. when a memory cell connected
`to a bit line belonging to the cell array region where the most
`significant bit of the X address is 0. among the other bit lines
`corresponding to the column selection line 290, is accessed,
`the replacement of the bit line does not take place. The 5
`reason for this is that. although the fuse block 304 activates
`the matching signal 308 because of the matching of the Y
`addresses, the transfer gate 312 is deenergized in this case,
`so that the YRED is not activated. Because of the nonacti(cid:173)
`vation of the YRED. the inhibit signal 234 is not activated 10
`either. and the column decoder 208 carries out the normal
`operation.
`Attention is to be drawn again to the fact that this means
`that only half of bit lines, namely. bit lines belonging to the
`cell array region where the most significant bit of the X
`address is "1". among the bit lines corresponding to the
`column selection line 290. can be replased to the redundant
`bit lines.
`The above operation will be understood more clearly by
`examining the timing chart shown in FIG. 5. From FIG. 5 it
`can be seen that the matching signal 306 is generated only
`during the time when XAO is active. whereas the matching
`signal 308 is generated only during the time when XA1 is
`active.
`In other words. half of the single redundant column
`selection line 230 replaces half of the column selection line
`222. and the remaining half of the same redundant column
`selection line 230 replaces half of the column selection line
`290. In this manner. by replacing only half. rather than all.
`of the column selection lines that include a defective bit line.
`in response to the X address to which the defective bit line
`belongs. two bit line defects with mutually different column
`selection lines can be replaced to means of a single redun(cid:173)
`dant column selection line. Consequently. the relief effi(cid:173)
`ciency of the defective bit lines can be doubled.
`More specifically. when the redundant column selection
`lines equal in number to the redundant column selection
`lines contained in the semiconductor memory device 100 are
`installed in the semiconductor memory device 200. it is
`possible to relieve twice as many defective bit lines as the
`semiconductor memory device 100 can. Accordingly. the
`relief efficiency can be enhanced accompanied by little
`increase in the chip area. Further. even when half as many
`redundant column selection lines as contained in the semi- 45
`conductor memory device 100 are installed in the semicon(cid:173)
`ductor memory device 200. it is possible to relieve the same
`number of defective bit lines as is done by the semiconduc-
`tor memory device 100. Accordingly. it is possible to reduce
`the chip area without deteriorating the relief efficiency.
`In the semiconductor memory device 200. defective bit
`lines are flexibly replaced using the most significant bit of
`the X address. However. this invention is not limited to this
`choice. and a defective bit line may be replaced flexibly by
`using. for example. the highest order two bits of the X 55
`address. Moreover. a defective bit line may be replased to
`using the highest order three bits of the X address. When the
`replacement of a defective bit line is carried out using the
`highest order two bits of the X address. the relief efficiency
`of the defective bit lines will be quadrupled. and when the 60
`highest order three bits of the X address are used, the relief
`efficiency of the defective bit lines will be octupled.
`However. when the highest order two bits of the X address
`are used, the number of fuse blocks to be included in the
`column redundancy decoder 216' has to be made 4. and 65
`when the highest order three bits of the X address are used.
`the number of fuse blocks to be included in the column
`
`8
`redundancy decoder 216' has to be made equal to 8.
`Accordingly. the number of fuse blocks cannot be allowed
`to increase without limit when no margin is available for the
`space to arrange the fuse blocks, although it will cause no
`problem when there is a sufficient margin for such a space
`is available. Eventually. the decision as to the number of
`higher order bits to be used of the X address should be
`determined by the trade-off between the available margin for
`arranging the fuse blocks and the anticipated number of
`generated defective bit lines.
`As in the above. the area required by the peripheral circuit
`region is increased in response to the used bit numbers of the
`X address. In general. however. the peripheral circuit region
`has a larger space margin than the cell array region. so that
`15 there occurs little increase in the chip area when the most
`significant bit of the X address is used as in the semicon(cid:173)
`ductor memory device 200.
`Next. referring to FIG. 6, the semiconductor memory
`device 600 according to a second embodiment of this
`20 invention will be described.
`As shown in FIG. 6. in tlle semiconductor memory device
`600 according to tlle second embodiment of this invention.
`the cell array region is subdivided into two parts. and a
`column decoder 608 and a redundant column selection line
`driver 614 are arranged in the region sandwiched between
`the two cell array regions. Each of these cell array regions
`has its own redundant cell array region. Namely. the upper
`cell array region consists of a normal cell array region 602
`and a redundant cell array region 604, and the lower cell
`array region consists of a normal cell array region 636 and
`a redundant cell array region 638.
`Of these two cell array regions. a row decoder 606 and a
`row redundancy decoder 612 are installed corresponding to
`35 the upper cell array region. and a row decoder 640 and a row
`redundancy decoder 646 are installed corresponding to the
`lower cell array region. An address (X' address) excluding
`the most significant bit of the X address is supplied in
`common to these decoders on the X side XAO indicating the
`40 most significant bit of the X address is supplied to tlle row
`decoder 606 and the row redundancy decoder 612. and XA1
`indicating the most significant bit of the X address is
`supplied to the row decoder 640 and the row redundancy
`decoder ()46.
`The row decoder 606 is activated when XAO is "1" and
`activates, in response the X' address, one word line corre(cid:173)
`sponding to the X' address out of a plurality of word lines.
`In