—1 6 BIT TRANSFERS-
`
`«as = -Efilflfiififlfilfi
`I
`--
`
`I
`
`I
`
`NBGT
`INCMND
`DTREO
`DTGRT
`
`I
`I
`
`‘ u5—>I I<—-
`oIoI5ps_I..I
`I..:
`200 "5"“"
`;,”I:
`166 ns max.—>-ha:
`
`I
`I
`
`
`
`I
`
`I
`
`I
`I
`'37tu3.9 us max.
`l37IO39[.1S max.
`
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`I
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`0.5 ys_.| I._.,
`166 ns_.u.._
`165 ns —>IJ:U*
`*U,U|-k
`
`DTSTR
`
`I.I*
`
`- IF A DTGFIT IS OMITTED DTACK~MWTFl«MCS-DTSTR WILL NOT BE PFIEE=,‘~AT IF DTGFIT IS PROVIDED ON THE NEXT DATA TRANSFER
`1
`A TRANSFER WILL OCCUR —- HOWEVER — GER WILL FIEIJAIH HIGH ANC HS FAIL WILL BE ACTIVE
`2 - * =166 ns PULSE or INTERVAL.
`
`FIGURE 3. BUS-66108 RECEIVE COMMAND TIMING
`
`DESCRIPTION
`
`Dual Redundant
`a
`is
`BUS-65112,
`The
`MIL-STD-1553B Remote Terminal Unit.
`It
`contains
`two
`transceivers,
`two Harris
`I-{D-15530 Encoder/Decoders,
`two Terminal Bit
`Processors,
`two Interface Logic Blocks, one
`Protocol Logic Sequencer, CMOS Data Buffers
`and some miscellaneous logic,
`such as the
`address
`parity detector
`circuit,
`It
`requires
`two
`external Bus-25679 Mux Bus
`Transformers,
`one 12 megahertz TTL
`eloek
`input, plus 5 volts, plus or minus 15 volts
`DC
`to operate.
`The BUS-65112 Hybrid
`X
`measures
`2.100"
`1.870"
`X
`.250” ht.
`maximum,
`This 3,93
`square inch package
`makes use of
`78 pins in a Dual-In-Line
`plug-in
`package
`configuration.
`The
`Bi-Polar and majority of CMOS devices makes
`this
`a very
`low power Dual Redundant RTU.
`At
`idle,
`the
`superhybrid will
`require
`approximately
`4.2 warts,
`while
`at
`25
`percent duty
`cycle it will draw 5.2 watts
`total.
`All this
`additional power is not
`dissipated within
`the
`hybrid,
`but
`transferred to the
`1553 MUX
`BUS during
`message transfers.
`
`has a dedicated internal 16
`The BUS-65112
`bit parallel highway which is isolated from
`the external
`16 bit
`SSIU highway by a set
`of Bi-Directional CMOS Buffers.
`The Buffer
`Enable (PIN 67) Signal
`is br°U8ht
`°Ut 50
`3110W the SSIU to m0flit0r
`the highway at
`811 times Or simply when data transfers to
`the SSIU are being performed.
`The type of
`transfer is of a DMA nature in that the RTU
`requests a transfer, waits for a SSIU Grant
`and
`then does the
`traHSf€F-
`Figure
`3:
`Receive
`Command Timing
`and Figure 4.
`Transmit Command Timimg, give
`typical 16
`bit
`transfer details.
`Note
`that Data
`Strobes
`(DT
`STR)
`occur
`for
`each DMA
`transfer
`cycle
`and
`during
`BUS-65112
`internal
`Command Word
`and Status Word
`transfers
`between
`the
`AB‘
`and
`B’
`Monolithics.
`The STATEN signal designates
`which
`DT
`STR
`is transferring the Status
`W0Td Register
`C0Ut€ntS
`to the A'
`for
`transmission-
`The B’ Protocol converts the external 12Ml-lz
`clock to 6MHz.
`The 6MHz is used internally
`in order to generate and
`clock all
`SSIU
`interface control signals.
`
`565
`
`BOHNG
`
`Ex.1031,p.636
`
`BOEING
`Ex. 1031, p. 636
`
`

`
`— 16 BIT TRANSFERS ~
`
`!
`
`XMT COMMAND
`
`I
`
`|
`
`STATUS
`
`3 5 us mm, -3 7 /45 max.
`
`IIEEWEEEEIIIIIIIIIIP 1 Eli‘
`
`
`|
`
`DATA 1
`
`I
`
`DATA 2
`
`§TATEN
`
`(A5) CMDTRF
`
`5 L-5*"
`
`85 : 2I;.Is—>
`'
`
`CLEAHED 156 ns arson: STATEN
`moms‘ _ *=‘6e ns PJLSE or INTEWAL _.|
`2
`’A]
`'TFlA|L|NG EDGE OF DTACK WJCREMENTS "C-“IC"
`____ja§i§5q£g§s9g§JgFw 3TZEHOS”CWC'
`FLAG WILL 50 LOW IF A CMND GRAIJT TS MISSING
`3 - DTACr.-.‘-.1'NTF\-MCS-DTSTFL WILL REMAIN HIGH SEOULD DY GT7’-l NOT OCCUR THE
`DATA TRANSFERS ARE S7iLL POSSIBLE HOWE‘/EH —— IF A DATA WD GRANT IS MISSED THE F-(TU MILL TEF(Mlr.~‘~TE TR»‘~’lSFE'r'iS
`FIGURE 4. BUS-66108 TRANS!‘/HT COMMAND TIMING
`
`The Superhybrid generates a 12 bit address
`field which is used by the SSIU to read or
`write into memory.
`Bits A0 - A4 are equal
`to the word Count Field
`(WC) between the
`NBGT
`and
`INCMD period
`of
`a
`normal
`transmit/receive command.
`It is always the
`WC
`during
`the process of
`a Valid Mode
`Command when INCMD
`is valid A0 - A4 then
`becomes
`the Current Word Counter
`(CWC)
`field starting at zero.
`The trailing edge
`of DTACK increments the CWC by one.
`The A5
`bit is the Command Transfer Signal
`(CMDTRF)
`that
`tells
`the
`SSIU
`that
`the
`DTREQ
`represents the Valid Command Transfer.
`The
`A6 - A10 bits
`represent the Valid Command
`Words T/R bit.
`The A0 bit is the least
`significant bit (LSB) , while All is the MSB
`bit.
`The Address Field is latched for the
`entire transfer cycle with the exception of
`the
`CWC being
`incremented for
`each Data
`Word Transfer.
`
`ERROR FLAGS
`
`can be
`four Error Flags which
`are
`There
`SSIU to detect if anything is
`by the
`used
`the BUS-65112
`terminal.
`The
`wrong with
`first is the Message Error (ME) Flag, which
`
`a
`RT detects
`the
`as
`soon
`low as
`goes
`message error condition, Format Error, Word
`Count Error,
`Invalid Words, Sync Error, RT
`to RT Command Address Error or T/R Bit
`Error.
`The
`second is
`the RT-FAIL Flag
`indicating an internal RT failure.
`The RT
`FAIL
`signal
`indicates when
`the A’
`or B’
`Monolithic
`devices
`fail
`during an
`RT
`transmission via the BIT.
`The wrap Around
`Bit Test checks
`the last word transmitted
`for
`incorrect
`sync
`type Manchester
`II
`Error.
`The Watch Dog Time-Out also sets
`this RT
`FAIL Flag.
`The RT
`FAIL Flag is
`cleared the next
`time the
`RT initiates a
`new status word transmission.
`The third
`error
`flag condition is
`the Handshake
`Failure (HS
`FAIL) which
`indicates when an
`SSIU
`fails
`to give
`the
`required data
`transfer grant
`in (DTGRT)
`in time.
`If a
`command
`word grant
`is missing,
`data
`transfers are still possible, however,
`if a
`data word grant
`is missed,
`the
`RT will
`terminate
`transfers.
`The
`fourth type of
`output
`flag
`is
`the
`RT Address Error
`(RTADERR) which indicates a parity failure
`on the
`unique RT address inputs ADDRA thru
`ADDRP.
`If one of the hardwired RT address
`lines should open,
`the RT ADDERR would flag
`the problem to the SSIU.
`
`566
`
`BOHNG
`
`Ex.1031,p.637
`
`BOEING
`Ex. 1031, p. 637
`
`

`
`OUTPUT SIGNALS
`
`The BUS-65112 has a number of useful output
`signals to interrupt the SSIU such as:
`
`(1) NBGT - New Bus Grant - Low level output
`pulse used to
`indicate the start of a new
`protocol
`sequence
`in response
`to the
`Command Word just received.
`
`to
`- High Level Output used
`INCMND
`(2)
`SSIU that
`the RT
`is presently
`inform the
`servicing a command.
`
`(3) STATEN - Status Word Enable - Low level
`active output present when the Status Word
`is
`enabled
`onto
`the
`16 Bit Parallel
`Highway.
`
`(4) BITEN - Built-In-Test Word Enable - Low
`level
`used output present when
`the BIT
`Register contents
`is enabled
`onto the
`16
`Bit Parallel Highway.
`
`GBR - Good Block Received Word - Low
`(5)
`level pulse
`used to
`flag the
`SSIU that a
`Valid, Legal, Non-Mode Receive Command with
`the correct
`number of data words has been
`received without
`a message
`error
`and
`successfully transferred to the subsystem.
`
`SPECIAL OPERATING FEATURES - Inputs
`
`There are two inputs which provide the SSIU
`with special operating features.
`The first
`is the RESET signal. This active low input
`causes
`the BUS-65112
`to reset all logic,
`for power-up
`and initialization sequences.
`The
`second special signal is the Broadcast
`Enable
`(BROENA),
`when high
`allows
`RT
`recognition of all ones in the Command Word
`as a Broadcast Message per MIL-STD-1553B.
`When low,
`the RT will not respond to the RT
`Address
`31,
`unless
`it was the
`assigned
`terminal address.
`
`two input signals just
`In addition to the
`described,
`the BUS-65112 features 6 inputs
`which provide
`control of
`the bits
`in the
`Status Word.
`One of the most unique and
`useful
`inputs
`is
`the
`Illegal
`Command
`(ILLCMD) which
`allows
`the
`subsystem to
`illegalize any command or mode code.
`That
`means
`any subaddress or any of the 1553B
`Dual Redundant Mode Codes not
`implemented
`by the SSIU can be illegalized. This can be
`accomplished
`by
`placing
`a
`properly
`programed PROM across the latched command
`word outputs.
`when
`an
`illegal pattern
`presents
`itself,
`the
`PROM will output
`the
`illegal flag, which is
`read by
`the B' at
`the proper time.
`The ME BIT will be set
`and the
`RT will
`transmit the Status Word,
`but won't transfer any data to or from the
`SSIU.
`
`The second
`(SRQ),
`is the Subsystem Request
`which
`is an
`input
`from the SSIU used to
`control
`the
`service
`request bit in
`the
`status
`register.
`If
`low when the status
`word is updated,
`the bit will
`be set, if
`high, it will be cleared.
`The third is the
`Accept Dynamic Bus Control
`(ADBC).
`An
`active
`low input from the SSIU used to set
`the Dynamic Bus Control Acceptance Bit
`in
`the Status Register if the Command Word was
`a valid,
`legal mode command for dynamic bus
`control.The
`fourth is
`the Remote Terminal
`Flag (RT FLAG) used to control
`the terminal
`flag bit in the Status Register.
`If low
`when
`the
`Status Word
`is updated,
`the
`Terminal Flag Bit would be set, if high, it
`would be cleared.
`
`the Subsystem Busy
`is
`fifth signal
`The
`(BUSY)
`used to control the busy bit in the
`status register.
`If low when the status
`word
`is updated,
`the busy bit will be set,
`if high,
`it will be cleared.
`If the Busy
`Bit
`is set in the status register, no data
`will
`be
`requested from the subsystem in
`response
`to a transmit command, on receive
`commands data will still be transferred to
`the SSIU.
`The sixth and last signal is the
`control
`Subsystem Flag
`(SS FLAG)
`used to
`the
`subsystem flag bit
`in the
`status
`register.
`If
`low when the status word is
`updated,
`the SS FLAG will be set, if high,
`it will be cleared.
`
`TYPICAL MODES
`
`The BUS-65112 Superhybrid Protocol Logic,
`when preparing its response to a command,
`entertains basically four typical modes.
`The
`B’ protocol,
`in determining its proper
`course of action,
`looks
`at the
`type of
`command
`and the
`associated T/R Bit.
`The
`first case
`is when a Mode Code is received
`with a T/R = l,
`the B’ checks the WC4 Bit
`to see
`if its
`zero for no data.
`This is
`also performed for reserved Mode Codes.
`If
`the WC4 Bit
`is not zero,
`the RT transmits
`the Status Word only.
`The second case is
`when a
`command is received with a T/R = 0,
`the WC4 Bit
`= 0, and no data is received,
`the B’ automatically sets the ME bit of the
`status
`register and doesn't transmit
`the
`status word.
`The third case is when the
`WC4
`= l,
`the T/R Bit = 0, and one and only
`one data word
`is
`received,
`the
`RT will
`respond with a
`status word only.
`If no
`data or
`too many data words are received,
`the
`RT will set the ME Bit and not respond
`with a
`status word.
`The fourth or last
`consideration is when WC4 = l and T/R = l,
`but
`its not
`a Transmit Bit Word Mode
`Command or Transmit Last Command Word Mode
`Command
`the
`RT will
`transmit the Status
`Word
`and request
`one word
`from the SSIU,
`unless illegalized by the optional external
`PROM.
`
`567
`
`BOHNG
`
`Ex.1031,p.638
`
`BOEING
`Ex. 1031, p. 638
`
`

`
`set up using 14
`The Bit Word Register is
`bits to
`provide the Bus Controller with a
`full
`report of
`the RT's condition.
`when
`the RT
`receives the Transmit Bit Word Mode
`Command
`a Status Word followed by the Bit
`Word is
`transmitted.
`The Bit Word is as
`follows:
`
`SYNC FIELD
`LSB BIT 15 - NA
`BIT l4 - NA
`BIT 13 - CHANNEL B TIME OUT
`BIT 12 - CHANNEL A TIME OUT
`BIT ll - CHANNEL B BIT
`BIT 10 ~ CHANNEL A BIT
`BIT
`9 - XMTR B SHUTDOWN
`BIT
`8 - XMTR A SHUTDOWN
`BIT
`7 - BROADCAST RECEIVED
`BIT
`6 - WORD COUNT HIGH
`BIT
`5 - WORD COUNT LOW
`BIT
`4 -
`ILLEGAL MODE COMMAND
`BIT
`3 - T/R BIT OR MODE CODE ERROR
`BIT
`2 - BIT TEST FAILURE
`BIT
`l
`- HANDSHAKE FAILURE
`MSB BIT
`O - CHANNEL A OR B TIME OUT
`PARITY
`
`B Time Out
`A or
`13 Channel
`l2 &
`The BIT
`Flags indicate when either of the Watch Dog
`Timers
`have
`exceeded
`800 microseconds.
`The
`Built-In-Test
`(BIT),
`which
`is
`continuously being
`performed with each and
`every message
`transfer dynamically,
`is
`next.
`The BIT checks for correct sync, and
`that
`there
`is
`no Manchester
`coding or
`parity errors
`as well
`checking the
`last
`word wrap-around
`for
`each
`transmission.
`The transmitter (XMTR) Shutdown for Channel
`A or B represents when the Mode Command has
`been exercised.
`If a Broadcast Command was
`received, BIT 7 will be set.
`If a Command
`with more
`words
`or
`less words
`than
`specified in the WC field is encountered,
`BITS 6 & 5, respectively will be set in the
`BIT Word Register.
`If the optional illegal
`mode command
`PROM is
`used, BIT
`4 will be
`set when
`one
`is received.
`The BIT
`3,
`indicates when
`a Mode
`Command is received
`with an
`incorrect T/R setting.
`Bit 2,
`flags when
`a BIT
`fault has occurred on
`either
`channel.
`Bit
`1, Handshake Fail
`is
`Flag,
`set once
`a grant is not received
`on time.
`The last Bit 0 indicates when the
`l553 Watch Dog Time Out Circuit timed out
`on either Channel A or B.
`
`SUMARY
`
`above features, along with the
`All of the
`14 Bit Built-In-Test Register makes this
`BUS-65112 a very powerful
`The Superhybrids
`remote
`terminal unit.
`low price
`and
`small
`size,
`low power,
`ideal choice
`in
`flexibility make
`it
`an
`space
`limited military applications where
`full
`883B level screened parts that
`can
`operate
`from -55 degrees C to +125 degrees
`C case temperatures are needed.
`
`568
`
`BOHNG
`
`Ex.1031,p.639
`
`BOEING
`Ex. 1031, p. 639
`
`

`
`VLSI CHIP SET FOR HIGH-PERFORMANCE AVIONIC COMPUTERS
`
`84-2730
`
`Stephen J. Forde* and Mark A. Hilmante|*
`
`Sanders Associates,
`Computer Engineering Department
`Nashua, New Hampshire
`
`Inc.
`
`ABSTRACT
`
`Advanced CMOS processing with line widths of
`two micrometers makes
`possible
`a
`VLSI
`implementation of avionics computers.
`Using
`a
`chip set designed with 6000-gate gate
`arrays
`has
`allowed the design of
`a very
`high—performance.
`yet
`small,
`low—power,
`cost—effective,
`and highly flexible avionics
`computer.
`
`the
`chips:
`four
`comprises
`chip set
`The
`(USEO),
`the arithmetic and
`microsequencer
`logic unit
`(ALU),
`the operand generator unit
`(OGU),
`and the memory controller unit
`(MCU).
`The four chips can be configured to implement
`the Air
`Force
`standard
`instruction
`set
`architecture (MlL—STD—1750A, Notice
`1)
`and
`emulate
`the
`Navy
`standard
`computers
`(AN/UYK—20, AN/AYK-14,
`and AN/UYK—44).
`An
`overview of
`the
`chip
`architectures
`is
`presented in this paper.
`
`INTRODUCTION
`
`Today's avionics computers must combine high
`processing
`throughput
`with
`low
`power
`consumption and small
`size,
`and yet
`remain
`cost—effective and flexible.
`Meeting such
`requirements is no easy task, as evidenced by
`many
`systems
`in
`the
`field today.
`Some
`systems.
`using emitter—coupled
`logic.
`have
`gained performance at
`the expense of power;
`some are too large for airborne requirements;
`while others have been so optimized for a
`specific task that
`they cannot be used for
`any other purpose.
`Even those systems which
`meet
`the
`power,
`size,
`and
`flexibility
`criteria never
`seem to have the performance
`needed for many real—time applications.
`
`from
`evolved
`have
`computers
`avionic
`Many
`architectures which were designed to make the
`best of
`low—performance core memories
`[1].
`Replacing
`the
`core memories with
`faster
`semiconductor memories has allowed for
`some
`increase in the performance of such machines.
`
`* Member
`
`IEEE
`
`This work was supported in part by
`the Naval Research Laboratory under
`Contract NOOOI4-84-C—2250.
`
`C°PYrighl © American Institute of Aeronautics and
`Astronautics, lnc., I984. All rights reserved.
`
`569
`
`these machines are limited by the
`However,
`underlying architectures.
`unable
`to take
`full
`advantage of
`the performance
`increases
`possible with
`newer
`technologies.
`The
`problem becomes apparent:
`how to combine
`technology with
`suitable architectures
`to
`produce a machine which meets
`the desired
`performance.
`power.
`size,
`cost,
`and
`flexibility objectives.
`The solution should
`be obvious:
`new technologies
`require
`new
`architectures.
`The remainder of
`this paper
`discusses a VLSI
`chip set which implements
`this solution.
`
`THE CHIP SE!
`
`the
`chips:
`four
`comprises
`chip set
`The
`(USEQ),
`the arithmetic and
`microsequencer
`logic unit
`(ALU),
`the operand generator unit
`(OGU),
`and the memory controller unit
`(MCUL
`The
`four
`chips
`can
`be
`configured
`(with
`appropriate support chips)
`to implement
`the
`Air
`Force
`standard
`instruction
`set
`architecture (ISA), MlL—STD—l75OA (Notice 1).
`These same chips can also be used to emulate
`the
`Navy
`standard
`l6—bit
`computers:
`AN/UYK—20, AN/AYK—14, and AN/UYK—44.
`
`shows a typical configuration for
`Figure 1
`these chips.
`including memory
`and support
`functions.
`The USEO.
`ALU,
`and OGU chips
`compose the heart of the central processing
`subsystem (CPU).
`The memory
`subsystem
`requires at
`least
`two
`independent memory
`banks. each with its own MCU.
`
`implemented with
`been
`has
`chip set
`The
`2—micrometer CMOS processing.
`Each chip has
`the
`equivalent
`complexity of
`a
`6000—gate
`device.
`The
`chip set was designed
`for
`execution
`of
`the
`DAIS
`floating—point
`instruction mix at
`two million instructions
`per
`second
`(MIPS)
`and execution of
`fixed
`point
`instructions
`at
`4 MIPS.
`This
`performance has been achieved by employing a
`six—level
`pipelined
`CPU,
`and
`a memory
`subsystem with multiple
`independent
`banks
`which
`allows
`simultaneous
`instruction and
`operand accesses.
`Power dissipation is ll
`watts per chip (typical).
`
`BOEING
`
`Ex. 1031, p. 640
`
`BOEING
`Ex. 1031, p. 640
`
`

`
`
`
`
`
`INSTRUCTION B'JS
`
`ADDRESS BUS— SYSTEH
`
`
`mm It
`
`CDNSULE
`
`|r1lCRE‘INSTRUtTION aus
`
`CONTROL
`STORE
`
`
`
`Figure 1.
`
`SYSTEM USING VLSl CHIP SET
`
`The Microseguencer Chip
`
`The USED chip (Figure 2) decodes instructions
`from the
`instruction pipeline and controls
`microinstruction
`sequencing.
`The
`chip
`contains
`five
`functional
`units:
`the
`instruction queue,
`the microaddress generator
`unit
`(MGU).
`interrupt processing logic (IPL).
`the control unit. and the microbranch detect
`unit
`(MDU).
`
`instruction
`The
`instructions
`for
`execution.
`sing|e—word
`instructions.
`
`queue
`decoding
`The
`queue
`instructions or
`
`machine
`buffers
`subsequent
`and
`holds
`four
`two double-word
`
`the next
`the microaddress of
`The MGU forms
`The
`microinstruction
`to
`be
`executed.
`microaddress is derived from the microprogram
`counter.
`the microaddress
`stack.
`the
`microliteral
`(from
`the
`current
`
`decoded
`from the
`microinstruction),
`The microaddress
`is
`machine
`instruction.
`used to access the off—chip control store.
`
`Ol’
`
`surveillance of various
`IPL maintains
`The
`internal
`and external
`fault
`flags.
`forcing
`interrupt processing to occur as necessary.
`The
`IPL receives data (e.g.
`interrupt masks)
`via the system data bus.
`Also included in
`this unit are timers which can be used as
`watchdog timers or
`real-time clocks.
`These
`timers are also loaded via the system data
`bus.
`
`The control unit receives microinstructions
`from the
`control
`store
`and
`uses
`these
`primarily for controlling the formation of
`the
`next microaddress.
`This unit
`also
`receives
`the microliteral
`field
`of
`the
`microinstruction. which
`is used
`in forming
`the next microaddress.
`
`internal
`The MDU maintains surveillance of
`status
`flags and detects conditions which
`require microbranching.
`Control signals are
`provided from the ALU chip for branching.
`These controls
`insure that
`the
`instruction
`queue contains the proper sequence of machine
`instructions.
`
`
`
`QDDPESS
`
`min
`INCR
`
`A
`
`'5
`
`IPL
`
`TIHERS
`
`HICRORCDRESS BUS
`
`UR
`
`j
`
`st A1 us
`
`nou j
`
`j
`
`Figure 2.
`
`MlCROSEQUENCER BLOCK DIAGRAM
`
`The Arithmetic and Logic Unit Chip
`
`a 32-bit
`uses
`3)
`(Figure
`chip
`ALU
`The
`perform both
`to
`architecture
`internal
`and
`floating—point operations.
`fixed—point
`The chip has four functional units:
`the ALU.
`the program status unit.
`the control unit.
`and an external
`interface.
`
`the chip comprises a set
`The ALU portion of
`of pipeline registers
`and an
`accumulator.
`They
`are
`configured
`as pairs
`of
`16-bit
`-registers.
`each 16-bit
`register
`is provided
`with individual controls so that both single-
`and double—precision operands can be handled
`efficiently.
`The
`ALU.
`shifter.
`and
`floating—point unit
`(FPU) are each 32—bits
`wide.
`These units
`are
`connected
`to an
`internal 32-bit bus. Results of operations
`are placed on this bus, where they may either
`be sent out on the system bus or used as
`operands during subsequent operations.
`
`570
`
`BOEING
`
`Ex. 1031, p. 641
`
`BOEING
`Ex. 1031, p. 641
`
`

`
`The controls for the instruction pipeline (on
`both the UGU and the USEQ chips) originate
`from the lPU.
`The
`lPU uses
`information in
`each microinstruction,
`as well
`as signals
`from the microbranch detect unit and program
`status unit on the USEO and ALU chips,
`to
`keep the pipeline filled.
`
`the UGU consists of
`file on
`register
`The
`sixteen 16-bit registers. addressed by a read
`address and a write address.
`it allows'two
`read operations and one write operation per
`machine cycle.
`Data read from the register
`file can be used as data by the ALU and/or
`used to compute a logical memory address by
`the address generator.
`
`The address generator unit's primary function
`is to calculate logical
`addresses.
`This
`unit
`allows memory—indexed operations
`to
`execute
`in a single machine cycle,
`saving
`time and control store space.
`The AGU is
`also used to
`adjust operands before being
`piped to the ALU.
`
`in addition to
`The control unit on the OGU.
`decoding
`microinstructions.
`controls
`pipeline
`data
`bypass
`logic.
`Bypass
`operations allow the CPU to proceed, without
`waiting,
`when
`one
`instruction
`execution
`requires the result value of the immediately
`
`the bypass
`preceding instruction. Without
`logic execution would be delayed while the
`needed operand flows
`through the pipeline.
`
`
`
`REGISTER
`
`INTRUCTION
`OUEUE
`
`
`
`CONTROL
`LOGIC
`
`
`
`liliiiiilil
`
`Figure 4.
`
`UGU BLOCK DlAGRAM
`
`571
`
`BOEING
`
`Ex. 1031 , p. 642
`
`system
`other
`interfaces with
`chip
`The
`three
`elements via three 16-bit buses.
`All
`Two
`are tri—state;
`two are bidirectional.
`The
`buses supply data operands to the ALU.
`the
`results of ALU operations are sent over
`system data
`bus
`(18
`bits
`at
`a
`time.
`controlled by
`the external
`interface),
`or
`additionally,
`over
`the bidirectional
`data
`operand bus. This capability is particularly
`useful
`for double—precision operations which
`require one of the words of the result to be
`reused (e g. double—precision multiply).
`
`The program status unit maintains the machine
`state.
`using
`status
`flags
`(e.g.
`carry.
`overflow.etc )
`from the ALU,
`shifter.
`and
`FPU,
`as well as data on the internal data
`bus.
`
`The chip receives encoded instructions from
`the control store.
`These
`instructions are
`decoded by the control unit and routed to the
`appropriate circuits on the chip.
`
`
`
`
`
`PSU
`
`n2¥3’EUs
`
`Figure 3.
`
`ALU BLOCK DIAGRAM
`
`The U erand Generator Unit Chi
`
`
`tasked with
`is
`4)
`(Figure
`chip
`OGU
`The
`providing the data operands to the ALU chip.
`These operands come from the register file or
`from memory.
`in the latter case,
`the UGU
`provides
`the data memory
`address
`to the
`memory controller chip.
`
`into five functional
`is divided
`chip
`The
`the
`instruction
`queue,
`the
`units:
`Instruction prefetch unit
`(IPU).
`the register
`file,
`the address generator unit
`(AGU),
`and
`the control unit.
`
`instruction queue is an exact copy of the
`The
`instruction queue on the microsequencer chip.
`The
`instructions are buffered on the UGU to
`provide the register addresses
`for machine
`Instructions.
`
`BOEING
`Ex. 1031, p. 642
`
`

`
`FE'CH bk:-«NEH
`
`PROGRAM
`COUNTER
`
`F—.~DE BIJLJ .L‘mRr
`
`CONTENTION
`
`
`
`QDDPESS
`
`TRQNS.RT'N
`CRH
`
`
`REQD/HPITE
`
`Figure 5.
`
`MEMORY CONTROLLER CHIP
`BLOCK DIAGRAM
`
`SUMMARY
`
`Today's avionic computers must combine high
`processing
`throughput
`with
`low
`power
`consumption and small
`size,
`and yet
`remain
`cost—effective
`and
`flexible.
`New
`architectures implemented with advanced CMOS
`gate. arrays
`have
`resulted
`in
`a
`highly
`flexible VLSI chip set, capable of executing
`the DAIS
`floating—point
`instruction mix at
`VHSIC speeds.
`The floating—point execution
`rate of 2 MIPS and fixed-point
`instruction
`rate of 4 MIPS, surpasses the performance of
`other machines of equal size and power by as
`much as 50-1002.
`These chips
`implement
`the
`MIL-STD—l75OA
`(Notice
`1)
`16-bit
`ISA
`and
`emulate
`the
`AN/AYK—I4,
`AN/UYK—20,
`and
`AN/UYK—44 standard computers.
`
`REFERENCES
`
`"High Performance Avionic
`J. Garbos,
`[I] R.
`GOVERNMENT
`MICROCIRCUIT
`Architectures“,
`APPLICATIONS CONFERENCE
`(GOMAC)
`I984 DIGEST
`OF PAPERS
`VOL. 9, November 1984.
`
`572
`
`BOHNG
`
`Ex.1031,p.643
`
`The Memory Controller Unit Chip
`
`The MCU gate array (Figure 5) controls a
`single bank of up to 128K words of memory.
`It
`provides
`the
`following
`capabilities:
`dual—port control with contention resolution;
`multi—mode
`logicaI—to-physical
`address
`translation;
`read/write/execute protection;
`and a program counter
`for
`instruction port
`accesses.
`
`transfers information
`The Memory Controller
`to and from the rest of the computer via the
`address
`bus.
`This
`information
`includes
`logical
`addresses,
`physical
`addresses.
`protection flags, and fault codes.
`
`Memory data does not pass through the Memory
`Controller gate array, but
`instead is gated
`to/from the
`instruction or
`data
`bus
`by
`signals
`generated in the memory controller;
`this reduces the number of pins required
`on
`the gate array.
`
`two
`is able to accept
`The Memory Controller
`for
`requests,
`one
`simultaneous
`memory
`data.
`for
`operand
`instructions
`and
`one
`Instruction addresses come
`from the on—chip
`program counter
`(except
`in
`the
`case
`of
`program branches)
`in order
`to reduce the
`number of wires connecting the memory with
`the CPU. Operand addresses come from the OGU
`chip via the address bus.
`In most cases,
`the
`two requests are handled simultaneously by
`memory
`controllers
`in
`separate
`banks.
`Occasionally. both requests must be serviced
`in
`the
`same
`bank;
`the memory controller
`contention resolution logic then sequences
`the operations on the memory array.
`
`allows
`(CAM)
`content-addressable memory
`A
`Iogica|—to—physical
`address translation and
`protection operations to occur simultaneously
`with address decoding,
`increasing throughput
`when
`translation
`is
`required.
`When
`an
`any
`address
`is
`not
`found
`in
`memory
`controller's CAM.
`the CAM is updated by the
`CPU.
`
`BOEING
`Ex. 1031, p. 643
`
`

`
`SESSION 22
`
`AIRBORNE
`
`SEPARATION
`
`ASSURANCE
`
`Chairman:
`
`Frank Chandler
`
`Sperry Dalmo Victor, Inc.
`
`Joseph J. Fee
`Federal Aviation Administration
`
`This session provides an understanding of the plans, designs, experiences and problems concerning
`
`current and future collision avoidance systems and select mode transponders.
`
`BOEING
`
`Ex. 1031 , p. 644
`
`BOEING
`Ex. 1031, p. 644
`
`

`
`BOEING
`
`Ex. 1031, p. 645
`
`BOEING
`Ex. 1031, p. 645
`
`

`
`EVOLUTION OF‘TEE COLLISION AVOIDANCE SYSTEM
`IN TH CDCKPIT
`
`William L. Hyland
`
`Federal Aviation Administration
`Washington, D.C.
`
`Abstract
`
`collision Avoidance Systems have been in various
`stages of development for a number of years.
`The
`aviation community is now on the verge of adopting
`the Traffic Alert and Collision Avoidance
`The
`System (TCAS)
`for operational implementation.
`majority of efforts over these development years
`have been devoted to the engineering aspects of
`the systems. As the system's concepts matured,
`the emphasis on the pilot use of the system has
`increased, with the attendant impact on system
`design of these evolutions. This paper treats the
`cockpit side of the systems evaluation, and the
`evolution of operational concepts over these
`years.
`
`Introduction
`
`The development of methodologies and systems for
`reducing the potential of aircraft midair
`collisions has been underway since the second
`airplane took off. Much effort has been expended
`by engineers and pilots to improve the
`capabilities of pilots to visually acquire and
`avoid potentially threatening aircraft. "Many
`years of experience have produced the present
`"rules of the road", and pilot procedures for
`"seeing-and—avoiding" other aircraft. Special
`aircraft paint and visual alerting devices, such
`as navigation lights, beacons and strobe lights
`have improved those capabilities.
`The air traffic
`control radar has improved the system for IFR and
`controlled aircraft.
`
`In recent years, more active collision avoidance
`systems have been proposed and evaluated to
`the
`further improve these capabilities.
`In 1966,
`airline community proposed an airborne system for
`air carrier use based on dedicated equipments for
`all users, operating at 1600 -1615 MHz.
`(1).
`This system became known as the Airborne Collision
`Avoidance System (ACAS).
`The FAA began
`development testing of a ground based collision
`avoidance system in 1974, designed to operate in
`the existing air traffic control radar beacon band
`at 1030-1090 Mz. This system, known as
`Intermittant Positive Control
`(IPC)
`(2) was
`intended for the general aviation community.
`
`the FAA began development of an airborne
`In 1975,
`beacon—based system, known as BCAS. As the
`benefits of the beacon-based solution became more
`evident,
`the FAA in 1976 (3) proposed a
`combination of airborne and ground systems to
`In
`improve "Airborne Separation Assurance" (ASA).
`1981,
`the FAA eliminated the ground—based portion
`of ASA and the Traffic Alert and Collision
`Avoidance System (TCAS) became the final system of
`choice.
`
`Through the above progression of systems,
`evaluation of use of the devices in the cockpit
`has progressed from none to comprehensive. As
`Pilots began to be more involved in the systems,
`This paper is declared a work of the U.S.
`Government and therefore is in the public domain.
`
`573
`
`84-2734
`
`changes in performance of the systems were
`introduced. Although little change in the basic
`concepts of the radio frequency (r.f.) portions of
`the system occured,
`the requirements for warning
`times needed by the pilot and the impact of rates
`at which alerts were experienced had considerable
`influence on the overall system design.
`
`Earlier Systems
`
`The ACAS envisioned by the airlines was basically
`an alerting system developed to deliver collision
`avoidance "commands" to the pilot.
`For display of
`this information,
`the system integrated the
`collision avoidance commands with an existing
`Instantaneous Vertical Speed Indicator (IVSI)
`instrument. The threat algorithm developed
`provided alerts with a 40—second and 25-second
`"time-to—co1lision" (TAU) and altitude separation
`of up to 3400 feet.
`The threat criteria produced
`the following commands:
`
`Limit descend to 2000'
`
`Limit climb to 2000'
`
`Limit descend to 1000'
`
`Limit climb to 1000'
`
`Limit descend to 500'
`
`Limit climb to 500'
`
`Don't descend
`
`Don't climb
`
`Climb
`
`Descend
`
`The integrated display (figure 1) provided a red
`climb or descend arrow, with segmented amber
`lights around the ring for limit rates. Because
`of the perceived need to control the environment
`when "commanding" a pilot to maneuver vertically,
`the display further instructed the pilot to "Don't
`Turn"! Pilot organizations found these proposed
`methodologies acceptable. However,
`there remained
`some concerns for the impact on the ATC system,
`and for possible false alarms.
`
`
`
`Figure 1
`
`While no actual pilot evaluations in operational
`environments were conducted, an ATC simulation was
`conducted to assess the CAS impact on the
`operating environment (4).
`It was found that the
`rate of cockpit alerts in the dense terminals
`would be excessively high because of the large
`protection volume, and that the phase of flight
`and location in the pattern at which the high
`number of alerts would occur would unnecessarily
`disrupt the ATC system.
`Commands were being
`generated with the "don't turn" instruction, which
`when delivered in the approach phase confused the
`overall air traffic control situation.
`
`IPC (later known as
`The ground-based system,
`Automatic Traffic Advisory and Resolution System,
`ATARS), originated from a background of general
`
`BOHNG
`
`Ex.1031,p.646
`
`BOEING
`Ex. 1031, p. 646
`
`

`
`aviation proximity warning systems, and had
`developed into a more complex system with maneuver
`commands.
`It was intended for delivering
`horizontal as well as vertical maneuver commands.
`The display developed for panel mounting
`(figure 2) provided the following:
`
`Turn Right/Don't Turn Right
`Climb/Don't Climb
`Descend/Don't Descend Turn Left/Don't Turn Left
`
`It did not use the IVSI or "limit rate" commands.
`The display also provided course bearing
`information on intruder traffic,
`in clock position
`lights, and altitude information at these clock
`positions displayed as "above", "coaltitude" or
`"below".
`
`
`
`Figure 2
`
`Some actual experience was gained in flying the
`IPC (5), although at this point the concept
`emphasized the general aviation environment and
`relied on VFR conditions and visual acquisition in
`most cases.
`A concept of priorities of alerts was
`conceived to first alert a pilot to a threat, and
`finally to maneuver.
`It used a decreasing time to
`collision (TAU)
`threat volume to generate these
`alerts. Many of the conclusions reached in these
`tests were as a result of the visual acquisition
`of the target aircraft. At this point the traffic
`advisory feature in VFR environments gained
`support.
`
`BCAS and IPC
`
`When the decision was made by the FAA to support a
`beacon-based collision avoidance system mainly
`‘because of the large number of operating
`transponder equiped aircraft,
`the operational
`concepts of ACAS and IPC were integrated.
`A lower
`cost active BCAS (i.e., actively interrogating
`other aircraft) would operate when out of ground
`radar coverage, providing vertical-only commands.
`A passive BCAS (i.e., listening to replies in
`response to ground interrogation) would operate
`within radar coverage and provide horizontal
`commands as well as range, bearing and altitude
`information.
`The IPC, which relied on use of the
`ground—based beacon system to derive collision
`avoidance data and transmit information, would
`individually tailor the threat volumes in terminal
`environments to reduce alert rates in the denser
`terminal are