IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Conley:
`
`Petition for Inter Partes Review
`
`U.S. Patent No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND
`READING OPERATIONS IN A
`NON-VOLATILE MEMORY
`
`Attorney Docket No.:
`337722-000080.490
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`
`Real Party in Interest: Apple Inc.
`
`
`
`DECLARATION OF DR. VIVEK SUBRAMANIAN
`
`APPLE INC.
`EXHIBIT 1203 - PAGE 0001
`
`
`
`In re patent of Conley:
`
`Petition for Inter Partes Review
`
`U.S. Patent No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND
`READING OPERATIONS IN A
`NON-VOLATILE MEMORY
`
`Attorney Docket No.:
`337722-000080.490
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`
`Real Party in Interest: Apple Inc.
`
`
`
`DECLARATION OF DR. VIVEK SUBRAMANIAN
`
`APPLE INC.
`EXHIBIT 1203 - PAGE 0001
`
`
`
`TABLE OF CONTENTS
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`
`Page
`
`INTRODUCTION .......................................................................................... 1
`RELEVANT BACKGROUND AND EXPERIENCE ................................... 2
`LEVEL OF ORDINARY SKILL IN THE ART ............................................ 3
`RELEVANT TECHNOLOGY BACKGROUND ......................................... 3
`CLAIM CONSTRUCTION ........................................................................... 7
`INVALIDITY OF CLAIMS 34-38, 40-64 AND 73-92 OF THE ’490
`PATENT ......................................................................................................... 7
`
`
`A.
`B.
`C.
`D.
`E.
`F.
`
`
`
`
`
`i
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0002
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`
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`Exhibit Number Description
`
`EXHIBITS
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`
`
`1201
`
`1202
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`1204
`
`1205
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`1206
`
`1208
`
`U.S. Patent 7,818,490 to Conley
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`File History for U.S. Patent 7,818,490
`
`CV for Dr. Vivek Subramanian
`
`U.S. Patent No. 5,822,781 to Wells (“Wells”)
`
`U.S. Patent No. 5,457,658 to Niijima (“Niijima”)
`
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`
`1209
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC
`
`1210
`
`1211
`
`Card Standard”)
`
`PCT WO 99/35650 (“Hazen”)
`
`Designing With Flash Memory, Brian Dipert and
`
`Markus Levy (1994) (“Dipert”)
`
`
`
`ii
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`
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0003
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`
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`A.
`
`Introduction
`
`1.
`
`2.
`
`I, Vivek Subramanian, declare as follows:
`
`I am making this Declaration at the request of Petitioner Apple Inc.
`
`regarding its Petitions for Inter Partes Review of U.S. Patent No. 7,818,490 (the
`
`“’490 patent”).
`
`3.
`
`I am being compensated for my work at my standard rate of $550 per
`
`hour. My compensation does not depend on the outcome of this proceeding.
`
`4.
`
`As part of my analysis, I reviewed the following materials:
`
`Exhibit 1201 U.S. Patent 7,818,490 to Conley
`
`Exhibit 1202
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`File History for U.S. Patent 6,818,490
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`Exhibit 1205 U.S. Patent No. 5,822,781 to Wells (“Wells”)
`
`Exhibit 1206 U.S. Patent No. 5,457,658 to Niijima (“Niijima”)
`
`Exhibit 1208
`
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`
`Exhibit 1209
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC
`
`Card Standard”)
`
`Exhibit 1210
`
`PCT WO 99/35650 (“Hazen”)
`
`Exhibit 1211 Designing With Flash Memory, Brian Dipert and
`
`Markus Levy (1994) (“Dipert”)
`
`
`
`1
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0004
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`B. Relevant Background and Experience
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`5. My background and experience is summarized in my curriculum
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`vitae, a true and correct copy of which is submitted as Exhibit 1204. Some of the
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`relevant points are described below as well.
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`6.
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`I received a B.S. in electrical engineering from Louisiana State
`
`University in 1994, an M.S. in electrical engineering from Stanford University in
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`1996, and a Ph.D. in electrical engineering from Stanford University in 1998.
`
`7.
`
`In 1998, I co-founded Matrix Semiconductor, Inc. to develop high
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`density memory technology.
`
`8.
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`I have been teaching in the Electrical Engineering and Computer
`
`Sciences Department at the University of California, Berkeley since 2000. I was
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`an Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to
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`2011, and a Professor from 2011 to the present.
`
`9.
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`I have been an adjunct professor at the Sunchon National University
`
`in Sunchon, Korea since 2009, leading research in printed electronics.
`
`10.
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`I have been an independent consultant in the semiconductor industry
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`since 2000, focusing on memory technology, flexible electronics, and RFID
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`technology.
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`11.
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`I have published more than 200 technical papers in journals and at
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`conferences.
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`
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`2
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0005
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`12.
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`I am a named inventor on over 30 U.S. Patents, many of which are in
`
`the field of memory design.
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`C. Level of Ordinary Skill in the Art
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`13.
`
`I am familiar with the knowledge and capabilities of a person of
`
`ordinary skill in art for memory devices in the 2001-2005 timeframe. Specifically,
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`my experience in the industry and with engineers practicing in the industry allowed
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`me to become personally familiar with the level of skill of individuals and the
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`general state of the art.
`
`14.
`
`In my opinion, a person of ordinary skill in the relevant art at the time
`
`of the ’490 patent would have earned the degree of Master of Science or equivalent
`
`in electrical engineering or a related field and two years of experience in memory
`
`technology or the equivalent.
`
`D. Relevant Technology Background
`
`15. A person of ordinary skill in the art as of the priority date of the ’490
`
`patent would have understood a flash memory device to consist of one or more
`
`arrays of non-volatile memory cells, and that each of the memory cells is a charge
`
`storage element. Non-volatile memory cells retain their data when power is
`
`removed. Some types of non-volatile memories, such as a read-only memory
`
`(“ROM”), contain cells whose data, once programmed, cannot be modified. The
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`cells in a flash memory, however, can be erased and then reprogrammed with new
`
`
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`3
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0006
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`information. While the typical flash memory architecture enables a device whose
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`cells are both non-volatile and reprogrammable, flash memories also suffer from
`
`several functional limitations. For example, once a flash memory cell is
`
`programmed with data, the cell must be erased before that cell can be
`
`reprogrammed with new data. The circuitry required to erase flash memory cells
`
`would be prohibitively large and time consuming to operate on flash memory cells
`
`individually. Therefore, instead of erasing individual cells, the typical flash
`
`memory has large groups of cells arranged into erasable blocks, a block containing
`
`the smallest number of cells that can be erased at one time. The ’490 patent
`
`specification confirms this. Ex. 1201 at 1:34-50. While substantial circuit
`
`overhead and time can be saved by erasing flash memory cells in large blocks, it is
`
`more convenient to read data from a flash memory and write data to a flash
`
`memory in units smaller than the size of a block. Therefore, blocks in a flash
`
`memory device are further partitioned into pages, a page containing the smallest
`
`number of cells that can be read from or written to at once. The ’490 patent
`
`specification confirms this. Ex. 1201 at 1:51-58. Finally, in some flash memories,
`
`typically due to memory management constraints, the pages within each block can
`
`only be programmed in a physically sequential manner. The ’490 patent also
`
`confirms this. Ex. 1201 at 7:1-4.
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`4
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0007
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`U.S. Patent No. 7,818,490
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`16. A person of ordinary skill in the art would have understood that prior
`
`to the’490 patent, it was known to store information related to the user data in the
`
`same page in which the data is stored. It was known to store such information in
`
`overhead data fields and flags. The ’490 patent confirms this. Ex. 1201 at 1:41-
`
`43, 5:53-55. Specifically, the ’490 patent explains that in the prior art, pages
`
`within a block can store a logical block number (“LBN”) indicating the logical
`
`address associated with the data. Ex. 1201 at 1:59-65, 5:41-55, 6:15-19, 6:42-43.
`
`Such overhead data fields and flags are illustrated in Figure 6 of the ’490 patent,
`
`below, which illustrates the prior art.
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`
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`5
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0008
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`U.S. Patent No. 7,818,490
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`17.
`
`In a flash memory, in order to reprogram even a page of data that has
`
`been previously programmed, the entire block in which the page exists must first
`
`be erased. Ideally, data in all pages within the block are updated together,
`
`maximizing efficiency. However, in operation, it is more common that only some
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`pages within a block are updated at one time, while the data in the remaining pages
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`does not change. This more common case was known at the time of the ’490
`
`patents as a partial block update. This is confirmed by the ’490 patent. Ex. 1201
`
`at 2:4-18.
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`18. At least two techniques to perform a partial block update were known
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`at the time of the ’490 patent. This is confirmed by the ’490 patent. Ex. 1201 at
`
`2:4-28. The first technique involves writing both unchanged pages of data from an
`
`original block and the changed pages of data to the pages of an unallocated block,
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`then erasing and de-allocating the original block. This technique is inefficient
`
`because it requires copying unchanged pages of data, a potentially substantial
`
`amount of data, to a new block. The second technique also involves writing the
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`changed pages of data to unallocated pages of a different block. However, instead
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`of copying the unchanged pages to the different block, the flags of the pages in the
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`original block which are being updated are modified to indicate that those pages
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`contain superseded data. The second technique requires flags in pages of the
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`
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`6
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0009
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`U.S. Patent No. 7,818,490
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`original block to be updated after they are already programmed, which is not
`
`possible in all flash memory architectures.
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`E. Claim Construction
`
`“metablock” (claims 42, 58, 87 and 88)
`
`19.
`
`I understand that Petitioner contends this term means “set of blocks
`
`associated together such that during operation they are programmed, read, or
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`erased together as a unit.”
`
`20.
`
`I understand that the Patent Owner contends this phrase means “two
`
`or more blocks positioned in separate units of one or more memory chips for
`
`programming and reading together in parallel as part of a single operation.”
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`21. Based on my understanding of the two proposed constructions, the
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`differences between them has no impact on validity analysis that I have performed
`
`in this declaration, and all of my conclusions remain the same under either
`
`construction.
`
`F.
`
`Invalidity of Claims 34-38, 40-64 and 73-92 of the ’490 Patent
`
`22. The ’490 patent explains that “a block contains the smallest number
`
`of cells (units of erase) that are erasable at one time.” Ex. 1201 at 1:38-40. This is
`
`consistent with the plain and ordinary meaning of the term “block” as a person of
`
`ordinary skill in the art would have understood it at the time of the ’490 patent.
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`Likewise, Niijima explains that a “cluster consists of one or more blocks each of
`
`
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`7
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0010
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`which is a physical erasure unit.” Ex. 1206 at 5:43-45. Niijima therefore discloses
`
`a cluster that is a physical erasure unit (i.e., a “block” in the context of the ’490
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`patent) because Niijima discloses that a cluster may consist of a single block that is
`
`a physical erasure unit. Consequently, a person of ordinary skill in the art would
`
`have understood that Niijima’s disclosures of “blocks” and single-block “clusters”
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`both anticipate the “blocks” recited in the claims of the ’490 patent. Additionally,
`
`the number of memory cells in a block may vary widely from one type of flash
`
`memory device to another. The ’490 patent itself describes blocks of various sizes.
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`Ex. 1201 at 1:41-58. Therefore, in addition to single-block clusters, it would have
`
`been obvious to one of ordinary skill in the art to substitute multi-block clusters for
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`the “blocks” recited in the claims of the ’490 patent because the cells in a multi-
`
`block cluster could be substituted for the unit of erasure to obtain predicable
`
`results.
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`23. The ’490 patent discloses:
`
`“[P]ages are [] the basic unit for reading and programming user data
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`(unit of programming and/or reading). Each page usually stores one
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`sector of user data, but a page may store a partial sector or multiple
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`sectors. A ‘sector’ is used herein to refer to the an amount of user data
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`that is transferred to and from the host as a unit.”
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`(Ex. 1201 at 1:52-58). This is consistent with the plain and ordinary meaning of
`
`the terms “sector” and “page” as a person of ordinary skill in the art would have
`
`
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`8
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0011
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`understood the terms at the time of the ’490 patent. Likewise, Niijima discloses
`
`that a sector “is the minimum access unit of the CPU 10 to the SSF 20.” (Ex. 1206
`
`at 5:35-38). Niijima further discloses an embodiment in which “two pages
`
`constitute one sector.” (Id. at 5:40). Therefore, one of ordinary skill in the art
`
`would have understood that the ’490 patent and Niijima use the terms sector and
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`page according to the ordinary and customary meanings of the terms. Specifically,
`
`having read both disclosures, a person of ordinary skill in the art would have
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`understood that in the ’490 patent and in Niijima, a sector is the unit of read/write
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`access between the host (e.g., a CPU) and the flash memory controller (e.g., the
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`SSF), while a page is the unit of read/write access between the flash memory
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`controller and the flash memory array. Therefore, the sector disclosed in Niijima,
`
`which contains two pages, anticipates the “plurality of pages,” “at least one page”
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`and “at least another page” elements recited in the claims of the ’490 patent.
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`24. A person of ordinary skill in the art would have understood that the
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`embodiment disclosed in Niijima, in which a sector constitutes two pages, is only
`
`one possible embodiment. In the particular embodiment, “a 16 Mbit flash memory
`
`is used, one physical sector uses two word lines in a flash EEPROM. That is, two
`
`pages constitute one sector.” Ex. 1206 at 5:38-40. A person of ordinary skill in
`
`the art would have understood that flash memory embodiments in which one
`
`physical sector uses only one word line (i.e., one page constitutes one sector) were
`
`
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`9
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0012
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`common at the time of the ’490 patent. Therefore, it would have been obvious to
`
`one of ordinary skill in the art to substitute single-page sectors for the “pages”
`
`recited in the claims of the ’490 patent because the cells in a single-page sector
`
`could be substituted for the page-sized unit of access to obtain predicable results.
`
`25. The ’490 patent expressly acknowledges that different techniques can
`
`be used to record a time stamp, including recording the output of a real-time clock,
`
`or storing the output of a “modulo-N counter.” Ex. 1201 at 8:34-43. A person of
`
`ordinary skill in the art would have understood the techniques listed in the patent to
`
`be exemplary and not exhaustive, and that a sequence of numbers output from a
`
`counter could be used to indicate the relative times of programming under the plain
`
`and ordinary meaning of the term “recording a relative time of programming.”
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`Niijima discloses maintaining information related to the relative time of
`
`programming sectors using a two-level hierarchy where sequence numbers are
`
`stored in clusters and the temporal order in which sectors are programmed is
`
`determined by the sectors’ relative locations within their cluster. Ex. 1206 at 7:60-
`
`8:6. In fact, this is the same method of indicating the relative times of
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`programming disclosed in the ’490 patent. Ex. 1201 at 755-8:4. Therefore, a
`
`person of ordinary skill in the art would have understood that the step of
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`maintaining the time sequence information by the two-level hierarchy disclosed in
`
`
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`10
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0013
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`Niijima anticipates the step of “recording a relative time of programming the new
`
`and superceded data” recited in claim 2 of the ’490 patent.
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`26. Niijima discloses, “If there are a plurality of physical sectors for a
`
`specific logical sector, it is judged that the one in the cluster with the greatest
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`sequence number is valid.” Ex. 1206 at 8:10-13. However, a person of ordinary
`
`skill in the art would have understood that a logical address could not be allocated
`
`to physical sectors in different clusters unless new data that supercedes old data for
`
`the same logical address was programmed into at least one sector of a different
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`cluster. Therefore, Niijima’s disclosure of multiple physical sectors corresponding
`
`to a single logical sector inherently discloses does the step of “programming the
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`pages of updated user data into the second block of memory storage elements.”
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`27. Claim 6 of Niijima recites a “first write request” that specifies a
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`logical address to which the data will be written. Ex. 1206 at 11:1-2. Claim 7 of
`
`Niijima, which depends from claim 6, recites “writing user data into a given one of
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`said N clusters by selecting and writing into, in response to a second write request
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`from said processor, an empty sector of said given one of said N clusters in a
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`sector-address order, until writing of said user data into said given one of said N
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`clusters is finished.” Ex. 1206 at 11:19-24 (emphasis added). In claim 7 of
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`Niijima, “one of said N clusters” refers to any cluster. Further, Niijima discloses
`
`such a second write request (as recited in claim 7 of Niijima) to the same logical
`
`
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`11
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0014
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`address as the first write request. Ex. 1206 at 2:57-61. Therefore, Niijima
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`discloses the step of “programming the pages of updated user data into the second
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`block of memory storage elements.”
`
`28. Also, in response to the second write request recited in claim 7 of
`
`Niijima, it would have been obvious to a person of ordinary skill in the art to
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`program new data into one or more pages comprising a sector within a cluster
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`different from the original cluster, as required by claim [3a], because the sectors of
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`the original cluster may be fully allocated, and a person of ordinary skill in the art
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`would have understood that the only sector available in which to program the new
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`data is located in a different cluster.
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`29. Niijima discloses the well-known method of “dynamic sector
`
`allocation,” which uses flags to mark superceded data sectors invalid. Ex. 1206 at
`
`2:28-67. One of ordinary skill in the art would have understood that dynamic
`
`sector allocation involves flagging superceded sectors invalid instead of copying
`
`unchanged sectors of data to a new cluster. The ’490 patent admits that using flags
`
`to mark superceded pages invalid eliminates the need to copy unchanged pages of
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`data to a new block. Ex. 1201 at 2:20-25. The invention of Niijima, like the ’490
`
`patent, achieves the benefits of using flags via other means that do not involve
`
`flags. Ex. 1201 at 2:32-36; Ex. 1206 at 3:14-29, 7:38-40. Therefore, it is not
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`surprising that Niijima never discloses copying non-superceded sectors of data to
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`
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0015
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`another cluster. A person of ordinary skill in the art would have understood that
`
`Niijima inherently discloses substituting new data for superceded data by
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`programming the new data into the sectors of another cluster, while non-
`
`superceded data in the sectors of the original cluster are not copied into the other
`
`cluster, because avoiding the need to copy unchanged data is the primary benefit of
`
`the dynamic sector allocation method used in Niijima. A person of ordinary skill
`
`in the art would also have understood that Niijima writes into one block an updated
`
`version of less than all of the original data stored in another block.
`
`30. The ’490 patent admits that the prior art substitutes new data for
`
`superceded data within at least one page of one of the plurality of blocks while data
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`in at least another page of said one block is not being superceded, using a
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`technique that “writes the updated pages to a new block but eliminates the need to
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`copy the other pages of data into the new block.” Ex. 1201 at 2:20-25. Therefore,
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`to the extent Niijima does not expressly or inherently disclose this limitation, the
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`limitation would have been obvious to try in combination with Niijima because it
`
`was an admittedly identified and predictable solution with a reasonable expectation
`
`of success.
`
`31. Niijima discloses using sequences of numbers to indicate the relative
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`time of programming. Ex. 1206 at 3:30-4:12. Storing the value of a clock was
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`well-known at the time of the ’490 patent. For example, this is shown in
`
`
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0016
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`Kidokoro, which discloses a timestamp used as a sequence number to indicate the
`
`relative time of programming. It would have been obvious to a person of ordinary
`
`skill in the art to substitute the sequence numbers disclosed in Niijima with clock
`
`values because clock values were well known and would have achieved the
`
`predictable result of indicating the relative times of programming the new and the
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`superceded data. Computers typically generate or have access to a clock that can
`
`be used for this purpose.
`
`32. Niijima explains that the relative positions of sectors within a cluster
`
`indicate the relative time of programming the new and superceded data within the
`
`sectors because sectors are programmed according to their physical order within
`
`the cluster. Ex. 1206, 7:40-8:6. Therefore, the locations of the physical pages
`
`must represent values indicating the relative times of programming new and
`
`superceded data. Therefore, Niijima discloses individual values indicating the
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`relative times of programming the new and superceded data, the values stored
`
`within the same pages as the new and superceded data to which the values relate.
`
`33. The ’490 patent admits that storing information related to user data in
`
`the same page as the user data was a known technique at the time of the ’490
`
`patent. Ex. 1201 at 1:41-43, 5:53-55. Therefore, having read Niijima, it would
`
`have been obvious to a person of ordinary skill in the art to store the individual
`
`values indicating the relative times of programming within the same sectors as the
`
`
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`EXHIBIT 1203 - PAGE 0017
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`new and superceded data to which the values relate because the time of
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`programming data is information related to the data, and storing that data within
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`the same sector as the data itself simply applies a known technique to a known
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`flash memory architecture ready for improvement to achieve predictable results.
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`34. The ’490 patent discloses recording at least the logical block number
`
`in the individual pages as overhead data as a known technique in the art as of the
`
`priority date of the ’490 patent. Ex. 1201 at 5:53-55, 6:42-43, 8:13-16, Figs. 4-7B.
`
`It would have been obvious to a person of ordinary skill in the art to record at least
`
`part of the common logical address in the individual sectors of Niijima as overhead
`
`data. Recording data-related information as overhead data in the pages was well-
`
`known at the time, and it would have been obvious to store common logical
`
`address information in this way due to the clear benefits in, for example, error
`
`correction and identification. Therefore, it would have been obvious to apply this
`
`technique to Niijima because recording at least part of the common logical address
`
`as overhead data in the individual pages as overhead data applies a known
`
`technique to a known flash memory architecture ready for improvement to yield
`
`predictable results
`
`35. At the time of the ’490 patent, it was common to refer to a random
`
`access memory as a “RAM.” RAM was (and still is) a type of volatile memory,
`
`meaning that the data stored in RAM is lost when power to the RAM is lost.
`
`
`
`15
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0018
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`
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
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`Therefore, a person of ordinary skill in the art would have understood RAM to
`
`refer to volatile memory.
`
`36. Niijima discloses that the relative times when sectors within a cluster
`
`are programmed are determined by the sectors’ relative positions within the
`
`cluster. Ex. 1206, 7:40-8:6. Having read Niijima, a person of ordinary skill in the
`
`art at time of the ’490 patent would have understood that in order to determine the
`
`relative times at which the sectors within a cluster are programmed, the relative
`
`positions of the sectors (indicating the relative times of programming the sectors)
`
`must be recorded somewhere, such as within the software or hardware of the
`
`memory controller 30. Ex. 1206 at 2:48-51, 2:57-61, 3:37-65, 6:66-7:10, 9:34-39.
`
`Since the relative positions indicating the relative times of programming must be
`
`recorded in order for them to be used, Niijima inherently discloses the limitation
`
`“wherein the relative time of programming is recorded for the individual pages in
`
`which the new and superceded data are programmed.”
`
`37. Niijima discloses that the address translation table must be
`
`reconstructed when the system is powered up. Ex. 1206 at 3:1-3. One of ordinary
`
`skill in the art would have understood that the only way to accurately reconstruct
`
`the address translation table is to read each sector of each cluster and distinguish
`
`between valid and superceded sectors. Therefore, Niijima inherently discloses
`
`reading pages of data from said one block and, if new data has been programmed
`
`
`
`16
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0019
`
`
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
`
`thereinto, said another block. Therefore, one of ordinary skill in the art would have
`
`understood Niijima to inherently disclose reading pages of data from each block.
`
`38. A person of ordinary skill in the art would have understood Niijima to
`
`disclose a table linking logical addresses of flash memory to the physical memory
`
`addresses where the data is stored. That linking is done in such a way that, when a
`
`sector of memory is updated, the table linking the logical address of the memory to
`
`the physical address is also updated so that the corresponding physical address
`
`reflects the newest data written to that logical address, in order for the table to
`
`remain current with the actual data. As I discussed earlier, the ’490 patent
`
`acknowledges that partial block updates, in which only a portion of sectors within
`
`a cluster are updated, are common. In the event of a partial block update, a person
`
`having ordinary skill in the art of the ’490 patent would have understood the table
`
`linking logical addresses to physical addresses to be updated so that the physical
`
`address corresponding to a sector that has been updated is the location of the most
`
`current (updated) data.
`
`39. Niijima discloses that when reading data, the data in the most current
`
`of any sectors having the same logical address is collected . Ex. 1206 at 2:54-56.
`
`Having read Niijima, a person of ordinary skill in the art would have understood
`
`that whenever a request is made to read data from a particular logical address, data
`
`from the most recent sector allocated to that logical address (i.e., the newest data
`
`
`
`17
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0020
`
`
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`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
`
`written to the particular logical address) would be retrieved from memory. This is
`
`a fundamental requirement of a properly operating flash memory system. One of
`
`ordinary skill in the art would also have understood that when writing data to
`
`memory, it is common for only some sectors within a cluster to require updating,
`
`and therefore, when reading data from a cluster, the data is assembled using the
`
`most current of any sectors having the same logical address, along with any non-
`
`superceded sectors within the cluster. Therefore, Niijima expressly or inherently
`
`discloses the method step “assembling data in the most current of any pages having
`
`the same logical address along with pages in said at least another page of said one
`
`block that have not been superceded” recited in claim [10g].
`
`40. The ’490 patent admits that assembling data using new data stored in
`
`a page belonging to the same or a different block, along with pages of non-
`
`superceded data within the same block, was known before the invention of the
`
`’490 patent. Ex. 1201 at 2:20-28. Therefore, it would have been obvious to
`
`assemble the data in Niijima as recited in claim [10g] because “assembling data in
`
`the most current of any pages having the same logical address along with pages in
`
`said at least another page of said one block that have not been superceded” simply
`
`applies a known technique to a known flash memory device ready for
`
`improvement to achieve predictable results.
`
`
`
`18
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`APPLE INC.
`EXHIBIT 1203 - PAGE 0021
`
`
`
`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
`
`41. A person of ordinary skill in the art would have understood that flash
`
`memory storage elements having more than two storage states, thereby storing
`
`more than one bit of data (i.e., more than “two storage states”) in each storage
`
`element, were well known as of the priority date of the ’490 patent. For instance,
`
`Exhibit 1208 is the Flash Memories text by Cappelletti, which was published in
`
`1999. Cappelletti describes flash memory technology in detail, including multi-
`
`level flash memory cells operated with more than two storage states. See Ex. 1208
`
`at 137-146. Cappelletti is indicative of what was generally known in the art at the
`
`time of the ’490 patent. Additionally, the ’490 patent itself notes that multi-state
`
`flash memory devices were known as of the priority date of the ’490 patent. Ex.
`
`1201 at 4:19-36. Simply substituting the two-state flash memory cells disclosed in
`
`Niijima with well-known multi-state flash memory cells would yield only
`
`predictable results. Therefore, the additional element recited in claim 12 (i.e.,
`
`“operating the individual memory storage elements with more than two storage
`
`states”) would have been obvious to a person of ordinary skill in the art.
`
`Therefore, in my opinion, Niijima in combination with the knowledge of a person
`
`of ordinary skill in the art at the time of the ’490 patent renders claim 12 obvious.
`
`For the same reasons, the additional element recited in claim 13 (i.e., “operating
`
`storage elements of the individual memory cells with more than two storage
`
`states”) would have been obvious to a person of ordinary skill in the art.
`
`
`
`19
`
`APPLE INC.
`EXHIBIT 1203 - PAGE 0022
`
`
`
`U.S. Patent No. 7,818,490
` Declaration in Support of Petition For Inter Partes Review
`
`Therefore, in my opinion, Niijima in combination with the knowledge of a person
`
`of ordinary skill in the art at the time of the ’490 patent renders claim 13 obvious.
`
`42. A person of ordinary skill in the art would have understood that flash
`
`memory storage elements having individual floating gates were well known as of
`
`the priority date of the ’490 patent. In fact, floating gates are essential to the
`
`proper operation of a flash memory device, and flash memory cells are almost
`
`always made us
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