IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Conley:
`
`U.S. Pat. No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND READING
`OPERATIONS IN A NON-VOLATILE
`MEMORY
`
`Petition for Inter Partes Review
`
`Attorney Docket No.:
`337722-70.490b
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`Real Party-in-Interest: Apple Inc.
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`Pursuant to the provisions of 35 U.S.C. §§ 311-319, Apple Inc. (hereinafter
`
`“Petitioner”) hereby petitions the Patent Trial and Appeal Board to institute an
`
`inter partes review of claims 34-38 and 40-64 of United States Patent
`
`No. 7,818,490 (“the ’490 patent”)
`
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`

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`TABLE OF CONTENTS
`
`
`Page
`
`
`I. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Lead and Back-up Counsel .................................................................. 2
`D.
`Service Information .............................................................................. 2
`II. GROUNDS FOR STANDING ....................................................................... 2
`III. RELIEF REQUESTED .................................................................................. 3
`IV. THE REASONS FOR THE REQUESTED RELIEF ..................................... 3
`A.
`Summary of Reasons ............................................................................ 3
`B.
`Relevant Technology Background (Flash Memory) ............................ 4
`C. Overview of the ’490 Patent ................................................................. 7
`D.
`Level of Ordinary Skill in the Art ........................................................ 9
`E.
`Claim Construction............................................................................... 9
`1.
`“metablock” (claims 42 and 58) .............................................. 10
`Challenge #1: Niijima Anticipates Claims 34-38, 40, 41, 43-45,
`50-57 and 59-64, or Renders Those Claims Obvious in View of
`the Knowledge of A Person of Ordinary Skill in the Art................... 11
`1.
`Overview of Niijima ................................................................ 11
`2.
`Niijima anticipates or renders obvious claim 34 ..................... 15
`3.
`Niijima anticipates or renders obvious claim 35 ..................... 21
`4.
`Niijima anticipates or renders obvious claim 36 ..................... 23
`5.
`Niijima anticipates or renders obvious claim 37 ..................... 23
`6.
`Niijima anticipates or renders obvious claim 38 ..................... 26
`7.
`Niijima anticipates or renders obvious claim 40 ..................... 26
`8.
`Niijima anticipates or renders obvious claim 41 ..................... 28
`9.
`Niijima anticipates or renders obvious claim 43 ..................... 29
`10. Niijima anticipates or renders obvious claim 44 ..................... 30
`11. Niijima anticipates or renders obvious claim 45 ..................... 31
`
`F.
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`
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`TABLE OF CONTENTS
`(continued)
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`Page
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`12. Niijima anticipates or renders obvious claim 50 ..................... 31
`13. Niijima anticipates or renders obvious claim 51 ..................... 32
`14. Niijima anticipates or renders obvious claim 52 ..................... 33
`15. Niijima anticipates or renders obvious claim 53 ..................... 34
`16. Niijima anticipates or renders obvious claim 54 ..................... 34
`17. Niijima anticipates or renders obvious claim 55 ..................... 35
`18. Niijima anticipates or renders obvious claim 56 ..................... 35
`19. Niijima anticipates or renders obvious claim 57 ..................... 35
`20. Niijima anticipates or renders obvious claim 59 ..................... 36
`21. Niijima anticipates or renders obvious claim 60 ..................... 37
`22. Niijima anticipates or renders obvious claim 61 ..................... 39
`23. Niijima anticipates or renders obvious claim 62 ..................... 40
`24. Niijima anticipates or renders obvious claim 63 ..................... 41
`25. Niijima anticipates or renders obvious claim 64 ..................... 42
`Challenge #2: Niijima in View of Wells Renders Claims 42 and
`58 Obvious ......................................................................................... 43
`1.
`Overview of Wells ................................................................... 43
`2.
`Niijima in view of Wells renders claim 42 obvious ................ 45
`3.
`Niijima in view of Wells renders claim 58 obvious ................ 48
`Challenge #3 (Multi-Bit Claims): Niijima and the Admitted
`Prior Art or Cappelletti Renders Claims 46 and 47 Obvious. ............ 48
`1.
`Niijima and the Admitted Prior Art or Cappelletti renders
`claim 46 obvious ...................................................................... 49
`Niijima and the Admitted Prior Art or Cappelletti renders
`claim 47 obvious ...................................................................... 50
`Challenge #4 (Floating Gates): Niijima and the Admitted Prior
`Art or Cappelletti Render Claim 48 Obvious ..................................... 51
`
`2.
`
`G.
`
`H.
`
`I.
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`TABLE OF CONTENTS
`(continued)
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`Page
`
`J.
`
`1.
`
`Niijima and the Admitted Prior Art or Cappelletti renders
`claim 48 obvious ...................................................................... 51
`Challenge #5 (Enclosure Card): Niijima and the Admitted Prior
`Art or the PC Card Standard Renders Claim 49 Obvious .................. 52
`1.
`Niijima and the Admitted Prior Art or the PC Card
`standard renders claim 49 obvious ........................................... 52
`CONCLUSION ............................................................................................. 53
`
`
`
`V.
`
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`

`
`EXHIBITS
`EXHIBITS
`
`Ex. 1101
`EX.
`1101
`
`U.S. Patent No. 7,818,490 to Conley (“the ’490 patent”)
`U.S. Patent No. 7,818,490 to Conley (“the ’490 patent”)
`
`Ex. 1102
`EX.
`1102
`
`Prosecution File History for U.S. Patent No. 7,818,490
`Prosecution File History for U.S. Patent No. 7,818,490
`
`Ex. 1103
`EX.
`1103
`
`Declaration of Dr. Vivek Subramanian
`Declaration of Dr. Vivek Subramanian
`
`Ex. 1104
`EX.
`1104
`
`CV for Dr. Vivek Subramanian
`CV for Dr. Vivek Subramanian
`
`Ex. 1105
`EX.
`1105
`
`U.S. Patent No. 5,822,781 to Wells (“Wells”)
`U.S. Patent No. 5,822,781 to Wells (“Wells”)
`
`Ex. 1106
`EX.
`1106
`
`U.S. Patent No. 5,457,658 to Niijima (“Nijima”)
`U.S. Patent No. 5,457,658 to Niijima (“Nijima”)
`
`Ex. 1108
`EX.
`1108
`
`Flash Memories, edited by Cappelletti, et al (1999)
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`(“Cappelletti”)
`
`Ex. 1109
`EX.
`1109
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC Card
`PC Card Standard, Volumes 1 and 3 (1999) (“PC Card
`
`Standard”)
`Standard”)
`
`Ex. 1110
`EX.
`1110
`
`PCT WO 99/35650 (“Hazen”)
`PCT WO 99/35650 (“Hazen”)
`
`Ex. 1111
`1111
`EX.
`
`Designing With Flash Memory, Brian Dipert and Markus
`Designing With Flash Memory, Brian Dipert and Markus
`
`Levy (1994) (“Dipert”)
`Levy (1994) (“Dipert”)
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`iv
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
`
`I. Mandatory Notices
`
`A. Real Party-in-Interest
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), the real party-in-interest is Apple Inc.
`
`B. Related Matters
`
`Petitioner states that Longitude Flash Memory Systems S.A.R.L. (“Patent
`
`Owner”) is asserting the ’490 patent against the real party-in-interest in a suit filed
`
`September 23, 2014, Longitude Licensing Ltd. v. Apple Inc., Case No. 3:14-cv-
`
`4275, pending in the USDC for N.D. Cal. (“Related Litigation”). Petitioner has
`
`filed, or soon will file, IPR petitions for U.S. Patent Nos. 6,510,488; 6,763,424 (the
`
`“’424 patent”); 6,831,865; 6,968,421; 7,012,835; 7,120,729; 7,224,607; 7,181,611;
`
`7,657,702 (the “’702 patent”); 7,970,987; 8,050,095; and 8,316,177. Petitioner
`
`also is concurrently filing two other petitions for the ’490 patent for claims other
`
`than the ones at issue in this petition.
`
`The ’424 patent, which is the parent of the ’490 patent, was the subject of
`
`previous litigation and the following opinions in which one or more claim terms
`
`found in both patents were construed: (1) SanDisk Corp. v. Kingston Tech. Co.,
`
`695 F.3d 1348 (Fed. Cir. 2012); (2) In the Matter of Certain Flash Memory
`
`Controllers, USITC, Inv. No. 337-TA-619, Order No. 33, July 15, 2008 (Bullock,
`
`ALJ); and (3) In the Matter of Certain Flash Memory Controllers, USITC, Inv.
`
`No. 337-TA-619, Commission Opinion, November 24, 2009. The ’702 patent,
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`
`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
`
`which is in the same family as the ’490 patent, was the subject of previous
`
`litigation and the following opinion in which some of its terms were construed:
`
`SanDisk Corp. v. Kingston Tech. Co., Inc., USDC for W.D. Wis., Case No. 10-cv-
`
`243-bbc, March 16, 2011 (Crabb, J.).
`
`No other judicial or administrative matters are presently known to Petitioner
`
`that would affect or be affected by an IPR of the ’490 patent.
`
`C. Lead and Back-up Counsel
`
`Lead counsel for this matter is Brent Yamashita (USPTO Reg. No. 53,808),
`
`and back-up counsel for this matter are Ed Sikorski (USPTO Reg. No. 39,478) and
`
`Kevin Hamilton (USPTO Reg. No. 67,593), all at: Apple-Longitude-
`
`IPR@dlapiper.com, and DLA Piper LLP (US), 2000 University Avenue, East Palo
`
`Alto, California, 94303, and the phone number is 650-833-2000.
`
`D.
`
`Service Information
`
`Pursuant to 37 C.F.R. § 42.8(b)(4), papers concerning this matter should be
`
`served on the following email address: Apple-Longitude-IPR@dlapiper.com.
`
`II. Grounds for Standing
`
`Petitioner certifies that the ’490 patent is available for inter partes review
`
`and that Petitioner is not estopped or barred from requesting inter partes review
`
`challenging the ’490 patent on the grounds identified in this petition.
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`III. Relief Requested
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis, institute a trial for inter partes review of claims 34-38 and 40-64 of the
`
`’490 patent, and cancel those claims as invalid for the reasons set forth below.
`
`IV. The Reasons for the Requested Relief
`
`A.
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`Summary of Reasons
`
`Challenge #1: Niijima anticipates claims 34-38, 40, 41, 43-45, 50-57
`
`and 59-64, or renders those claims obvious in view of the knowledge
`
`of a person of ordinary skill in the art.
`
`Challenge #2: Niijima in view of Wells renders claims 42 and 58
`
`obvious.
`
`Challenge #3 (Multi-Bit Claims): Niijima and the Admitted Prior
`
`Art or Cappelletti render claims 46 and 47 obvious.
`
`Challenge #4 (Floating Gates): Niijima and the Admitted Prior Art
`
`or Cappelletti render claim 48 obvious.
`
`Challenge #5 (Enclosure Card): Niijima and the Admitted Prior Art
`
`or the PC Card Standard renders claim 49 obvious.
`
`Challenge #6 (Metablock): If the Board rejects Challenge #2 based
`
`on the “metablock” element, then claims 42 and 58 are rendered
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`obvious by Niijima and Wells, and the knowledge of one of ordinary
`
`skill in the art, Hazen or Dipert.
`
`B. Relevant Technology Background (Flash Memory)
`
`A flash memory device contains one or more arrays of non-volatile memory
`
`cells. (Ex. 1101 at 1:29-34). Non-volatile memory cells retain their data when
`
`power is removed. (Id.). However, unlike most types of non-volatile memory
`
`cells (such as ROM cells), flash memory cells are reprogrammable. (Id.). The
`
`typical flash memory architecture used to achieve non-volatility and
`
`reprogrammability has several functional limitations. For example, once a flash
`
`memory cell is programmed with data, the cell must be erased before that cell can
`
`be reprogrammed with new data. (Id.). Further, prohibitively large and time
`
`consuming circuitry would be required to erase flash memory cells individually.
`
`(Ex. 1101 at 1:34-50). Therefore, instead of erasing individual cells, the typical
`
`flash memory has large groups of cells arranged into erasable blocks, a block
`
`containing the smallest number of cells that can be erased at one time. (Id.). It is
`
`desirable to read or write data in units smaller than the size of a block. (Ex. 1101
`
`at 1:51-58). Therefore, blocks are further partitioned into pages, a page containing
`
`the smallest number of cells that can be read or written at one time. (Id.). Also, in
`
`some flash memories, the pages within each block can only be programmed in a
`
`physically sequential manner. (Ex. 1101 at 7:1-4; Ex. 1103 at ¶ 15).
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`In addition to user data, each page in a flash memory can contain a set of
`
`overhead data fields and flags to store information related to the user data. (Ex.
`
`1101 at 1:41-43, 5:53-55). For example, each time user data is written to a page, a
`
`logical block number (“LBN”) indicating the data’s logical address can be
`
`recorded in a data field within the page. (Ex. 1101 at 1:59-65, 5:41-55, 6:15-19,
`
`6:42-43). Figure 6 of the ’490 patent, shown below, illustrates some elements of
`
`the typical flash memory architecture.
`
`
`
`(Ex. 1101 at Figure 6; Ex. 1103 at ¶ 16).
`
`The block and page architecture of the typical flash memory presents several
`
`challenges when updating user data. In the ideal case, the data in all pages of a
`
`block are modified together and written to the pages of an erased block. (Ex. 1101
`
`at 2:4-6). However, a partial block update is more common, in which the data in
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`only some pages within a block are updated, while the data in the remaining pages
`
`is unchanged. (Ex. 1101 at 2:8-10). At least two techniques to perform a partial
`
`block update in a flash memory device were well known when the ’490 patent was
`
`filed and are acknowledged as prior art by the ’490 patent itself. (Ex. 1101 at 2:4-
`
`28). The first technique involves writing the updated data into a new, erased block.
`
`(Id.) The system then copies the unchanged data from the old block into the new
`
`block. (Id.). Finally, the system erases the old block. (Id.). This technique is
`
`inefficient because it requires copying unchanged pages of data to a different
`
`block. (Id.; Ex. 1103 at ¶¶ 17-18).
`
`The second known partial block update technique also involves writing the
`
`data of the updated pages to a corresponding number of pages in a new block. (Ex.
`
`1101 at 2:20-28; Ex. 1103 at ¶ 18). However, instead of copying the unchanged
`
`pages of data to the new block, the flags of the pages in the original block which
`
`are being updated are modified to indicate that those pages contain superseded
`
`data. (Id.). When reading the data, the updated data from pages of the new block
`
`are combined with the unchanged data from the pages of the original block that are
`
`not flagged as superseded. (Id.). While the second technique avoids copying the
`
`unchanged data to the new block, it still requires updating a flag in each
`
`superceded page. (Id.)
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
`
`C. Overview of the ’490 Patent
`
`The ’490 patent discloses a method and apparatus for an improved partial
`
`block transfer that does not require copying the unchanged pages of data to the
`
`new block (like the prior art), and also does not require modifying the flags of the
`
`pages in the original block which are being updated to indicate they contain
`
`superseded data. (Ex. 1101 at 2:32-36). By eliminating the step of modifying the
`
`flags in the superceded pages, “a potential of disturbing the previously written data
`
`in adjacent pages of that same block that can occur from such a writing operation is
`
`eliminated. Also, a performance penalty of the additional program operation is
`
`avoided.” (Ex. 1101 at 2:58-63). The ’490 patent purports to achieve these
`
`advantages “by maintaining both the superceded data pages and the updated pages
`
`of data with a common logical address. The original and updated pages of data are
`
`then distinguished by the relative order in which they were programmed.” (Ex.
`
`1101 at 2:37-41).
`
`The ’490 patent eliminates the need to modify flags by tracking the relative
`
`order in which pages having the same logical address are programmed. (Id. at
`
`2:37-41). Among pages with the same logical address, only the page most recently
`
`programmed has valid data. (Id.) Specifically, the ’490 patent explains:
`
`“But rather than tagging the pages containing original data as being
`
`superceded, the memory controller distinguishes the pages containing
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`the superceded data from those containing the new, updated version
`
`either (1) by keeping track of the order in which the pages having the
`
`same logical addresses were written, such as by use of a counter,
`
`and/or (2) from the physical page addresses wherein, when pages are
`
`written in order within blocks from the lowest page address to the
`
`highest, the higher physical address contains the most recent copy of
`
`the data.”
`
`(Ex. 1101 at 7:58-67). An example embodiment distinguishes valid and invalid
`
`pages using a combination of time stamps written to blocks and the relative
`
`locations of pages within each block, exploiting the fact that the pages within each
`
`block must be programmed in a known physical order to determine the order in
`
`which pages within the block were programmed. (Id. at 9:37-50). Specifically, the
`
`’490 patent explains:
`
`“A second specific implementation of the inventive technique can also
`
`be described with respect to FIG. 8. In this example, the time stamp is
`
`used only to determine the relative age of the data stored in blocks,
`
`While the most recent pages among those that carry the same LBN
`
`and page number are determined by their relative physical locations.
`
`The time stamp 43 then does not need to be stored as part of each
`
`page. Rather, a single time stamp can be recorded for each block,
`
`either as part of the block or elsewhere within the non-volatile
`
`memory, and is updated each time a page of data is written into the
`
`block.”
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`(Id. at 9:37-50).
`
`Therefore, the ’490 uses a combination of known prior art, including only
`
`writing updated pages to the new block, and the known limitation of certain flash
`
`memories that pages within each block must be written sequentially, to achieve its
`
`goal of performing a partial block update without modifying the flags of the
`
`superceded pages. In fact, the only element in the implementation above for which
`
`the ’490 patent even claims novelty is the use of a timestamp to record the relative
`
`times at which blocks are programmed. As shown below, Niijima contains all of
`
`the alleged novel elements and/or renders them obvious in light of the knowledge
`
`of one of ordinary skill in the art.
`
`D. Level of Ordinary Skill in the Art
`
`A person of ordinary skill in the relevant art at the time of the ’490 patent
`
`would have had a Master’s Degree or equivalent in electrical engineering or a
`
`related field and two years of experience in memory technology or the equivalent.
`
`(Ex. 1103 at ¶14).
`
`E. Claim Construction
`
`For unexpired patents, claims should be given the “broadest reasonable
`
`interpretation in light of the specification” (“BRI”). See 37 C.F.R. § 42.100(b) and
`
`42.204(b)(3). Due to the different claim construction standards of IPR and U.S.
`
`District Court proceedings, Petitioner expressly reserves the right to assert different
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
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`claim constructions and to take different positions with respect to any claim terms
`
`of the ’490 patent construed in the Related Litigation or any other proceeding.
`
`1.
`
`“metablock” (claims 42 and 58)
`
`
`
`This term was previously construed by the Federal Circuit in prior litigation
`
`involving the ’424 patent, SanDisk Corp. v. Kingston Tech. Co., 695 F.3d 1348,
`
`1359 (Fed. Cir. 2012). The Federal Circuit discussed the meaning of the term but
`
`apparently did so in an ambiguous manner because Petitioner and Patent Owner
`
`have expressed different views on the Federal Circuit’s construction in the Related
`
`Litigation, although both agree the meaning of this term should be the same for the
`
`’490 patent as in the ’424 patent.
`
`
`
`Petitioner contends the phrase means: “set of blocks associated together
`
`such that during operation they are programmed, read, or erased together as a
`
`unit.” Patent Owner contends the phrase means: “two or more blocks positioned
`
`in separate units of one or more memory chips for programming and reading
`
`together in parallel as part of a single operation.”
`
`
`
`The difference in constructions does not impact the validity analysis
`
`contained herein, and the conclusions are the same under either construction. (Ex.
`
`1103 at ¶ 21).
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
`
`F. Challenge #1: Niijima Anticipates Claims 34-38, 40, 41, 43-45, 50-
`57 and 59-64, or Renders Those Claims Obvious in View of the
`Knowledge of A Person of Ordinary Skill in the Art
`
`The earliest claimed priority date of the ’490 patent is the filing date of
`
`parent U.S. Patent Application No. 09/766,436, filed on November 19, 2001.
`
`Niijima issued on October 10, 1995, more than one year before the claimed priority
`
`date of the ’490 patent. Niijima is therefore prior art to the ’490 patent under pre-
`
`AIA 35 U.S.C. § 102(a), (b) and (e), and pre-AIA 35 U.S.C. § 103(a).
`
`As explained below, Niijima discloses all elements and limitations of claims
`
`34-38, 40, 41, 43-45, 50-57 and 59-64 of the ’490 patent. To the extent a claim
`
`element or limitation is not disclosed, Niijima renders obvious claims 34-38, 40,
`
`41, 43-45, 50-57 and 59-64 of the ’490 patent, particularly when viewed in
`
`conjunction with the knowledge of a person of ordinary skill in the art as of the
`
`priority date of the ’490 patent.
`
`1. Overview of Niijima
`
`Niijima discloses a nonvolatile memory with cluster-erase flash capability
`
`and a solid state file apparatus (“SSF”) that can dynamically allocate flash memory
`
`sectors. (Ex. 1106 at 1:10-14). Niijima is based in part on a “dynamic sector
`
`allocation” method for flash memories previously disclosed in Japanese Patent
`
`Application No. 3-197318. (Id. at 7:38). Niijima explains that dynamic sector
`
`allocation involves creating and maintaining an address translation table to map
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`U.S. Pat. No. 7,818,490
`Petition For Inter Partes Review
`
`between logical addresses specified by a host processor and physical address
`
`within a flash-memory-based SSF. (Id. at 2:28-35). In addition to storing data,
`
`each addressable sector in the SSF includes a reverse reference pointer (“RP”) area
`
`to store the logical address corresponding to the data stored in the sector, and a
`
`status area storing flags to indicate whether or not the data stored in the sector is
`
`valid. (Id. at 2:35-56).
`
`When the SSF receives a command from the host processor to write data to a
`
`logical address, the SSF allocates a new physical flash memory sector to the
`
`logical address, writes the data to the physical sector’s data area, writes the logical
`
`address to the RP area of the physical sector, and sets a “valid” flag in the status
`
`area of the physical sector. (Id. at 2:45-56). The SSF also records the physical
`
`address of the allocated physical sector in an address translation table entry for the
`
`logical address. (Id. at 2:51-53). The results of writing data to logical address
`
`“(1,4,5)” are illustrated in Figure 1 of Niijima, shown below. (Id. at 2:45-56).
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`When the SSF again receives a command from the host processor to write
`
`new data to the same logical address, the SSF sets an “invalid” flag in the status
`
`area of the physical sector previously allocated to that logical address. (Id. at 2:57-
`
`67). The SSF allocates another new physical sector of the flash memory to the
`
`logical address, writes the new data to the data area of the new sector, writes the
`
`logical address to the RP area of the new sector, and sets a “valid” flag in the status
`
`area of the new sector. (Id.). The SSF also records the physical address of the new
`
`sector in the address translation table entry for the logical address. (Id.). The
`
`results of writing new data to logical address “(1,4,5)” are illustrated in Figure 2 of
`
`Niijima, shown below. (Id. at 2:57-67).
`
`
`
`Niijima describes known methods of updating the “valid” and “invalid”
`
`flags within the status area of an allocated physical sector. (Id. at 3:11-22). Like
`
`the ’490 patent, Niijima explains that it is difficult, and in some cases impossible,
`
`to update a sector’s status flags once data is written to the sector. (Ex. 1101 at
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`6:61-7:4; Ex. 1106 at 3:11-22). Also like the ’490 patent, Niijima explains that the
`
`object of the invention is to provide a flash memory that operates without the need
`
`to update the flags. (Ex. 1101 at 2:32-36, 7:8-12; Ex. 1106 at 3:14-22, 3:26-29).
`
`To this end, Niijima discloses:
`
`“4) Writing into a sector uses a dynamic allocation method. However,
`
`unlike Japanese Pat. Appln. No. 3-197318, it does not set valid/invalid
`
`flags.”
`
`(Ex. 1106 at 7:38-41). Instead of relying of status flags to distinguish valid and
`
`invalid sectors, Niijima recognizes that “it is easy to distinguish valid sectors from
`
`invalid sectors if the sequence of all sectors in time order can be determined.” (Id.
`
`at 7:60-62). Using the same method later claimed in the ’490 patent, Niijima
`
`determines the order in which all sectors were written using sequence numbers
`
`written to clusters and the relative locations of sectors within their clusters:
`
`“The present invention maintains this time sequence information by
`
`two-level hierarchies, the cluster and the sector. Clusters are
`
`sequenced by sequence numbers in cluster information sectors… .
`
`Sectors are sequenced by the locations where they are in their clusters
`
`due to the write methods described in 4). By combining them, the
`
`sequence of all sectors
`
`in
`
`temporal order can be uniquely
`
`determined… .”
`
`(Id. at 7:54-8:6). The write method described in 4) explains that “[s]ectors in the
`
`same cluster are written in ascending or descending order of address.” (Id. at 7:40-
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`41). Therefore, Niijima identifies precisely the same problem, and anticipates
`
`precisely the same solution, as the ’490 patent.
`
`
`
`2.
`
`Niijima anticipates or renders obvious claim 34
`
`Claim 34
`[34pre] In a re-
`programmable non-
`volatile semiconductor
`memory system having
`a plurality of blocks of a
`minimum number of
`memory charge storage
`elements that are
`erasable together as a
`unit, the plurality of
`blocks individually
`being divided into a
`plurality of a given
`number of pages of
`memory storage
`elements that are
`individually
`programmable as a unit
`and which have
`specified offset
`positions within their
`respective blocks, a
`method of operating the
`memory system,
`comprising:
`
`“Niijima” (Ex. 1106)
`Niijima discloses “a nonvolatile memory with
`cluster-erase flash capability.” (Ex. 1106 at 1:10-11;
`see also Id. at Title, Fig. 4, 3:26-29, 4:57-61, 5:24-
`34). The nonvolatile memory “comprises N clusters,
`each comprising M sectors, wherein M and N are
`integers greater than one.” (Id. at 3:31-33). Niijima
`explains, “The cluster consists of one or more blocks
`each of which is a physical erasure unit.” (Id. at
`5:43-45; see also Id. at 1:60-63). Niijima discloses
`an embodiment in which a sector “is the minimum
`access unit of the CPU 10 to the [nonvolatile
`memory].” (Id. at 5:35-38). In the same
`embodiment, “one physical sector uses two word
`lines in a flash EEPROM. That is, two pages
`constitute one sector.” (Id. at 5:38-40). Therefore,
`Niijima discloses a non-volatile memory system
`having a plurality of blocks of memory storage
`elements (i.e., “clusters” and/or “blocks”) that are
`individually organized into a plurality of pages of
`memory storage elements (i.e., “sectors” and/or
`“pages”) that are individually programmable as a
`unit.
`
`As explained below regarding elements [34a] through
`[34e], Niijima discloses a method of operating the
`memory system.
`
`One of ordinary skill in the art would have understood that a non-volatile
`
`flash-memory such as that disclosed in Niijima is a re-programmable non-volatile
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`semiconductor memory system comprising blocks of memory charge storage
`
`elements. (Ex. 1103 at ¶ 15).
`
`The ’490 patent discloses that “a block contains the smallest number of cells
`
`(unit of erase) that are erasable at one time.” (Ex. 1101 at 1:38-40). Likewise,
`
`Niijima discloses an embodiment in which a “cluster consists of one or more
`
`blocks each of which is a physical erasure unit.” (Ex. 1106 at 5:43-45). Since
`
`Niijima expressly discloses an embodiment with a cluster comprising one block,
`
`one of ordinary skill in the art would have understood that the “clusters” disclosed
`
`in Niijima anticipate the “blocks” recited in the claims of the ’490 patent. (Ex.
`
`1103 at ¶ 22). To the extent that “clusters” disclosed in Niijima do not anticipate
`
`the “blocks” claimed in the ’490 patent, it would have been obvious to a person of
`
`ordinary skill in the art to use blocks in place of clusters in Niijima. (Id.).
`
`The ’490 patent discloses that “pages are [] the basic unit for reading and
`
`programming user data (unit of programming and/or reading). Each page usually
`
`stores one sector of user data, but a page may store a partial sector or multiple
`
`sectors. A ‘sector’ is used herein to refer to the an amount of user data that is
`
`transferred to and from the host as a unit.” (Ex. 1101 at 1:53-58). Likewise,
`
`Niijima discloses that a sector “is the minimum access unit of the CPU 10 to the
`
`SSF 20.” (Ex. 1106 at 5:35-38). Niijima also discloses that “two pages constitute
`
`one sector.” (Id. at 5:40). Because Niijima discloses that a sector is the minimum
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`unit of read/write access from the CPU to the SSF, one of ordinary skill in the art
`
`would have understood that the “sector” disclosed in Niijima anticipates the
`
`“page,” “plurality of pages” and “number of pages” elements recited in the claims
`
`of the ’490 patent. (Ex. 1103 at ¶ 23). To the extent that the “sector” disclosed in
`
`Niijima does not anticipate the “page” elements recited in the ’490 patent claims, it
`
`would have been obvious to a person of ordinary skill in the art to use one or more
`
`pages in place of sectors in Niijima. (Ex. 1103 at ¶ 24).
`
`[34a] programming
`original data into
`individual ones of a first
`plurality of pages in at
`least a first block, the
`pages of original data
`having logical addresses
`associated therewith,
`
`[34b] thereafter
`programming, into
`individual ones of a
`second plurality of
`pages in a second block,
`an updated version of
`less than the given
`number of pages of the
`original data
`programmed into the
`first plurality of pages,
`the pages of the updated
`version of the original
`
`Niijima discloses that the SSF receives a command to
`write one or more sectors of data to a logical address.
`For example, Niijima explains:
`
`
`“[W]hen the SSF receives a write command
`regarding a logical address (H, C, S)=(1, 4,
`5) from the host processor, a sector Y, which
`is empty until then, is allo