KLUWER ACADEMIC PUBLISHERS
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0001
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0001
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`

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`FLASH MEMORIES
`FLASH MEMORIES
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0002
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`

`
`FLASH MEMORIES
`
`By
`
`Paulo Cappelletti
`
`Carla Golla
`
`Piero Olivo
`
`Enrico Zanoni
`
`KLUWER ACADEMIC PUBLISHERS
`Boston/Dordrecht/London
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0003
`
`

`
`Distributors for North, Central and South America:
`Kluwer Academic Publishers
`101 Philip Drive
`Assinippi Park
`Norwell, Massachusetts 02061 USA
`Telephone (781) 871-6600
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`E-Mail <kluwer@wkap.corn>
`
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`
`Library of Congress Cataloging-in-Publication Data
`
`Flash memories / by Paulo Cappelletti ... (et al.).
`p. cm
`Includes bibliographical references.
`ISBN 0-7923-8487-3
`1. Flash memories (computers) (cid:9)
`TK7895.M4F58 1999
`004.5--dc21 (cid:9)
`
`I. Cappelletti, Paulo
`
`99-25278
`
`CIP
`
`Copyright © 1999 by Kluwer Academic Publishers
`
`All rights reserved. No part of this publication may be reproduced, stored in a
`retrieval system or transmitted in any form or by any means, mechanical, photo-
`copying, recording, or otherwise, without the prior written permission of the
`publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park,
`Norwell, Massachusetts 02061
`
`Printed on acid-free paper.
`
`Printed in the United States of America
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0004
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`

`
`Contents
`
`1
`FLASH MEMORIES: AN OVERVIEW (cid:9)
`P. Olivo, E. Zanoni
`1.1 Role of Non Volatile Memories in Microelectronic Systems and in Semicon-
`ductor Market (cid:9)
`1.2 Evolution of Non-volatile Memories (cid:9)
`1.3 The Floating Gate Device (cid:9)
`1.4 Charge Injection Mechanisms (cid:9)
`1.5 Erasable Programmable Read Only Memories (cid:9)
`1.5.1 The Floating gate Avalanche-injection MOS transistor (FAMOS) Cell (cid:9)
`1.5.2 The basic Erasable Programmable Read Only Memory (EPROM) (cid:9)
`1.6 Electrically Erasable Programmable Read Only Memories (cid:9)
`1.6.1 The FLOating gate Thin Oxide (FLOTOX) Memory Cell (cid:9)
`1.6.2 Textured Polysilicon Cells (cid:9)
`1.6.3 The EEPROM Architecture (cid:9)
`1.6.4 Ferroelectric Memories (cid:9)
`/1.7 Flash Memories: The Basic ETOX Cell. Programming and Erasing Mecha-
`nisms (cid:9)
`/1.8 Memory NOR Architecture and Related Issues (cid:9)
`
`/1.9 The NAND Flash Mass Storage Concept (cid:9)
`1.10 Embedded Flash Memories (cid:9)
`1.11 The Future of Flash Memories (cid:9)
`1.11.1 Evolution of Flash Memory Technology (cid:9)
`1.11.2 Non Volatile Memories Market Development (cid:9)
`
`References (cid:9)
`
`2
`THE INDUSTRY STANDARD FLASH MEMORY CELL
`P. Pavan, R. Bez
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`1
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`APPLE INC.
`EXHIBIT 1108 - PAGE 0005
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`". .31i' Mfm
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`vi FLASH MEMORIES
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`2.1 Introduction
`2.2 Basic Structure
`2.3 Operating Conditions
`2.3.1 Read
`2.3.2 Program
`2.3.3 Erase
`2.4 Technology and Process
`2.4.1 Isolation
`2.4.2 Well and Channel Doping
`2.4.3 Cell Structure Definition
`2.4.4 (cid:9)
`Interlevel Dielectrics
`2.4.5 Interconnections
`2.4.6 Final Passivation
`2.5 Yield and Reliability (cid:9)
`2.5.1 Retention (cid:9)
`2.5.2 Endurance (cid:9)
`2.5.3 Reading Disturbs (cid:9)
`2.5.4 Programming Disturbs (cid:9)
`2.5.5 Erasing Disturbs (cid:9)
`2.6 Scaling Issues (cid:9)
`
`References (cid:9)
`
`3
`BINARY AND MULTILEVEL FLASH CELLS (cid:9)
`B. Eitan, A. Roy
`3.1 Introduction to Flash Cell Design (cid:9)
`3.2 Binary Flash Cells (cid:9)
`3.2.1 Figures of Merit (cid:9)
`3.2.2 Cell Design Complication Hierarchy from ROM to Flash (cid:9)
`3.2.3 (cid:9) Basis for Flash Cells/Array Classification (cid:9)
`3.2.4 Detailed Description of Flash Cells and Architectures (cid:9)
`• 3.2.5 Scaling and Conclusions (cid:9)
`3.3 Multilevel Flash Cells (cid:9)
`3.3.1 Introduction to the Concept of Multilevel Flash (cid:9)
`3.3.2 Multilevel Programming Mechanisms (cid:9)
`3.3.3 Architectures for Multilevel Flash Memories (cid:9)
`3.3.4 Scaling and Trade-Offs for Multilevel (cid:9)
`
`References (cid:9)
`
`4
`PHYSICAL ASPECTS OF CELL OPERATION AND RELIABILITY (cid:9)
`L. Selnzi, C. Fiegna
`4.1 Introduction (cid:9)
`4.2 Electronic Properties of Carriers and MOS Structures (cid:9)
`Electrons in Crystals (cid:9)
`4.2.1 (cid:9)
`Electrons as Classical Particles (cid:9)
`4.2.2 (cid:9)
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`APPLE INC.
`EXHIBIT 1108 - PAGE 0006
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`Contents (cid:9)
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`vii
`
`4.2.3 Silicon (cid:9)
`4.2.4 Silicon Dioxide (cid:9)
`4.2.5 Silicon - Silicon Dioxide Interface (cid:9)
`4.2.6 Oxide and Interface Traps (cid:9)
`4.3 Fundamentals of Tunneling Phenomena (cid:9)
`4.3.1 Basic Concepts and the WKB Approximation (cid:9)
`4.3.2 Transmission Coefficient (cid:9)
`4.3.3 Tunneling Current (cid:9)
`4.4 Tunneling Phenomena in MOSFETs (cid:9)
`4.4.1 Fowler-Nordheim and Direct Tunneling Through Gate Oxides (cid:9)
`4.4.2 Modeling the Tunnel Current of MOS Structures (cid:9)
`4.4.3 Band-to-band and Trap-to-band Tunneling (cid:9)
`4.4.4 Modeling the Band-to-band and Trap-to-band Tunneling Current (cid:9)
`4.5 Fundamentals of Carrier Transport (cid:9)
`4.5.1 The Distribution Function (cid:9)
`4.5.2 The Boltzmann Transport Equatioh (cid:9)
`4.5.3 Scattering (cid:9)
`4.5.4 The Carrier Distribution in Thermal Equilibrium (cid:9)
`4.5.5 Carrier Distributions in Homogeneous Electric Fields (cid:9)
`4.5.6 The Effective Temperature Model (cid:9)
`4.6 Hot Carrier Effects in MOSFETs (cid:9)
`4.6.1 Carrier Heating in MOSFETs and Flash Cells (cid:9)
`4.6.2 MOSFET Design and Carrier Heating (cid:9)
`4.6.3 Simplified Models of Carrier Heating (cid:9)
`4.6.3.1 Average Energy (cid:9)
`4.6.3.2 (cid:9) Carrier Distribution (cid:9)
`4.6.4 Impact Ionization (cid:9)
`4.6.5 Substrate Current (cid:9)
`4.6.6 Hot Carrier Injection into SiO2 (cid:9)
`4.6.6.1 (cid:9) Distribution Function (cid:9)
`Injection Probability (cid:9)
`4.6.6.2 (cid:9)
`4.6.7 Gate Current (cid:9)
`4.6.7.1 (cid:9) Channel Hot Electron Injection (cid:9)
`4.6.7.2 (cid:9) Drain Avalanche Hot Carrier Injection (cid:9)
`4.6.7.3 Secondary Generated Hot Electron Injection (cid:9)
`4.6.7.4 Substrate Hot Electron Injection (cid:9)
`Implications for Device Operation (cid:9)
`4.6.7.5 (cid:9)
`4.6.8 Hot Carrier Effects at Low Voltages (cid:9)
`4.7 Oxide Degradation due to High Field Stress (cid:9)
`4.7.1 Oxide Wear-out and SILC (cid:9)
`4.7.1.1 Stress Induced Leakage Currents (SILC) (cid:9)
`4.7.2 Oxide Breakdown (cid:9)
`4.7.3 Lifetime Evaluation Models (cid:9)
`4.7.3.1 SILC Lifetime Evaluation Model (cid:9)
`4.7.3.2 Breakdown Lifetime Evaluation Model (cid:9)
`4.8 Oxide and Interface Degradation due to Hot Carrier Injection (cid:9)
`4.8.1 Homogeneous Hot Carrier Degradation (cid:9)
`n-channel Devices (cid:9)
`- 4.8.1.1 (cid:9)
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`APPLE INC.
`EXHIBIT 1108 - PAGE 0007
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`

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`viii FLASH MEMORIES
`
`p-channel Devices (cid:9)
`4.8.1.2 (cid:9)
`4.8.2 Non-homogeneous Hot Carrier Degradation (cid:9)
`4.8.3 Lifetime Evaluation Models (cid:9)
`
`References (cid:9)
`
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`5
`241
`MEMORY ARCHITECTURE AND RELATED ISSUES (cid:9)
`M. Branchetti, G. Campardo, S. Commodaro, S. Ghezzi, A. Ghilardelli, C. Golla, M. Maccarrone,
`Martines, R. Micheloni, J. Mulatti, M. Zammattio, S. Zanardi
`5.1 Flash Architecture: General Overview
`Flash Architecture Scenario
`5.1.1 (cid:9)
`5.1.2 (cid:9) NOR Cell Operation and Array Organization
`5.1.3 (cid:9)
`Flash Memory User Interface
`5.1.4 (cid:9)
`Flash Memory Operations: Overview
`5.1.4.1 (cid:9)
`Read Path Building Blocks Description
`Program Path Building Blocks Description
`5.1.4.2 (cid:9)
`5.1.4.3 (cid:9)
`Erase Path Building Blocks Description
`5.2 Read Path: Decoding
`5.2.1 Predecoding
`5.2.2 Row Decoder
`5.2.3 Column Decoder
`5.2.4 Hierarchical Decoder
`5.2.5 Low Vcc Problems
`5.2.6 Boost Concept: Continuous Boost and "One-shot" Bost
`5.2.7 A New Boost Approach: Miniboost
`5.3 Read Path: Input and Output Buffers
`Input Buffer
`5.3.1
`5.3.2 Output Buffer
`5.3.3 Noise Issues
`5.3.4 High Voltage Tolerance
`5.4 Read Path: Sensing Techniques
`5.4.1 Sensing Techniques: An Overview
`5.4.2 Differential Sensing Technique
`5.4.3 Differential Sensing Technique with Offset Current
`5.4.4 Differential Semi-Parallel Sensing Technique
`5.4.5 Reading Speed-up Techniques
`5.4.6 From EPROM to Flash
`5.4.7 Reading Flash Memories with Depleted Bits
`5.4.8 Low Voltage Flash Read
`5.4.9 Reference Problems
`5.5 Program Operation Circuitry
`5.5.1 (cid:9) Cell Programming Voltages: Optimum Choice
`5.5.2 Typical Program Path
`5.5.3 Drain Voltage Regulation: (cid:9) Principles and Basic Circuits
`5.5.4 Gate Voltage Regulation Fundamentals
`5.6 Erase Operation Circuitry
`5.6.1 (cid:9) Double Supply Voltage Approach
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`EXHIBIT 1108 - PAGE 0008
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`
`Source Erase Circuitry (cid:9)
`5.6.1.1 (cid:9)
`Slow Discharge of Critical Nodes (cid:9)
`5.6.1.2 (cid:9)
`5.6.2 Single Supply Voltage Approach (cid:9)
`5.6.2.1 Charge Pumping (cid:9)
`5.6.2.2 Voltage Regulators (cid:9)
`5.6.2.3 Source Switch (cid:9)
`5.7 Control Logic and Embedded Algorithms (cid:9)
`5.7.1 Logic Architecture (cid:9)
`5.7.2 Embedded Algorithms (cid:9)
`5.7.2.1 Sequencer (Pseudo-Microcontroller) (cid:9)
`Finite State Machine (cid:9)
`5.7.2.2 (cid:9)
`5.7.3 Program Flow (cid:9)
`5.7.4 Erase Flow (cid:9)
`5.7.5 Erase Suspend - Erase Resume (cid:9)
`5.7.6 Testability Issues (cid:9)
`5.8 Redundancy and Error Correction Codes (cid:9)
`5.8.1 The Yield (cid:9)
`5.8.2 Static Redundancy (cid:9)
`5.8.3 Wafer Yield (cid:9)
`5.8.4 A Real Case (cid:9)
`5.8.5 Error Correction Codes (cid:9)
`
`6
`MULTILEVEL FLASH MEMORIES (cid:9)
`G. Torelli, M. Lanzoni. A. Manstretta, B. Ricca
`6.1 Introduction (cid:9)
`6.1.1 The Multilevel Approach (cid:9)
`6.1.2 Basic Issues for ML Storage (cid:9)
`6.2 Array Architectures for Multilevel Flash Memories (cid:9)
`6.2.1 NOR Architecture with CHE Programming (cid:9)
`6.2.2 NOR Architecture with FN Programming (cid:9)
`6.2.3 NAND Architecture (cid:9)
`6.3 Multilevel Sensing (cid:9)
`6.3.1 Signal Production and Recognition (cid:9)
`6.3.2 Sensing Schemes (cid:9)
`6.4 Multilevel Programming (cid:9)
`6.4.1 Program-and-Verify Approaches (cid:9)
`6.4.2 Self-Controlled Approaches (cid:9)
`6.5 Conclusions (cid:9)
`
`References
`
`7
`FLASH MEMORY RELIABILITY (cid:9)
`P. Cappelletti, A. Modelli
`7.1 Introduction (cid:9)
`7.2 Memory Array Vt Distributions and Tunnel Oxide "Defects" (cid:9)
`7.3 Main Yield and Reliability Issues (cid:9)
`
`Contents (cid:9)
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`ix
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`7.3.1 Over-Erasing (cid:9)
`7.3.2 Program Disturbs (cid:9)
`7.3.3 Read Disturb (cid:9)
`7.3.4 Program/Erase Endurance (cid:9)
`7.3.5 Data Retention (cid:9)
`7.4 Testing for Reliability (cid:9)
`7.5 Failure Modes Induced by Program/Erase Cycling (cid:9)
`7.5.1 Memory Cell Intrinsic Endurance (cid:9)
`7.5.2 The Behavior of Tail Bits (cid:9)
`7.5.3 Single Bit Failure Mechanisms (cid:9)
`7.5.3.1 The Erratic Erase Phenomenon (cid:9)
`7.5.3.2 Single Bit Data Loss after Program/Erase Cycling (cid:9)
`7.5.3.3 Gain Degradation (cid:9)
`7.6 Multilevel Storage Reliability (cid:9)
`7.7 Conclusion (cid:9)
`
`References (cid:9)
`
`8
`FLASH MEMORY TESTING (cid:9)
`G. Gasagrande
`8.1 Introduction (cid:9)
`8.1.1 Impact of Testing on Product Cost (cid:9)
`8.1.2 Impact on Product Life Cycle (cid:9)
`8.1.3 Objectives of Production Testing (cid:9)
`8.1.4 Testing Versus Quality and Reliability (cid:9)
`8.2 Flash Testing Aspects (cid:9)
`8.2.1 Flash Functional Model (cid:9)
`8.2.2 Oxide Stress in a Flash (cid:9)
`8.2.3 Flash Testing Aspects (cid:9)
`8.2.4 Conceptual Test Flow (cid:9)
`8.3 Flash Testability Tools (cid:9)
`8.3.1 Focus on Cell and Technology (cid:9)
`8.3.1.1 Direct Memory Access (cid:9)
`8.3.1.2 Vt Measurement (cid:9)
`8.3.1.3 Stress Modes (cid:9)
`8.3.1.4 Depletion/Low-Vt Test (cid:9)
`8.3.2 Focus on Test Productivity (cid:9)
`8.3.3 Focus on Design (cid:9)
`8.3.4 Flash Design Testability: an Example (cid:9)
`8.4 Fault Repairing (cid:9)
`8.4.1 Error Correction (cid:9)
`8.4.2 Redundancy (cid:9)
`8.4.2.1 (cid:9) Diagnosis and Repairing (cid:9)
`8.4.2.2 Testability Tools for Redundancy (cid:9)
`8.5 Production Testing (cid:9)
`8.5.1 DC Tests (cid:9)
`
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`
`8.5.2 (cid:9)
`Functional Testing
`8.5.3 (cid:9) AC Read/Command Interface
`8.5.4 (cid:9) Erase/Program Performance; Endurance
`8.5.5 (cid:9)
`Reliability
`8.6 (cid:9) Test Productivity
`8.6.1 (cid:9)
`Impact on Tester Structure
`8.6.2 (cid:9)
`Parallel Testing Final Test
`8.6.3 (cid:9)
`Parallel Testing at EWS
`Product Characterization
`8.7 (cid:9)
`8.8 (cid:9) Conclusions
`
`References
`
`Contents
`
`xi
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`9
`FLASH MEMORIES: MARKET, MARKETING AND ECONOMIC CHALLENGES
`481
`B. Beverina, P. Berge, with contributions by C. Kunkel, G. Moy, A. Damiano, R. Ferrara, A. Re
`9.1 (cid:9)
`Introduction
`482
`9.2 (cid:9) Market Segmentations
`483
`9.2.1 (cid:9) Application Segments and Subsegments
`485
`9.2.2 (cid:9) Technology, Performances and Applications
`488
`Segment Dynamics
`9.2.3 (cid:9)
`492
`9.2.4 (cid:9) Commodity or Non-Commodity?
`493
`9.3 (cid:9) Customer/Supplier Relationship
`495
`9.4 (cid:9) The Development of the Flash Market
`496
`9.5 (cid:9)
`Flash Memory and the "Economy"
`499
`9.6 (cid:9) Applications More in Detail
`500
`9.6.1 (cid:9)
`Survey
`500
`9.6.2 (cid:9)
`Flash in Mobile Phones and Terminals
`503
`9.6.3 (cid:9)
`Flash in the BIOS
`508
`9.6.4 (cid:9)
`Flash in Automotive
`515
`9.7 (cid:9) Conclusions
`525
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`References
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`526
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`APPLE INC.
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`

`
`1 FLASH MEMORIES:
`
`AN OVERVIEW
`Piero Olivo', Enrico Zanoni2
`
`1 Dipartimento di Ingegneria, University di Ferrara
`
`Via Saragat 1, 44100 Ferrara, Italy
`
`olivo@ing.unife.it
`
`2 Dipartimento di Elettronica e Informatica, University di Padova
`
`Via Gradenigo 6/A, 35131 Padova, Italy
`
`zanoni@dei.unipd.it
`
`1.1 ROLE OF NON VOLATILE MEMORIES IN MICROELECTRONIC
`SYSTEMS AND IN SEMICONDUCTOR MARKET
`
`Solid-state memory devices which retain information once the power supply is
`switched off are called "nonvolatile" memories. For instance, using standard
`digital technology, a nonvolatile memory can be implemented by writing perma-.
`nently the data in the memory array during manufacturing (mask-programmed
`Read Only Memories, ROM). As an alternative, the user can program the in-
`formation by blowing fusible links or antifuses, thus changing permanently the
`cell content (i.e. obtaining a Programmable ROM or PROM). In both cases,
`the memory array can not be erased, thus making these solutions viable only
`for a limited number of applications.
`In the Course of the years, several technological solutions have been devel-
`oped, which have led to the availability of non-volatile memories which can
`be electrically written and erased. Erasable Programmable Read Only Mem-
`ories (EPROM) can be electrically programmed, but have to be removed and
`exposed to ultra-violet (UV) radiation for about 20 minutes in order to be
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0012
`
`

`
`2
`
`FLASH MEMORIES
`
`erased. Electrically Erasable Programmable ROMs (EEPROM) are electri-
`cally erasable and programmable in-system, byte by byte, but use larger areas
`than EPROMs, and have therefore higher costs and lower densities.
`System designers have long dreamt of a non volatile memory which could
`be electrically erased and programmed in-system, offering at the same time
`very high-density and low cost-per-bit, random access, bit alterability, short
`read/write times and cycle times, excellent reliability. In most of the current
`system applications, these features should be also combined with low power
`consumption and single, low-voltage, power supply operation. If available, a
`solid-state memory technology having these characteristics would not only be-
`come dominant in the nonvolatile memory market, but could also make possible
`an unprecedented design flexibility, replacing all other kinds of memory in many
`applications. At the moment, this "ideal" memory chip has still to be invented.
`The Flash memory technology has many of the characteristics of the "ideal"
`memory concept and is consequently considered as a driver for the semicon-
`ductor industry in the next decade. In 1996 it was forecasted that nonvolatile
`memories are going to be 12% of the worldwide memory market by the year
`2000; Flash memories will occupy 50% of this nonvolatile memory market.
`Currently (1998), the Flash memory market is approximately $2.5B [1].
`Flash memories are non volatile memories in which a single cell can be
`electrically programmed and a large number of cells — called a block, sector or
`page — are electrically erasable at the same time. The word "flash" itself is
`related to the fact that since the whole memory can be erased at once, erase
`times can be very fast. Flash technology combines the high density of the UV
`EPROM (it has basically a single transistor cell like EPROMs) with electrical
`in-system erasability of EEPROMs.
`There are two major applications for Flash memories that should be pointed
`out. One is the possibility of nonvolatile memory integration in logic systems
`— mainly, but not only, microprocessors — to allow software updates, store
`identification codes, reconfigure the system on the field, or simply have smart
`cards. The other application is to create storing elements, like memory boards
`or solid-state hard disks, made by Flash memory arrays which are configured
`to create large-size memories to compete with miniaturized hard disks. Flash
`solid-state disks are very useful for portable applications, since they have small
`dimensions, low power consumption, and no mobile parts, therefore being more
`robust.
`Flash memories also combine the capability of nonvolatile storage with an
`access time comparable to Dynamic Random Access Memories (DRAM), which
`allows direct execution of microcodes. Many programs can be stored in Flash
`chips, without being continuously loaded and unloaded from the hard disk, and
`directly executed. Moreover, the realization of new generations of Flash memo-
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0013
`
`

`
`FLASH MEMORIES: AN OVERVIEW
`
`3
`
`ries that can be erased by blocks of different sizes, emulating EEPROMs in some
`applications, and with a single power supply, widens the field of applicability
`for Flash memories and encourages new uses. Besides voice recorders, answer-
`ing machines and portable audio guides, Flash memories find wide applications
`in personal computers and peripherals, automotive engine control units, digi-
`tal cordless telephones, and in emerging applications, such as personal digital
`assistants (PDAs), digital set-top boxes, digital still cameras, portable medi-
`cal diagnostic systems and many others, also taking advantage of the recent
`possibility of storing more bits on a single cell (in "multilevel" Flash memories).
`In this introduction the reader will find a description of the basic concepts
`and characteristics which have led to the development of Flash memories. The
`basic cell structures, device physics, memory chip architecture, reliability and
`testing issues of Flash memories will be analyzed in details in the following
`Chapters.
`
`1.2. EVOLUTION OF NON-VOLATILE MEMORIES
`Two are the parameters describing how "good" and reliable a nonvolatile mem-
`ory cell is: endurance (capability of maintaining the stored information after
`erase/program/read cycling) and retention (capability of keeping the stored
`information in time). The need of information modification, however, always
`contrasts with that of a good data retention; cells with different characteristics
`have different applications according to the relevance of some device functional
`parameters (absorbed power, programming/erasing speed and selectivity, ca-
`pacity...).
`To have a memory cell which can commute from one state to the other,
`and which can store the information independently of external conditions, the
`storing element needs to be a device whose conductivity can be changed in a
`non-destructive way.
`One solution is to have a transistor with the threshold voltage which can
`change repetitively from a high to a low state, corresponding to the two states
`of the memory cell. Following the P1005 IEEE Draft Standard for Definitions,
`Symbols and Characterization of Floating Gate Memory Arrays [2], the low-
`and the high-threshold states in Flash memories are generally called as "erased"
`and "programmed", respectively. It must be noticed, however, that this stan-
`dard definition is not followed for all kinds of cells; for some implementations,
`it is common practice to distinguish the "program" and "erase" operations on
`the basis of the memory array organization; as a consequence, "programmed"
`does not always correspond to "high threshold" . Deviations from the standard
`definitions will be pointed out in Chapter 3, which describes advanced Flash
`memory cells.
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0014
`
`

`
`4 FLASH MEMORIES
`
`The threshold voltage VT of a MOS transistor can be written as:
`
`VT = K — QICox
`
`(1.1 )
`
`where K is a constant that depends on the gate and substrate material, on
`the channel doping, and gate oxide thickness, Q is the charge weighted with
`respect to its position in the gate oxide, and Cox is the gate oxide capacitance.
`As can be seen, the threshold voltage of a MOS memory cell can be altered by
`changing the amount of charge present between the gate and the channel, i.e.
`by changing Q/Cox. Two are the most common solutions used to store charge:
`1. in traps which are present in the insulator or at the interface between
`two dielectric materials. The most commonly used interface is the silicon
`oxide/nitride interface. Devices obtained in this way are called MNOS
`(Metal-Nitride-Oxide-Silicon) cells;
`
`2. in a conductive material layer between the gate and the channel and com-
`pletely surrounded by insulator; this is the "floating gate" (FG) device.
`Because of their lower endurance and retention, MNOS devices are used only
`in specific applications (such as in military, thanks to their radiation hardness).
`Their modern counterpart, the SONOS (Silicon - Oxide - Nitride - Oxide -
`Silicon) nonvolatile memory technology, is still based on electron trapping in the
`nitride layer, but exploits the achievement of a better control of the processing
`of the ONO (Oxide-Nitride-Oxide) layer. By using a relatively thin (5-10 nm)
`dielectric layer low programming voltages (5 to 10 V) can be achieved. Despite
`these improvements, however, nonvolatile memories based on charge trapping
`are still a very low fraction of the total nonvolatile memory production.
`Floating gate devices, on the contrary, are at the basis of every modern
`nonvolatile memory, and are used in particular for Flash applications.
`
`1.3 THE FLOATING GATE DEVICE
`
`The schematic cross section of a generic floating gate device is shown in Fig. 1.1a:
`the upper gate is the control gate, while the lower one, completely surrounded
`by dielectric, is the floating gate. The basic concepts and the functionality of
`a FG device can be easily understood by determining the relationship between
`the FG potential, that physically 'controls the channel conductivity, and the
`control gate potential, controlled by external circuitry. This can be done by
`using the simple electrical model of Fig. 1.1b, where Cc, CS, CD and CB are
`the capacitance between FG and control gate, source, drain and bulk regions,
`respectively. The FG potential (VF) is:
`
`CB
`Cc (cid:9)
`Cs ,
`
`1/F = —vc + — (cid:9)s + — vp + — vB + (cid:9)
`CT CT
`CT (cid:9)
`CT (cid:9)
`
`CT
`
`(1.2 )
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0015
`
`(cid:9)
`(cid:9)
`

`
`FLASH MEMORIES: AN OVERVIEW
`
`5
`
`Interpoly Oxide
`
`Control Gate
`
`Gate Oxide
`
`C
`
`Floating Gate
`
`CQ
`
`Cc (cid:9)
`
`
`
`FG
`
`Cs
`
`CB
`
`b)
`
`p
`
`b B
`
`a)
`
`Figure 1.1 a) Schematic cross section of a generic floating gate device; b) electrical model
`of a floating gate device (junction capacitances are neglected).
`
`where Vc, VS, VD, and VB are the control gate, drain, source and bulk poten-
`tials, respectively; Q is the charge within the FG, while CT = CC+CS+CD+CB
`is the total capacitance.
`Eq. (1.2) shows that the FG potential does not depend on the control gate
`voltage only, but also on source, drain and bulk potentials. If the source and
`bulk are both grounded and all potentials are referred to the source, (1.2) can
`be rearranged as
`
`CC (cid:9)
`VFS = CT VCS (cid:9)
`
`r7 (cid:9)
`Q
`CD
`•
`VDS DS (cid:9)
`
`T CT
`
`(1.3 )
`
`By defining ac = CC/CT as the "coupling factor" and f = CD/CC, (1.3 )
`can be written as
`
`, Q
`VFS = cec (Vas + fVDS -r ) •
`CC
`
`(1.4 )
`
`The characteristics of a FG device depend on the threshold voltage, that
`is the potential (VTFS ) that must be applied to the FG (with VDS = 0) to
`reach the inversion of the surface population. Since the floating gate cannot be
`accessed, VTFS is applied to the floating gate when a suitable voltage (V-Tcs
`to be derived from (1.4 ), is applied to the control gate:
`
`1 ,
`VTcs = — VTE's
`
`Q
`CC
`
`(1.5 )
`
`",•24.tt-
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0016
`
`(cid:9)
`

`
`6
`
`FLASH MEMORIES
`
`erased (cid:9)
`Q = 0 (cid:9)
`
`programmed
`Q 0
`
`IDS
`
`-Q/C c
`
`V (cid:9)
`-FE (cid:9)
`
`V
`TP (cid:9)
`
`VCS
`
`a)
`
`Sensing Vcs
`
`b)
`
`Figure 1.2 a) I-V trans-characteristics of a FG device for two different values of charge
`stored within the FG (Q = 0, and Q < 0), denoting two different states, respectively:
`erased and programmed; b) reading operation of a FG device: a suitable control gate voltage
`(VTE < VCS < VTp ) is applied to the device to determine whether it is conductive or not.
`
`While VT„ depends only on the device technology (and on the possible
`charge trapped within the gate oxide), Vrc E varies with the charge within the
`FG and this is the key result explaining the success of the FG device as the
`basic cell for nonvolatile memories applications. Fig. 1.2a shows two different
`I-V trans-characteristics obtained by modifying the FG charge. In particular,
`by choosing a suitable "threshold shift" (IQ/Cc 1), it is possible to define two
`different (and separate) device states: erased for Q = 0, and programmed for
`Q < 0. The corresponding threshold voltages applied to the control gate are
`
`VTG, s
`
`VTG, s
`
`1 T
`- V TF s = VTE
`ac
`1 T 7
`— vr,s — = vrp ,
`ac (cid:9)
`cc
`
`(1.6 )
`
`(1.7 )
`
`and they are denoted as "erased threshold" and "programmed threshold", re-
`spectively.
`The device state can be read by applying an appropriate "sensing" voltage
`to the control gate, as shown in Fig. 1.2b. When the FG device I-V curve
`corresponds to curve a (Q = 0), then Vcs > VTE and the device is ON; when
`the device has been previously programmed (curve b), Vcs < Vrp and the
`device is OFF.
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0017
`
`(cid:9)
`(cid:9)
`

`
`FLASH MEMORIES: AN OVERVIEW
`
`7
`
`L4 CHARGE INJECTION MECHANISMS
`
`There are many solutions used to transfer electric charge from and into the
`floating gate. For both erase and program, the problem is making the charge
`pass through a layer of insulating material. The different physical phenomena
`which contribute to determine the behavior of a nonvolatile memory cell are
`analyzed in depth in Chapter 4.
`The hot-electron injection and the Fowler-Nordheim tunneling mechanisms
`are generally used to write Flash memories. In the former, a lateral electric
`field (between source and drain) "heats" the electrons, and a transversal electric
`field (between channel and control gate) promotes the injection of the carriers
`through the oxide. The latter starts when there is a high electric field through
`a thin oxide. In these conditions, the energy band diagram of the oxide region
`is very steep; therefore, there is a high probability of electrons passing through
`the energy barrier itself.
`Hot electrons and tunneling effects have been extensively studied since they
`can induce reliability problems in scaled MOS transistors. In nonvolatile mem-
`ory cells, the very same mechanisms are controlled and exploited to become
`efficient program/erase mechanisms.
`
`1.5 ERASABLE PROGRAMMABLE READ ONLY MEMORIES
`
`1.5.1 The Floating gate Avalanche-injection MOS transistor (FAMOS) Cell
`
`In 1967 D. Khang and S. M. Sze at Bell Laboratories [3] proposed a MOS-
`based nonvolatile memory cell based on a floating gate in a metal-insulator-
`metal-insulator-semiconductor structure. The lower insulator had to be thin
`enough (< 5 nm) to allow quantum-mechanical tunneling of electrons from the
`substrate to the floating gate and viceversa. At that time, however, it was
`almost impossible to deposit such a thin oxide layer without introducing fatal
`defects.
`As a consequence, the tunneling mechanism was initially abandoned, and
`the first operating floating gate device, which adopted a fairly thick oxide layer,
`was developed at Intel in 1971 by Frohman-Bentchowsky [4]. This cell had no
`control gate, and was programmed by applying a highly-negative voltage at the
`drain, thus avalanching the drain/substrate junction, and creating a plasma of
`highly energetic electrons underneath the gate. The electrons were injected
`into the oxide and reached the floating gate, thus programming the cell.
`Due to the absence of a control gate, however, the operation was extremely
`inefficient, and enormous voltages were needed. In order to inject electrons in
`the floating gate, p-channel devices had to be used. Erasure was obtained by
`providing externally the energy required by electrons to be re-emitted from the
`
`APPLE INC.
`EXHIBIT 1108 - PAGE 0018
`
`

`
`eqPiC4411.
`
`8
`
`FLASH MEMORIES
`
`floating gate. This was accomplished by exposing the cell to ultra-violet (UV)
`radiation.
`
`1.5.2 The basic Erasable Programmable Read Only Memory (EPROM)
`
`The FAMOS concept eventually evolved into a double polysilicon stacked gate
`n-channel cell, as schematically shown in Fig. 1.1, which constitutes the basic
`cell of an EPROM.
`This cell is programmed by injection of channel hot-electrons into the float-
`ing gate and is erased using UV radiation. The programming consists in raising
`both the control gate (wordline) and the drain (bitline) to high voltages, typi-
`cally 12 V. There are several relevant features:
`
`1. hot electron programming is a very inefficient process, which requires
`both high voltage and high current. The stacked gate EPROM can not
`work with a single, low voltage supply;
`
`2. only the cell which has both the control gate and the drain at high voltage
`is programmed: the operation is bit-selective. The same applies to the
`reading operation;
`
`3. both the bit-selective hot-electron programming mechanism and the UV
`erasure process, which is obviously carried out on the whole array, are
`self-limiting. In particular, by UV erasure one can not indefinitely re-
`move electrons from the floating gate, thus obtaining a cell with a too
`low threshold, i.e. an overerased cell. An over-erased cell is a cell with ex-
`cessive source-drain leakage current when unselected, due to the threshold
`of the cell itself being lower than the applied control gate voltage.
`
`Since the programming and reading operations are automatically bit-selective,
`while erasure is carried out on the whole chip, the EPROM does not require
`a select transistor or a split-gate structure to carry out bit selection, and can
`be implemented as a one-transistor memory cell. Its T-shaped cell is therefore
`extremely co