ATTORNEY DOCKET NO.: 21584-112006
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SMART MODULAR TECHNOLOGIES INC.
`
`Petitioner
`
`v.
`
`JAMES B. GOODMAN
`
`Patent Owner
`
`
`
`Case No. TBD
`
`Patent 6,243,315
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF CLAIMS 1, 5, 10, AND 16 OF U.S. PATENT NO. 6,243,315
`
`
`
`VIA PRPS
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`Michael F. Heafey (Lead Counsel)
`Registration No. 38,178
`King & Spalding, LLP
`601 South California Avenue, Suite 100
`Palo Alto, California 94304
`(650) 422-6700
`
`
`
`
`

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`ATTORNEY DOCKET NO.: 21584-112006
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`TABLE OF CONTENTS
`
`
`I.  MANDATORY NOTICES – 37 C.F.R. § 42.8 .......................................................................... 1 
`Fees ............................................................................................................................... 1 
`A. 
`Real Party-In-Interest ..................................................................................................... 1 
`B. 
`Identification Of Challenge ............................................................................................ 1 
`C. 
`Standing ......................................................................................................................... 1 
`D. 
`Related Matters - 37 C.F.R. § 42.8(b)(2): ......................................................................... 1 
`E. 
`Lead, Back-Up Counsel, And Service Information ......................................................... 3 
`F. 
`III. STANDARD OF REVIEW ...................................................................................................... 4 
`IV. STATEMENT OF THE PRECISE RELIEF REQUESTED 37 C.F.R. §§ 42.104(B)(1) & (2) . 4 
`V.  STATEMENT OF THE REASONS FOR THE RELIEF REQUESTED ............................... 5 
`Description Of The ‘315 Patent ..................................................................................... 5 
`A. 
`The Alleged Invention ......................................................................................... 6 
`1. 
`Description Of The Prior Art ......................................................................................... 8 
`U.S. Patent No. 5,600,605 (“Schaefer”) ................................................................ 9 
`1. 
`U.S. Patent No. 5,793,776 (“Qureshi”) .............................................................. 11 
`2. 
`U.S. Patent No. 5,204,840 (“Mazur”) ................................................................. 12 
`3. 
`Claim Construction 37 C.F.R. § 42.104(b)(3) ................................................................ 12 
`“A Memory System For Use In A Computer System” (Claims 1 & 10) .............. 14 
`1. 
`“Plurality Of Volatile Solid State Memory Devices” (Claims 1 & 10) ................. 15 
`2. 
`“Address Lines And Control Lines” (Claims 1 & 10) ......................................... 16 
`3. 
`4. 
`“A Control Device For Selectively Electrically Isolating [The] Memory Devices”
`(Claim 1) & “A Control Device . . . For Selectively Electrically Isolating [The]
`Memory Devices” (Claim 10) ............................................................................. 17 
`“A low power mode for [the] memory system” (Claims 1 & 10) ........................ 18 
`5. 
`Legal Standard For Obviousness .................................................................................. 19 
`Scope And Content Of The Prior Art ................................................................ 20 
`1. 
`Differences Between The Prior Art And The Patent Claims .............................. 21 
`2. 
`The Level Of Ordinary Skill In The Art ............................................................. 24 
`3. 
`Motivation To Combine References .................................................................. 25 
`4. 
`5. 
`The Predictability Of The Field, Skill Of The POSITA, & The
`Ordinary/Expected Functions ........................................................................... 29 
`The Challenged Claims 37 C.F.R. §§ 42.104(b)(1) & (4) ................................................ 31 
`Detailed Discussion Of The Challenged Claims ........................................................... 47 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`F. 
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`ATTORNEY DOCKET NO.: 21584-112006
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`ATTORNEY DOCKET NO.: 21584-112006
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`Independent Claim 1 Of The ‘315 Patent .......................................................... 48 
`1. 
`Independent Claim 1 Of The ‘315 Patent ........................................................ .. 48
`1.
`Independent Claim 10 Of The ‘315 Patent ........................................................ 54 
`2. 
`Independent Claim 10 Of The ‘315 Patent ...................................................... .. 54
`2.
`Dependent Claims 5 And 16 Of The ‘315 Patent ............................................... 59 
`3. 
`Dependent Claims 5 And 16 Of The ‘315 Patent ............................................. .. 59
`3.
`VI. CONCLUSION ....................................................................................................................... 60 
`VI. CONCLUSION ..................................................................................................................... .. 60
`
`
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`ii
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`ATTORNEY DOCKET NO.: 21584-112006
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`
`TABLE OF AUTHORITIES
`
`Cases
`In re Am. Acad. Of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004) ................... 13, 15
`SAP America, Inc. v. Versata Dev. Group, Inc. , CBM2012-00001 ....................................... 14
`Graham v. John Deere Co., 383 U.S. 1, 17 (1966) ............................................................ 19, 20
`KSR Int’l Co. v. Teleflex Inc., 127 S.Ct. 1727, 1741 (2007) ............................... 19, 23, 27, 29
`Pfizer, Inc. v. Apotex, Inc., 480 F. 3d 1348, 1363 (Fed. Cir. 2007) ...................................... 20
`In re Royka, 490 F.2d 981, 180 USPQ 580 (CCPA 1974) ............................. 19, 54, 59, 60
`Rothman v. Target Corp., 556 F.3d 1310, 1319–20 (Fed. Cir. 2009) .................................. 20
`X2Y Attenuators, LLC v. Int’l Trade Comm’n, 757 F.3d 1358, 1363 (Fed. Cir. 2014) ....... 31
`Ultradent Prods., Inc. v. Life-Like Cosmetics, Inc., 127 F.3d 1065, 1069 (Fed. Cir. 1997) .... 32
`
`Statutes
`35 U.S.C. § 314(a) ...................................................................................................................... 4
`35 U.S.C. § 103(a) ...................................................................................................................... 5
`
`Rules
`MPEP § 2141 Sec. I, ¶ 2 ..................................................................................... 20, 23, 27, 29
`75 F.R. 53650, Examination Guidelines Update, September 2010 .................... 20, 23, 27, 29
`
`Regulations
`37 C.F.R. § 42.8 .......................................................................................................................... 1
`37 C.F.R. § 42.104(a) ................................................................................................................ 1
`37 C.F.R. § 42.100(b) .............................................................................................................. 13
`
`
`
`
`
`iii
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`

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`
`
`Exhibit
`Number
`1001
`1002
`1003
`
`1004
`1005
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`1013
`1014
`
`1015
`
`1016
`
`1017
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`ATTORNEY DOCKET NO.: 21584-112006
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`TABLE OF EXHIBITS
`
`Exhibit
`
`U.S. Patent No. 6,243,315
`Declaration of Nader Bagherzadeh
`Plaintiff’s Amended Infringement Chart For U.S. Patent No. 6,243,315
`From Case No. 4:14-cv-01380 GHM (S.D. Tex.)
`U.S. Patent No. 5,600,605 to Schaefer
`U.S. Patent No. 5,793,776 to Qureshi et al.
`U.S. Patent No. 5,204,840 to Mazur
`JEDEC DDR SDRAM Specification JESD79 R1, June 2000
`JEDEC DDR2 SDRAM Specification JESD79-2F, November 2009
`Micron MT48LC2M8S1(S) Datasheet, April 1994
`Micron MT48LC2M8S1(S) Specification Sheet, June 1993
`Dkt. 7 From Case No. 4:14-cv-01380 GHM (S.D. Tex.)
`JEDEC DDR3 SDRAM Specification JESD79-3E, July 2010
`U.S. Patent No. 4,005,395 to Fosler, Jr. et al.
`Reengineering the Curriculum: Design and Analysis of a New Undergraduate
`Electrical and Computer Engineering Degree at Carnegie Mellon University,
`Director et al., IEEE 1995
`Plaintiff’s Disclosure Of Asserted Claims And Preliminary Infringement
`Contentions From Case No. 4:14-cv-01380 GHM (S.D. Tex.)
`Dkt. 18 - Second Amended Complaint From Case No. 4:14-cv-01380
`GHM (S.D. Tex.)
`Plaintiff’s Second Amended Infringement Chart For U.S. Patent No.
`6,243,315 From Case No. 4:14-cv-01380 GHM (S.D. Tex.)
`
`iv
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`

`
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`I. MANDATORY NOTICES – 37 C.F.R. § 42.8
`
`ATTORNEY DOCKET NO.: 21584-112006
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`A. Fees
`
`Please charge Deposit Account No. 50-4616, Order No. 21584-112006.
`
`B. Real Party-In-Interest
`
`SMART Modular Technologies, Inc.
`
`39870 Eureka Drive, Newark, California 94560.
`
`C. Identification Of Challenge
`
`Petitioner requests inter partes review of Claims 1, 5, 10, and 16 of U.S. Patent
`
`No. 6,243,315.
`
`D. Standing
`
`Petitioner certifies that the ‘315 patent is available for inter partes review and
`
`Petitioner is not barred or estopped from petitioning for inter partes review. 37
`
`C.F.R. § 42.104(a).
`
`Patent Owner is alleging infringement of the ‘315 patent by Petitioner in
`
`Case No. 4:14-cv-01380 currently pending in the Southern District of Texas.
`
`Patent Owner served Petitioner with the complaint on August 7, 2014. Ex. 1011
`
`at 1. Petitioner is entitled to request inter partes review under 35 U.S.C. § 315(b)
`
`because it is filing this petition within one year of the service date.
`
`E. Related Matters - 37 C.F.R. § 42.8(b)(2):
`
`Petitioner identifies Case No. 4:14-cv-01380 pending in the Southern
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`1
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`ATTORNEY DOCKET NO.: 21584-112006
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`District of Texas as a patent infringement matter involving the ‘315 patent that
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`may be affected by a decision in this proceeding. Petitioner is not aware of any
`
`other active matter that may be affected by a decision in this proceeding, but
`
`identifies the following litigations involving allegations of infringement of the ‘315
`
`patent, all of which have been terminated as of the filing of this petition:
`
`No.
`
`Case
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`Goodman v. Alliance Memory, Inc., Southern District of Texas (4:13-cv-02106)
`
`Goodman v. Intel Corporation; Elpida Memory, Inc.; Emerging Memory and Logic
`
`Solutions Inc.; Fidelix Co., Ltd.; Integrated Silicon Solution, Inc.; & Eon Silicon
`
`Solutions Inc., Northern District of California (4:11-cv-02607)
`
`Goodman v. Chiplus Semiconductor Corp; & Premier Components, Inc., Eastern
`
`District of New York (2:11-cv-02982)
`
`Goodman v. Emerging Memory and Logic Solutions, Inc.; Fidelis Co., Ltd.; Integrated
`
`Silicon Solution, Inc.; Winbond Electronics Corporation; & Elpida Memory Inc.,
`
`Northern District of California (5:10-cv-03738)
`
`Goodman v. Numonyx B.V., Northern District of California (3:09-cv-04243)
`
`Goodman v. Fujitsu Limited, Southern District of New York (1:08-cv-10773)
`
`Goodman v. Spansion Inc., Northern District of California (3:07-cv-01346)
`
`Goodman v. Nanya Technology Corporation, Northern District of California
`
`(3:13-cv-4415)
`
`2
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`

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`
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`9
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`ATTORNEY DOCKET NO.: 21584-112006
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`Goodman v. ProMOS Technologies Inc., Northern District of California (4:12-
`
`cv-02069)
`
`10
`
`Goodman v. Etron Technology America, Inc., Northern District of California
`
`(4:08-cv-00995)
`
`11
`
`Goodman v. Hynix Semiconductor America Inc., Southern District of Texas
`
`(4:06-cv-01098)
`
`12
`
`Goodman v. Nanya Technology Corporation, U.S.A., Northern District of
`
`California (3:13-cv-03397)
`
`13
`
`Goodman v. ON Semiconductor Corp., Southern District of Texas (4:13-cv-
`
`01542)
`
`14
`
`Goodman v. Corsair components Inc., Southern District of Texas (4:14-cv-
`
`01381)
`
`15
`
`Goodman v. Atmel Corporation, Northern District California (3:07-cv-03113) -
`
`Status: Terminated on February 12, 2008;
`
`16
`
`Goodman v. NanoAmp Solutions, Inc., Northern District of California (3:05-
`
`cv-05313)
`
`17
`
`Goodman v. Patriot Memory LLC, Southern District of Texas (4:14-cv-01360)
`
`F. Lead, Back-Up Counsel, And Service Information
`
`Lead counsel is:
`
`Michael F. Heafey
`
`Back-up counsel is:
`
`Sanjiva K. Reddy
`
`3
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`ATTORNEY DOCKET NO.: 21584-112006
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`Registration No. 38,178;
`
`Registration No. 70,816;
`
`King & Spalding LLP,
`
`King & Spalding LLP,
`
`601 South California Avenue,
`
`1185 Avenue of the Americas,
`
`Palo Alto, California 94304
`
`New York, New York 10036
`
`(650) 422-6719 (telephone)
`
`(212) 556-2157 (telephone)
`
`(650 422-6800 (facsimile)
`
`(212) 556-2222(facsimile)
`
`mheafey@kslaw.com (email)
`
`sreddy@kslaw.com (email)
`
`Petitioner also requests service via emails to the email addresses above, with a
`
`courtesy copy to patentmailnyc@kslaw.com.
`
`III. STANDARD OF REVIEW
`
`A petition for an inter partes review must show “that there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least one of the claims
`
`challenged in the petition.” See 35 U.S.C. § 314(a). The challenged claims are obvious
`
`in view of the prior art and it would have been well-known to a person of skill in the
`
`art to arrive at the claimed system of the ‘315 patent.
`
`IV. STATEMENT OF THE PRECISE RELIEF REQUESTED 37 C.F.R. §§
`42.104(B)(1) & (2)
`
`Petitioner requests that Claims 1, 5, 10, and 16 of the ‘315 patent be canceled.
`
`4
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`

`
`
`The grounds1 are supported by the Declaration of Nader Bagherzadeh (Ex. 1002 ).
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`ATTORNEY DOCKET NO.: 21584-112006
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`Ground 1: Claims 1 and 5 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over U.S. Patent No. 5,600,605 to Schaefer (Ex. 1004, “Schaefer”) in view of U.S.
`
`Patent No. 5,793,776 to Qureshi et al. (Ex. 1005, “Qureshi”).
`
`Ground 2: Claims 10 and 16 are unpatentable under 35 U.S.C. § 103(a) as
`
`obvious over Schaefer, in view of Qureshi, and further in view of U.S. Patent No.
`
`5,204,840 to Mazur (Ex. 1006, “Mazur”).
`
`The references and their combinations were not considered during prosecution
`
`of the ‘315 patent. See, Ex. 1001, ‘315 Patent, 1: References Cited.
`
`V. STATEMENT OF THE REASONS FOR THE RELIEF REQUESTED
`A. Description Of The ‘315 Patent
`The ‘315 patent (Ex. 1001), issued to James B. Goodman, has 2 independent
`
`claims and 18 dependent claims, all of which are directed to a volatile memory system
`
`with data retention capability during low power situations. The ‘315 patent issued
`
`from application number 09/477,920, filed on December 31, 1999, which is also its
`
`earliest effective filing date. Patent Owner has confirmed that no earlier priority date
`
`is being asserted. Ex. 1015, 1:(e).
`
`
`1 The ‘315 patent issued on June 5, 2001 from an application filed on December 31,
`
`1999, prior to the America Invents Act (“AIA”). Accordingly, Petitioner uses pre-
`
`AIA statutory framework in this Petition. 35 U.S.C. § 100.
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`5
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`ATTORNEY DOCKET NO.: 21584-112006
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`1.
`The abstract of the ‘315 patent states that it pertains to “a plurality of volatile
`
`The Alleged Invention
`
`solid state memory devices that retain information when an electrical power source is
`
`applied to the memory devices within a predetermined voltage range[.]” ‘315 patent,
`
`Abstract.
`
`Typically, volatile memory is volatile because it can only “retain information as
`
`long as a voltage is applied.” Id., 1:30-31. “Whenever electrical power is removed
`
`from the devices, the memory contents of the device [are] lost and irretrievable.” Id.,
`
`2:56-58. The ‘315 patent states that it achieves data retention for a volatile memory
`
`system using a control device to “isolate the [address and control busses] from the
`
`memory devices” during “a power down self-refresh mode,” which “reduc[es] the
`
`power drain” and which
`
`may be supported by
`
`“backup supply source[s]”
`
`at lower power till normal
`
`power is returned. Id.,
`
`5:60-67, 6:30-37, 7:15-19,
`
`& 10:27-29.
`
`Fig. 1 of the ‘315
`
`patent is annotated to
`
`highlight four elements of Claims 1 and 10 – A: “a plurality of volatile solid state
`
`6
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`

`
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`memory devices” (element 5 of the figure); B: “a low power mode for [the] memory
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`ATTORNEY DOCKET NO.: 21584-112006
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`system [during which the] control device electrically isolates [the] memory devices”
`
`(control device 15 for electrically isolating memory devices 5 during a low power
`
`mode); C: which then “places [the] memory devices in [the] self-refresh mode;” and
`
`which then results in D: “reducing the amount of electrical energy being drawn from
`
`an electrical power supply for [the] computer system.
`
`Accordingly, Claim 1 is directed to “a memory system for use in a computer
`
`system [and including] a plurality of volatile solid state memory devices [with a] self
`
`refresh mode [and] address lines and control lines.” Id., Claim 1. Claim 1 also
`
`requires “a control device for selectively electrically isolating [the] memory devices
`
`from [the] address lines and [the] control lines,” as well as “a memory access enable
`
`control device coupled to [the] control device and to [the] control lines for
`
`determining when [the] memory system is not being access and for initiating a low
`
`power mode.” Id. It further requires that, in the low power mode, [the] control
`
`device electrically isolates [the] memory devices and places [the] memory devices in
`
`[the] self refresh mode[, thereby achieving a reduction in] the amount of electrical
`
`energy being drawn from an electrical power supply for [the] computer system.” Id.
`
`Claim 10 is similar to Claim 1, but further requires “connecting [a] second
`
`electrical power source to [the] memory devices when [the] first voltage [that is drawn
`
`from the electrical power supply for the computer system] is less than [a]
`
`predetermined voltage.” Id., Claim 10. The use of the second electrical power source
`
`7
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`
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`enables “the data in [the] memory devices [to be] preserved by [the] second electrical
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`ATTORNEY DOCKET NO.: 21584-112006
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`power source when [the] electrical power source [from the computer system] fails to
`
`maintain at least [the] predetermined voltage on [the] memory devices, and [the]
`
`memory devices are isolated from errant signals.” Id. The second electrical power
`
`source comprise a backup battery, capacitors, or photoelectric cells, which is different
`
`from the first electrical power source from the computer system. Id., 10:27-30.
`
`Claims 5 and 16 depend from Claims 1 and 10, respectively. Claims 5 and 16
`
`require that the memory devices of Claims 1 and 10 are DRAM semiconductor
`
`microchips. Id., Claims 5 & 16.
`
`B. Description Of The Prior Art
`Volatile memory devices, such as dynamic random-access memory (DRAM)
`
`and its synchronous variant subset, the SDRAM, have included low power self-refresh
`
`modes from well before filing of the ‘315 patent – at least since 1993 – as illustrated in
`
`datasheets for Micron Semiconductor Inc.’s SDRAM chip MT48LC2M8S1 (Exs. 1009
`
`and 1010). Ex. 1002 (Bagherzadeh Decl.), ¶¶ 26-27. The concept of using a backup
`
`battery supply to power DRAM in low power refresh modes was described in the
`
`prior art since May 8, 1975. Ex. 1013 (U.S. Patent No. 4,005,395 to Fosler, Jr. et. al.
`
`at 2:35-38, 4:49-56, & 5:31-35. See also Ex. 1002 (Bagherzadeh Decl.), ¶ 28. In
`
`addition to the above references, the following prior art discloses the limitations of
`
`the ‘315 patent.
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`8
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`ATTORNEY DOCKET NO.: 21584-112006
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`1.
`Schaefer (Ex. 1004) issued on February 4, 1997, and is prior art to the ‘315
`
`U.S. Patent No. 5,600,605 (“Schaefer”)
`
`patent under at least Section 102(b). Schaefer was not considered during the
`
`prosecution of the ‘315 patent. See, ‘315 patent (Ex. 1001), 1: References Cited.
`
`Schaefer is assigned to Micron Technology and incorporates the functional
`
`specification of Micron’s MT48LC2M8S1 SDRAM chip by reference. Ex. 1004
`
`(Schaefer), 3:3-6. Schaefer explains that a low power self-refresh mode is in the
`
`MT48LC2M8S1 SDRAM chip, in which the amount of electrical energy drawn from
`
`the computer system is reduced. Id. 3:58-61, 6:56-58, & 3:21-26. Accordingly,
`
`Schaefer is applicable as prior art and discloses the volatile memory devices with self
`
`refresh mode and address and control lines, from Claims 1 and 10; the memory access
`
`enable control device for determining access from Claim 1; and that the volatile
`
`memory are DRAM devices, from Claims 5 and 16.
`
`The Micron functional specification discloses that Schaefer’s MT48LC2M8S1
`
`SDRAM “meets all JEDEC functional specifications.” Micron Datasheet, 2-3. The
`
`Joint Electron Device Engineering Council (JEDEC) is an independent
`
`semiconductor engineering standardization body that maintains the industry-
`
`recognized standards for most memory devices in the market today. Fig. 1 of
`
`Schaefer is a functional block diagram illustrating the structure of Micron’s
`
`MT48LC2M8S1 SDRAM chip. It is noted that the Micron functional block diagram
`
`from Schaefer is similar to the block diagram established under the JEDEC standards
`
`9
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`
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`for SDRAM. Ex. 1007 (JEDEC JESD79 Std.), page 4. Fig. 1 from Schaefer is
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`ATTORNEY DOCKET NO.: 21584-112006
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`annotated and reproduced below:
`
`The block diagram from the JEDEC SDRAM standard is annotated and
`
`
`
`reproduced below:
`
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`10
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`ATTORNEY DOCKET NO.: 21584-112006
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`Specific structural similarities include:
`
` the existence of multiple “banks” of memory in both the JEDEC
`
`specification and Schaefer;
`
` access control components – illustrated as the “control logic” in JEDEC
`
`and the command controller in Schaefer;
`
` address and control signals generated by the respective logic in JEDEC
`
`and Schaefer; and
`
` refresh components – common to both.
`
`Ex. 1002 (Bagherzadeh Decl.), ¶¶ 31-33.
`
`2.
`Qureshi (Ex. 1005) issued on August 11, 1998, and is prior art to the ‘315
`
`U.S. Patent No. 5,793,776 (“Qureshi”)
`
`patent under at least Section 102(b). Qureshi was not considered during the
`
`prosecution of the ‘315 patent. See, ‘315 patent, 1: References Cited.
`
`Qureshi is assigned to Samsung Electronics and teaches a memory controller
`
`for SDRAM chips, such as the Micron SDRAM chip described in Schaefer. Qureshi’s
`
`memory controller is a test controller that is configured to place a connected SDRAM
`
`chip into a low power self-refresh mode to retain the existing data. Ex. 1005
`
`(Qureshi), Abstract. Ex. 1002 (Bagherzadeh Decl.), ¶ 34. Accordingly, Qureshi is
`
`applicable as prior art and discloses the control device that initiates the self refresh
`
`modes and triggers the electrical isolation, from Claims 1 and 10; and that the volatile
`
`11
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`memory are DRAM devices, from Claims 5 and 16. Ex. 1002 (Bagherzadeh Decl.), ¶¶
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`ATTORNEY DOCKET NO.: 21584-112006
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`44-45 & 64-65.
`
`3.
`Mazur (Ex. 1006) issued on April 20, 1993, and is prior art to the ‘315 patent
`
`U.S. Patent No. 5,204,840 (“Mazur”)
`
`under at least Section 102(b). Mazur was not considered during the prosecution of
`
`the ‘315 patent. See ‘315 patent, 1: References Cited.
`
`Mazur teaches the use of a battery as an alternative low power source (e.g., a
`
`rechargeable battery”) to drive a DRAM device in a low power refresh mode. For
`
`example, Mazur discloses “methods [to] back up the dynamic RAM memory of the
`
`associated computer system in the event of a power loss or outage.” Ex. 1006
`
`(Mazur), 2:24-26. Mazur discloses corresponding hardware that includes “a power
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`loss detection circuit, an independent power supply, a continuously rechargeable
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`battery which is recharged by the independent power supply, a standby refresh circuit,
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`a switch-over circuit, address and data busses, and an address control circuit, all of
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`which are in addition to and augment the existing conventional computer circuits.”
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`Id., 2:6-14. Ex. 1002 (Bagherzadeh Decl.), ¶ 35. Accordingly, Mazur is applicable as
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`prior art and discloses the “second electrical power source” from Claim 10, and that
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`the volatile memory are DRAM devices, from Claims 5 and 16. Ex. 1002
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`(Bagherzadeh Decl.), ¶¶ 64-65.
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`C. Claim Construction 37 C.F.R. § 42.104(b)(3)
`In proceedings before the Patent Office, the challenged claims are interpreted
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`according to their broadest reasonable interpretation that is consistent with the
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`ATTORNEY DOCKET NO.: 21584-112006
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`specification of the ‘315 patent (“BRI”). MPEP §§ 2111 & 37 C.F.R. § 42.100(b).
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`The BRI standard is broader than the claim construction applied in district court –
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`according to the understanding of a person of ordinary skill in the art. See, e.g., In re
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`Am. Acad. Of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004).
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`In the concurrent litigation involving the ‘315 patent, Patent Owner uses the
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`JEDEC standards as evidence of infringement, broadly construing the claim terms to
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`read on the JEDEC standards for memory devices. Ex. 1016, 3:¶¶9-10 & Ex. 1017, 3.
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`Specifically, Patent Owner alleges that the “testing and validating” of “any memory
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`product identified as being DDR2, DDR3, or DDR4 [according to] JEDEC
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`Standards” infringe the ‘315 patent.2 Ex. 1016, 3:13. See also, Ex. 1017, 3:
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`to show [infringement,] it is only necessary to compare the respective
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`applicable JEDEC Standards for the DDR2, DDR3, and DDR4 memory
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`products to claim 1 and take into account the equipment Smart Modular uses
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`for its tests . . .
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`Patent Owner alleges that the ‘315 patent’s claims encompass any system made in
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`accordance with the JEDEC standards. Id. Accordingly, Petitioner uses Patent
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`2 The JEDEC standards to which Patent Owner refers are JESD79-2F (DDR2
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`SDRAM Specification), JESD79-3F (DDR3 SDRAM Standard), and JESD79-4
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`(DDR4 SDRAM). Exs. 1003, 1; 1017, 2 & 1016, 3: ¶10.
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`Owner’s infringement contentions for specific and consistent claim constructions, and
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`ATTORNEY DOCKET NO.: 21584-112006
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`submits, for the purposes of this IPR only, that the terms of the challenged claims are
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`to be given their broadest reasonable interpretation as understood by one of ordinary
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`skill in the art in view of the specification of the ‘315 patent and Patent Owner’s
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`infringement contentions as set forth below. See SAP America, Inc. v. Versata Dev.
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`Group, Inc. , CBM2012-00001, Paper 36 (Jan. 9, 2013) at 8-9.
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`1.
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` “A Memory System For Use In A Computer System”
`(Claims 1 & 10)
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`To the extent that the preamble is limiting, the construction of “[a] memory
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`system for use in a computer system” should at least be:
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`a JEDEC-compliant system with memory devices connected to a
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`memory controller.
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`As discussed above, the ‘315 patent discloses a memory system, coupled with a
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`computer, that is “in accordance with the JEDEC industry standard” ‘315 patent,
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`5:41-48. In the concurrent litigation, Patent Owner stated that the “memory system”
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`should be construed broadly enough to encompass:
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`DDR2, DDR3, and DDR4 [memory devices that] comply with the
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`respective JEDEC Specifications [and that are subjected to] tests [by
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`a control device for] the respective memory products.
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`Ex. 1003, 2 & 4 (emphasis added) and Ex. 1017, 4, 8 & 12 (stating that each of DDR
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`2, 3 & 4 standards are “within the scope of the preamble” during testing). All DDR
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`standards, including the DDR2, DDR3, and DDR4 standards, are DRAM memory
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`ATTORNEY DOCKET NO.: 21584-112006
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`standards issued by the JEDEC. Ex. 1003, 1; Ex. 1016, 3:¶10; Ex. 1017, 2; and Ex.
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`1002 (Bagherzadeh Decl.), ¶¶ 30 & 37.
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`Patent owner’s statements in the concurrent litigation are relevant to the
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`present construction, because they set forth that the claims may be construed by a
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`POSITA without departing from the ‘315 patent specification. In re Am. Acad. Of Sci.
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`Tech Ctr., 367 F.3d at 1359, 1369.
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`2.
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`“Plurality Of Volatile Solid State Memory Devices” (Claims
`1 & 10)
`
`The construction of a “plurality of volatile solid state memory devices” should
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`at least be:
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`more than one bank of JEDEC-compliant memory.
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`The ‘315 patent discloses a memory system, coupled with a computer, that is
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`“in accordance with the JEDEC industry standard” ‘315 patent, 5:41-48. The ’315
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`patent also describes bank selection using two write enable signals, corresponding to
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`separate banks, stating that “[a] logic HIGH on
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`/WE dictates the READ from memory mode
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`while a logic LOW on /WE dictates the
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`WRITE to memory mode.” Id., 10:6-9. Fig. 5I
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`(excerpt reproduced). Patent Owner stated in
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`litigation that the “plurality of volatile solid state memory devices” should be
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`construed broadly enough to encompass “banks of memory” in DDR2, 3, or 4, which
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`ATTORNEY DOCKET NO.: 21584-112006
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`comply with the respective JEDEC Specifications.” Ex. 1003, 2 & 4; Ex. 1008, 16;
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`Ex. 1017, 5, 8 & 12. Ex. 1002 (Bagherzadeh Decl.), ¶¶ 38. Patent Owner’s
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`statements are relevant to the present construction for the same reasons as set forth in
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`Section (V)(C)(1), above.
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`3.
`The construction of a “address lines and control lines” should at least be:
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`“Address Lines And Control Lines” (Claims 1 & 10)
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`JEDEC-compliant address and control balls or pins.
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`The ‘315 patent describes that the “solid state memory devices [are] in two way
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`communications [using] a standard memory connector . . . such as a 72 PIN SIMM,
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`144 PIN SODIMM, or 168 PIN DIMM connector, all three in accordance with the
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`JEDEC industry standards.” ‘315 patent, 9:9-14. The ’315 patent also describes that
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`“[the] address buses [are] in direct communication with memory devices . . . via the
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`address pins of the memory devices” and that “[e]ach DRAM in the configuration has
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`. . . three control signals, /CAS, /RAS and /WE, and eleven address lines labeled A0-
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`A10.” Id., 9:18-20 & 10:65-11:1.
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`Patent Owner alleged in
`
`litigation that the “address lines and
`
`control lines” should be construed
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`broadly enough to encompass the JEDEC standards (e.g., section 2.3 of DDR2). Exs.
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`1003, 3 & 1017, 14. An excerpt from section 2.3 of DDR2 (reproduced here)
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`illustrates that the JEDEC specification includes control balls or pins (e.g., BA, RAS,
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`ATTORNEY DOCKET NO.: 21584-112006
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`CAS & WE) and address balls or pins (e.g., A0-A15) to receive corresponding
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`JEDEC-complaint BA, RAS, CAS, WE, and address signals. Ex. 1008, 13. See also,
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`Ex. 1002 (Bagherzadeh Decl.), ¶ 39.
`
`4.
`
` “A Control Device For Selectively Electrically Isolating
`[The] Memory Devices” (Claim 1) & “A Control Device . . .
`For Selectively Electrically Isolating [The] Memory
`Devices” (Claim 10)
`
`The construction of “a control device for selectively electrically isolating [the]
`
`memory devices” (Claim 1, and its variation in Claim 10) should at least be:
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`a memory controller for providing a JEDEC-compliant signal to
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`trigger a ‘don’t care’ or inhibit action for the corresponding memory
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`devices.
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`The ‘315 patent discloses a memory system, coupled with a computer, that is
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`“in accordance with the JEDEC industry standard . . .” ‘315 patent, 5:41-48. The
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`patent also explains that a “DNC further electrically isolate[s] the DRAMs . . . by
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`inhibiting any responses . . .” Id., 10:24-26. It further explains that “[t]he [DNC chip
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`provides control signals, e.g., ] /RASO, /CASO and /WEO, which are inputs to the
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`respective DRAM chip. ” Id., 10:14-16. Accordingly, a POSITA would understand
`
`that the DNC is a controller for providing JEDEC-compliant RAS, CAS, and WE
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`signals for the memory devices, which in turn “inhibit any responses” from the
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`memory devices. Ex. 1002 (Bagherzadeh Decl.), ¶¶ 40-41.
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`ATTORNEY DOCKET NO.: 21584-112006
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`Patent Owner stated in litigation that “a control device for selectively
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`electrically isolating” should be construed to encompass the JEDEC standards (e.g.,
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`sections 2.3, 3.10, 3.11, and 4.2 of DDR2). Ex. 1003, 4 & Ex. 1017, 15. Specifically,
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`Patent Owner alleged that the “‘don’t care’ [is] electrically isolating” – which Section
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`3.10 of the JEDEC DDR2 specification describes:
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`When the DDR2 SDRAM has entered Self Refresh mode, all of the
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`external signals except CKE, are “don’t care.”
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`Ex. 1008, 50. This establishes to a POSITA that the JEDEC-compliant memory
`
`devices are configured to enter a “don’t care state,” in which its responses are
`
`inhibited, when appropriate JEDEC-compliant signals from a controller are applied to
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`these memory devices. Ex. 1002 (Bag