SMART EXHIBIT 1006
`
`SMART EXHIBIT 1006
`
`

`
`_
`United States Patent
`
`[19]
`
`llllll|||||||l|||lllllllllllllll||l||lllllIllllllllllllllllllll|l||||l||||I
`Usoos2o4840A
`[11] Patent Number:
`
`5,204,840
`
`Mazur
`
`[45] Date of Patent:
`
`Apr. 20, 1993
`
`[54] MEANS AND Mymons pox pngsgnvmc
`Mjcnopgocgssog MEMORY
`
`
`
`3/1939 Fujii .......
`4.315.032
`364/900
`4,823,308 4/1989 Knight . . . . . . .
`... .. 364/900
`4,897,631
`1/1990 Jundtetal.
`.365/228)(
`.
`4,901,233
`2/1990 Hanbury 61111.
`365/222
`Jeffrey 13- Mnzur, 8041 Sadnng
`4,959,774 9/1990 Davis
`364/200
`Ave., Canoga Park, Calif. 91304
`21333132 ‘$13 ?i§.:.f..“:..::....................:_3“§2i’/§o’é
`I211 Am» No—= 391.096
`Primary Examiner—Alyssa H. Bowler
`[22] Fihd‘
`“'3' 8* 1989
`[51]
`111:. CL: ........................ GllC 5/14; [57]
`ABSTRACT
`[52] us. c1. .................................. .. 365/228; 365/229;
`Means and methods for Preservins the RAM of an
`395/425; 364/DIG. 1; 364/969.4; 364/DIG. 2
`externally powered microprocessor on the oecasion of a
`[53] Field of Search
`364/200, 900, 969.4,
`loss In external 1>ower- When the power loss is detected,
`364/969.3; 365/226, 227, 228, 229
`I signal is generated which initiates a sequence to isolate
`the RAM and refresh it with an independent power
`supply. When main power is restored, the microproces-
`sor is restored to its precise location at the moment of
`'’°“’'?' '°”' sh‘"d°“’“' “an”? ‘“‘.d 5°°“"‘y ’°"‘“‘°5 are
`pf0VldCd
`SOfKW3IC CII1bOdICd In Ihfl SYSICHI.
`
`[76]
`
`Inventor:
`
`‘
`
`5 Claims, 4 Drawing Sheets
`
`Reference‘ Cit“
`U.S. PATENT DOCUMENTS
`4,573,774
`3/1986 Muller ............................... .. 364/900
`4,631,701 12/1986 Kappa”. cl 8].
`4 365/222 X
`4,7l8,038
`l/1988 Yoshida ........ ..
`364/900
`4,788,661 ll/1988 Morita ............. ..
`. 365/228 X
`
`
`
`[56]
`
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`
`CAS/RAS
`
`SMART EXHIBIT 1006 - PAGE - 1
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`SMART EXHIBIT 1006 - PAGE - 1
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`

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`US. Patent
`
`Apr. 20, 1993
`
`Sheet 1 0:4
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`SMART EXHIBIT 1006 - PAGE - 2
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`

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`U.S. Patent
`
`Apr. 20, 1993
`
`Sheet 2 of 4
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`SMART EXHIBIT 1006 - PAGE - 3
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`SMART EXHIBIT 1006 - PAGE - 3
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`US. Patent
`
`Apr. 20, 1993
`
`Sheet 3 of 4
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`SMART EXHIBIT 1006 - PAGE - 4
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`

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`US. Patent
`
`Apr. 20, 1993
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`Sheet 4 of 4
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`SMART EXHIBIT 1006 - PAGE - 5
`
`

`
`1
`
`5,204,840
`
`MEANS AND METHODS FOR PRESERVING
`MICROPROCESSOR MEMORY
`
`INTRODUCTION
`This invention relates generally to microcomputers
`and like devices which employ dedicated microproces
`sors and more particularly to means and methods for
`maintaining the status quo of the microprocessor and all
`device memory associated therewith when the electric
`power supplied thereto is either intentionally or unin
`tentionally, diminished or is interrupted altogether.
`
`2
`and MPU are mounted to automatically restart its pro
`cessing cycle at the precise point of interruption.
`BRIEF SUMMARY OF THE INVENTION
`At a system level, the means of the present invention
`comprise both hardware and software. The hardware
`‘comprises in coactive combination a power loss detec
`tion circuit, an independent power supply, a continu
`ously rechargeable battery which is recharged by the
`independent powerv supply, a standby refresh circuit, a
`switch-over circuit, address and data busses, and an
`address control circuit, all of which are in addition to
`and augment the existing conventional computer cir
`cuits. The software used in combination with the hard
`ware is capable, upon power fail detect, to copy all of
`the volatile data stored in the microprocessor and de
`liver it to nonvolatile storage. Upon subsequent power
`up, the normal reboot sequence is aborted and the data
`held in the nonvolatile storage is copied back to the
`microprocessor which creates an “instant-on" system,
`that is, the user is returned to where he left the machine
`when power was lost.
`In operation, the means and methods of the present
`invention back up the dynamic RAM memory of the
`associated computer system in the event of a power loss
`or outage. In addition, the present invention preserves
`the status of the machine and upon resumption of the
`principal power source, restores the machine to the
`precise place it was at the moment of the power loss or
`outage. Furthermore, means are provided which main
`tain the security of the data and password protect the
`computer after restoration of original power.
`The prior art has heretofore dealt with the problems
`created for static random access memory (“SRAM”)
`when the power source fails. None have successfully
`transferred the protective concept to the management
`and protection of the dynamic RAM (DRAM). It is
`toward this goal that the present invention is directed.
`Accordingly a prime object of the present invention
`is to provide new and unique means and methods for
`placing a computer in “suspended animation" during
`the course of a loss or interruption of external power
`and for causing it to restart when the external power is
`restored without any loss of information originally con
`tained in DRAM or the computer‘s microprocessor.
`Another object of the present invention is to provide
`new and improved means which allow a microcom
`puter to restart after a power interruption without re
`quiring a reset or reboot process.
`A further object of the present invention is to provide
`new and improved means which allow a computer to be
`turned off and on, and to thereafter resume operation as
`if the power interruption had never occurred.
`These and still further objects of the present inven
`tion as shall hereinafter appear, are fulfilled by the pres
`ent invention in a remarkably unexpected fashion as can
`be readily discerned from a careful consideration of the
`following description of the preferred embodiments
`thereof especially when read in conjunction with the
`accompanying drawing in which like parts bear like
`indicia throughout the several views.
`
`25
`
`BACKGROUND OF THE INVENTION
`During the past ten to ?fteen years microcomputers,
`and related devices have pervaded Western society and
`are commonplace throughout America. Indeed, it has
`been reported that one in seven American teenagers
`have access to their own microcomputer. The total
`number of microcomputers in use throughout the
`United States has been estimated to total more than 70
`million.
`The proliferation of microcomputer devices has been
`fueled in large part by dramatic cost reductions in the
`manufacture of integrated circuit chips, namely Dy
`namic Random Access Memory (DRAM) and in the
`production of Microprocessor (MPU) chips. Without
`low cost DRAM and MPU chips, the electronic explo
`sion most likely would not have occurred.
`MPU and DRAM chips, and all devices reliant there
`upon, share a common vulnerability. These chips re
`quire a constant and uninterrupted supply of electric
`power to function properly. A power interruption of
`35
`only a millisecond can cause such chips to lose all infor
`mation programmed thereon and thus abort what could
`be a very valuable asset of a business enterprise.
`The provision of uninterruptable power supplies to
`keep MPU and DRAM chips in action at a time when
`an external power source is interrupted is not practical
`in most applications. Large batteries and complex
`switching are required which violate the basic size and
`weight requirements inherent in most applications uti
`lizing MPU and DRAM chips.
`This vulnerability to imperceptible power outages
`affects not only the microcomputer, but those devices
`controlled or reliant upon MPU and/or DRAM chips.
`If, for example, a clothes or dishwasher is mechanically
`controlled, a ?ve minute power outage is a minor incon
`venience that the consumer may not even notice. When
`the power comes back on, the appliance continues with
`its cycle as if the interruption had not occurred.
`Such is not the case with the new and improved
`computer controlled appliances where the loss of
`55
`power to the DRAM and MPU assures that all informa
`tion kept therein is lost. In such a case, the appliance
`will go to the "ready" or “abort” mode, and await fresh
`input. The interrupted cycle will not be completed.
`Further, the programmed cycles maintained in DRAM
`and the MPU will have to be reestablished in the device
`before it can be again usefully employed.
`It is therefore apparent that a clear need exists for
`means and methods which will unequivocally preserve
`the information contained in DRAM and the micro
`processor even though its power supply is interrupted
`and which will upon the restoration of the external
`power source, allow the device with which the DRAM
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWING
`In the drawing:
`FIG. 1 shows a functional block diagram of a system
`embodying the present invention;
`FIG. 2 is a more detailed block diagram of the em
`bodiment of FIG. 1.
`
`SMART EXHIBIT 1006 - PAGE - 6
`
`

`
`5,204,840
`4
`3
`electrically erasable programmable ROM (“EE
`FIG. 3 is a block diagram of the power supply of the
`PROM”).
`embodiment of FIG. 1; and
`Power supply means 18, as shown in FIG. 3, includes
`FIG. 4 is a block diagram of the power fail detector
`an external transformer power source 30, rechargeable
`of the embodiment of FIG. 1.
`battery 31, battery charging circuit 32, and a voltage
`DESCRIPTION OF THE PREFERRED
`regulator 33. Charging circuit 32 acts continuously to
`EMBODIMENT
`‘recharge battery 31 so long as the hardware receives
`electricity from external power source 30. Power loss
`In practice, the means and methods embodying the
`detection circuit M, as shown in FIG. 4, comprism a
`present invention function as follows. When the power
`precision reference voltage 34, an input voltage 35, and
`loss detection circuit senses a signi?cant undervoltage
`a comparator 36. When input voltage 35 falls below the
`from the external power source relative to a preselected
`value set for reference voltage 34, as determined by the
`reference voltage value, the device hereof will automat
`comparator 36, a NMI signal 37 is sent to computer 16,
`ically switch from a passive mode to an active mode and
`send a signal to the computer microprocessor directing
`to a delay 23, then to refresh switch-over circuit 24
`signifying the voltage drop. Delay 23 is an LC. circuit
`it to follow a novel and unique shutdown routine with
`which it has been speci?cally programmed. After the
`that delays the signal by about one millisecond. Such
`microprocessor completes the shutdown routine, the
`circuits are well known. Once refresh switch-over cir
`microprocessor is essentially placed in suspended ani
`cuit 24 has been noti?ed of the voltage drop, circuit 24
`mation. The typical gyrations followed by a micro
`switches the DRAM of computer 16 to receive its
`20
`processor as it loses power do not affect the stored
`DRAM refresh signal from refresh generator 22 rather
`memory as the DRAM is isolated from the MPU
`than from within computer 16 (which signal was depen
`switching circuitry. The states and pointers of the mi
`dent on the power whose failure was detected). The
`croprocessor are recorded in a portion of the replace
`refresh signals delivered by refresh generator 22 to the
`ment DRAM which allows all of the information con
`DRAM of computer 16 are synchronized to the com
`tained in the microprocessor and DRAM at the time of 25
`puter's normal refresh signal by a synchronization cir
`the power loss to be preserved.
`cuit which is a part of refresh switch-over circuit 24.
`The standby refresh circuit in the novel system will
`Refresh switch-over circuit 24 also acts to isolate the
`continue to refresh the replacement DRAM for the
`DRAM of the computer 16 from the computer device
`duration of the external power source interruption.
`16 per se so that none of the information maintained and
`30
`Such interruption can persist for an indefinite period of
`retained in the DRAM is corrupted during the shut
`time if the device is on external power. If both the de
`down and restart of computer 16. The refresh generator
`vice and computer have lost power, the refresh can be
`22 insures that the information in the DRAM is main
`continued for as long as its associated battery holds out.
`tained as it was at the last moment of normal operation
`Current batteries possess sufficient power to maintain
`of computer 16 so long as power is received from power
`the memory in "suspended animation" for eight hours
`supply 18.
`or more.
`Referring now to FIG. 2 which shows a block dia
`When external power is restored to the computer, the
`gram of system 10 when it is con?gured for use with a
`device embodying the present invention will direct the
`MACINTOSH SE computer (Apple Computer Corp.,
`microprocessor to follow a special preprogrammed
`Cuppertino, Calif). Because the hardware must pre
`40
`restart procedure and resume operating as if the power
`cisely interact with the computer 16 on which it is in
`interruption had never happened. All of the micro
`stalled, both software means 12 and the associated hard
`processor states and pointers are restored to the status
`ware will require some modi?cation to render it com
`quo ante. When the voltage equals the preselected refer
`patible with the device for which use of system 10 is
`ence value, the microprocessor is reenabled, and the
`intended. However, as will appear, the basic concept of
`microcomputer resumes normal operations. To the user,
`the system as shown herein is equally applicable to all
`the restart of the microcomputer is essentially instanta
`such computer devices with which the system 10 may
`neous after power has been restored.
`be installed. The MACINTOSH SE is referred to
`Referring to the drawing, a memory preserving sys
`herein merely to exemplify the invention.
`tem embodying the present invention, is identi?ed by
`In one embodiment hereof, power supply means 18
`the general reference numeral 10. As shown in FIG.
`comprises an external transformer supply 30, a re
`each system 10 comprises software means 12 associated
`chargeable battery 31, a battery charging circuit 32, and
`with hardware means, each of which are more fully
`voltage regulator 33. When the computer 16 is on, the
`described below. System 10, when operable, is coac
`voltage to system 10 and the DRAM is supplied by the
`tively connected to a computer 16 which may contain a
`computer’s internal power circuit. When the computer
`microprocessing unit ("MPU”) or a full board proces
`16 is turned off, unplugged, or otherwise loses its
`sor.
`power, the requisite voltage to operate system 10 and
`The hardware hereof comprises independent power
`refresh DRAM is instantaneously delivered by trans
`supply means 18, power-loss detection circuit 20, re
`former 30. Should transformer 30 lose power, the
`fresh generator 22, a refresh switch-over circuit 24, a
`DRAM will forthwith receive its maintenance voltage
`60
`power switch-over circuit 26, a non-volatile memory
`from battery 31. Battery 31 is preferably nickel-cad
`(“NVM”) 28, and memory connection means 29 con
`mium but any battery known to the art to be recharge
`nected to the dynamic RAM of computer 16, each of
`able can be used. The voltage delivered to system 10
`which operatively interact with each other and coact
`and the DRAM by either transformer supply 30 or
`with software means 12 to allow the system 10 to per
`battery 31 will be regulated through a voltage regulator
`form its intended function as will now be more fully
`33.
`described. The term “non-volatile memory" as used
`As shown in FIG. 2, refresh generator 22 comprises
`herein includes such known memory elements as static
`an oscillator which produces pulses of a preselected
`RAM, erasable programmable ROM ("I-PROM“) and
`
`65
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`55
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`15
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`35
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`45
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`SMART EXHIBIT 1006 - PAGE - 7
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`

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`5,204,840
`6
`5
`As previously explained, the software 12 can include
`repetition rate and duration to refresh the DRAM sup
`four functional routines, namely, the installation pro
`ported by system 10.
`gram (or code), the shutdown routine (or code), the
`In installing system 20 into a microcomputer 16, for
`restart routine (or code) and the security routine (or
`example, a MACINTOSH SE, the DRAM is removed
`code). These routines will now be described in further
`from the computer and placed on an auxiliary circuit
`detail.
`board (not shown) upon which system 10 is mounted.
`The installation program is run every time the com
`Typical installation involves conventional SIMM sock
`puter is rebooted. This program installs the shutdown
`ets which for all functions except column address select
`routine (or code) and the restart routine (or code) into
`("CAS"), row address select (“RAS”) and supply volt
`the NVM 28 disposed on the system board 10._It also
`age (V cc), couple the computer generated signals to the
`changes the NMI vector so that the vector now points
`DRAM. The CAS, RAS and Vcc signals will originate
`to the shutdown code. As will appear, the restart code
`with the computer 16 when the computer's power sup
`is installed in such a way that it is automatically exe
`ply is functioning correctly and from system 10 when a
`cuted upon restart of the computer. Note that in a per
`power lapse has occurred.
`fect world, the installation program will be run only
`A variety of schemes exist for storing the software 12
`once, because system 10 obviates the need to reboot the
`within the system 10. For example, when a MACIN
`computer ever again.
`TOSH SE is in its startup mode, it looks for a hook at
`The second aspect of software 12 is the shutdown
`address SFBOOOO. NVM 28 of the system 10 is located at
`code. The computer's NM] vector is set to point to this
`address $F80000 and up. A special program is executed
`code as explained above. Thus, when an NMI is re
`to place a program in the NVM. The code contained
`ceived, the shutdown code is immediately executed.
`therein interrupts the normal restart procedure for the
`Upon execution, the code saves the contents of the
`MACINTOSH and the software 12 substitutes itself for
`registers in the MPU, saves the VIA registers, calcu
`the normal restart routines. After restart is accom
`lates a checksum of a portion of memory, and then saves
`plished, the software 12 allows the MACINTOSH to
`the checksum. This has the effect of saving the status of
`continue running the application software from the
`all volatile memory which had been in the computer
`point of interruption.
`(the DRAM is no longer volatile because of the opera
`The code in the NVM also controls the power-fail
`tion of system 10). The code then places a special "sig
`routine.
`nature” word on the stack to indicate that it (the code)
`Synchronization means 38 in the refresh switch-over
`has been run.
`circuit 24 acts to synchronize refresh generator 22 with
`The third aspect of software 12 is the restart code.
`the refresh pulses generated by the MACINTOSH.
`Upon re-application of power, computer 16 starts to
`This is necessary so that all DRAM are properly re
`reboot. Early in the reboot code, it checks to see if there
`freshed when the system 10 is activated by power loss
`is a “magic" flag at location SFSOOOO. If this ?ag is
`detection circuit 20.
`present, the code pointed to by the data at $F80004 is
`In practice with MACINTOSH SE, a fall of the
`executed. When the installation program is run, it places
`supply voltage below 4.8 V will be sensed by power fail
`the ?ag at SFSOOOO, and the address of the restart code
`detection circuit 20 which activates a one shot delay
`at $F80004. Because of this, the restart code is executed
`generator to produce a six hundred micro second delay.
`whenever power is restored. The restart code checks to
`If at the end of the delay, the incoming voltage to the
`see if the special signature word is present on the stack.
`computer 16 is still below the precision reference volt
`If it is not, the code assumes that the user wants to
`age 34, e.g., 4.8 V, as measured by loss detector 20, a
`reboot computer 16 and obligingly reboots the machine.
`non-maskable interrupt (“NMI”) signal is generated.
`However, if there is a special code or signature on the
`The use of the micro second delay avoids false trigger
`stack this will indicate that the computer was inter
`ing due to “glitches". The NM] signal then causes the
`rupted. In this case, rebooting will not occur. Instead,
`shutdown portion of the software 12 to be run. The low
`software 12 simply restores computer 16 to the status it
`voltage measurement also activates refresh switch~over
`was in when power loss occurred. If a secret mode is
`means circuit 24 via delay 23 to immediately direct
`implemented, then restoration is back into the middle of
`refresh signals to the DRAM from the refresh generator
`the security code. The code then re-calculates the mem
`22, circumventing the principal computer. The entire
`ory checksum and compares it with the saved value. If
`computer 16 is placed in suspended animation until such
`they are not equal, the machine is rebooted. The code
`time as the computer supply voltage rises above the
`then restores the registers of the MPU and VIA. This
`preselected precision voltage reference, e.g., 4.8 V, as
`has the effect of restoring the computer to virtually its
`measured by power fail detection circuit 20.
`exact state at the moment the power failed.
`The fourth aspect of software 12 which is optional, is
`When the power supply to the computer 16 is re
`the security code. The security code actually consists of
`stored, the computer 16 initiates the execution of the
`start-up routine of software 12 and the refresh signals to
`two parts, namely, one which is a utility which allows
`the DRAM are again generated by the computer 16,
`the user to set a password to prevent unauthorized
`instead of by refresh generator 22. The computer 16
`access to his machine. The password is encrypted and
`stored in SRAM 28 of system 10. This utility also allows
`then begins to run the applications software at the exact
`place where it left off when power went down.
`the user to set a delay time to allow his hard drive to
`As appears above, the system 10 of the present inven
`come up to speed.
`tion enables the Dynamic RAM of the computer to be
`The second part of the security code is a desk acces
`sory (DA) which activates the security feature. DA's
`saved even when the power supply voltage of the com
`puter reaches 0. The system thus preserves all of the
`are programs which can be activated in the middle of
`another program. The DA in system 10 allows the user
`main memory of the computer as well as the internal
`to turn off his computer with security activated. When
`memory of the microprocessor during the power inter
`ruption.
`power is restored, the DA prevents access to the com~
`
`40
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`25
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`35
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`45
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`55
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`65
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`SMART EXHIBIT 1006 - PAGE - 8
`
`

`
`5,204,840
`8
`a voltage regulator, and a battery charging circuit
`connected to said battery, said transformer power
`supply being connected to said voltage regulator
`and to said battery charging circuit, said battery
`being connected to said voltage regulator for deliv
`ery of power to said switch-over circuit; and
`a power-fall detection circuit comprising a precision
`voltage reference, means for measuring the input
`voltage to said computer system, and a comparator
`for initiating an NM] alert signal when said mea
`sured input voltage falls below said precision volt
`age reference; and
`software operatively associated therewith and re
`sponsive to said power loss detection circuit signal
`to initiate a shutdown routine when said signal is
`activated and to initiate a restart routine when said
`signal is deactivated; and
`security means for interrupting a normal startup se
`quence of said computer system to invoke a secu
`rity procedure, whereby further use of said com
`puter system would be allowed only after identify
`ing an authorized user.
`2. The system of claim 1 wherein said security means
`includes a startup detection circuit which connects to
`said computer system, which detects execution of the
`startup sequence and positively interrupts said startup
`sequence and instead executes a security routine.
`3. The system of claim'2 wherein said security routine
`comprises software operatively associated therewith
`and responsive to said startup detection circuit to initi
`ate a security routine when said startup sequence is
`detected and to allow the normal startup sequence to
`proceed only after properly identifying an authorized
`user.
`4. The system of claim 1 wherein said security means
`includes nonvolatile memory to store a security routine
`and/or user identi?cation information.
`5. The system of claim 3 wherein said security means
`includes hardware and/or software to operatively pre
`vent any person from circumventing the function of the
`security means.
`
`20
`
`25
`
`7
`puter until the correct password has been entered. At
`this time the screen is preferably blackened to prevent
`unwanted observation. The programmer’s interrupt
`switch is disabled, and reset has been circumvented, so
`there is no way to access the computer without entering
`the correct password.
`In the preferred practice of the present invention, all
`the circuitry herein described and illustrated in the
`description of system 10, with the exception of batteries
`31, can be mounted on a single circuit board which is
`installable within computer 16 in the same manner as
`any auxiliary circuit board is currently installed. When
`space constrictions do not allow a single board, system
`10 can be disposed on a plurality of boards, the actual
`placement and disposition of the several increments
`being with the skill of the art and not material to the
`unique functioning of the described system.
`From the foregoing, it becomes apparent that new
`and useful procedures have been herein described and
`illustrated which ful?ll all of the aforestated objectives
`in a remarkably unexpected fashion. It is of course un
`derstood that such modi?cations, alterations and adap
`tations as may readily occur to an artisan having the
`ordinary skills to which this invention pertains are in
`tended within the spirit of the present invention which
`is limited only by the scope of the claims appended
`hereto.
`Accordingly, what is claimed is:
`l. A system for preserving at least the main random
`access memory (“RAM") of a computer system having
`a power supply on the occasion of a sudden loss in
`power, said system comprising:
`a power loss detection circuit adapted to sense a loss
`in the power supply of said computer system and
`emit a signal causing a switch-over circuit to isolate
`at least said main RAM from the computer system
`and cause at least said main RAM to receive its
`power from an independent power source; and
`a power switch-over circuit responsive to said power
`loss detection signal to connect said independent
`power source to said memory; and
`an independent power supply comprising an external
`transformer power supply, a rechargeable battery,
`
`30
`
`O
`
`'
`
`Q U
`
`'
`
`45
`
`50
`
`55
`
`65
`
`SMART EXHIBIT 1006 - PAGE - 9