United States Patent [191
`Fujinami et al.
`
`lllllllllllllllllllllllllllllllllllllllllllllll|l||llllllllllllllllllllllll
`5,521,922
`May 28, 1996
`
`[11]
`
`[45]
`
`USOO5521922A
`Patent Number:
`Date of Patent:
`
`[54] DATA DEMULTIPLEXER
`
`OTHER PUBLICATIONS
`
`[75] Inventors: Yasushi Fujinami, Kanagawa; Markus
`H. Veltman, Tokyo, both of Japan
`
`[73] Assignee: Sony Corporation, Tokyo, Japan
`
`[21]
`[221
`[30]
`
`Appl. No.: 245,768
`Filed:
`May 18, 1994
`Foreign Application Priority Data
`
`May 25, 1993
`
`[JP]
`
`Japan .................................. .. 5-122269
`
`[51] Int. Cl.6 ...................................................... .. H04J 3/06
`[52] U.S. Cl. ....................... .. 370/84; 370/100.l; 370/112;
`348/423; 352/12; 352/25
`[58] Field of Search .................................. .. 370/84, 100.1,
`370/l05.l, 105.4, 105.5, 112; 348/17, 423,
`466, 467; 352/12, 14, 15, 16, 17, 19, 20,
`21, 22, 23, 24, 25; 379/93, 96
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3,898,376
`5,231,492
`5,262,964
`5,287,182
`5,291,486
`
`8/1975
`Nabeyama et al. ............ .. 370/l00.l X
`7/1993
`Dangi et a1. ...... ..
`11/1993
`Bonsall et al. ..
`..
`2/1994 Haskell et a1. ..
`3/1994 Koyanagi .......................... .. 370/112 X
`
`FOREIGN PATENT DOCUMENTS
`
`0245904Al 11/1987
`0460751A2 12/1991
`522853A3 l/l993
`0577329A2 1/1994
`4345271A1 5/1994
`2259229 3/ 1993
`
`European Pat. Off. ....... .. H04N U21
`European Pat. Oif. ....... .. H04N 5/92
`European Pat. Off. ....... .. H04N 5/92
`European Pat, Oif. ....... .. H04N 7/13
`Germany ............. ..
`H04N 5/92
`United Kingdom ............ .. H04] 3/22
`
`Macinnis, A., “The MPEG systems coding speci?cation”,
`Signal Processing: Image Communication, vol. 4, No. 2;
`(Amsterdam, NL: Apr. 1992); pp. 153-159.
`International Standards Organisation, 20 Apr. 1992, Tokyo,
`“Coding of Moving Pictures and Associated Audio for
`Digital Storage Media at up to About 1.5 Mbits/s, Part 1,
`Systems”.
`
`Primary Examiner-Douglas W. Olms
`Assistant Examiner-Russell W. Blum
`Attorney, Agent, or Firm—William S. Frommer; Alvin
`Sinderbrand
`
`ABSTRACT
`[57]
`A data demultiplexer for separating multiplex data including
`at least coded video data, coded audio data, timing data
`indicative of a video decoding start time, timing data indica
`tive of an audio decoding start time, and timing data
`indicative of a system clock reference time. The demulti
`plexer comprises a circuit for separating the multiplex data
`into the component data, and comparators for comparing
`input data with the reference timing data. When the timing
`data indicative of a video decoding start time is inputted and
`detected, the video data is written in a video code buffer at
`the maximum transfer rate. During such time period, the
`reference timing data indicative of the current time is
`monitored, and the operation of decoding the video data is
`started when the reference timing data has become equal to
`the video timing data. A similar operation is performed with
`regard to the audio data as well, so that the video and audio
`data can be inputted fast to consequently enhance the
`responsivity at the start of reproduction.
`
`16 Claims, 11 Drawing Sheets
`
`l 1
`
`I"
`s2
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`RING
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`
`[,5 DATA DEMULTI PLEXER
`
`,
`
`e
`
`SEPARATION
`CIRCUIT
`
`VIDEO DATA
`AUDIO DATA
`22
`
`DTSV
`oTsv REGISTZ:
`
`DTSA REG'STER
`3I
`
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`coIvIIfAIaAToR
`START SIGNAL
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`
`LG Ex. 1008, pg 1
`
`

`
`US. Patent
`
`May 28, 1996 '
`
`Sheet 1 of 11
`
`5,521,922
`
`FIG. I(A)
`
`ECC
`RING
`r> DRIVE *DEMODULATORg
`CIRCUIT “’ BUFFER “’
`
`[/5 DATA DEMULTI PLEXER
`
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`
`LG Ex. 1008, pg 2
`
`

`
`US. Patent
`
`May 28, 1996
`
`Sheet 2 of 11
`
`5,521,922
`
`—————————————— "T,
`
`61
`
`87'
`
`VIDEO
`gSP-E-ER
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`DECODER VIDEQ
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`OUTPUT
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`FIG. I
`
`FIG. I(A) FIG. I(B)
`
`LG Ex. 1008, pg 3
`
`

`
`US. Patent
`
`May 28, 1996
`
`Sheet 3 of 11
`
`5,521,922
`
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`
`LG Ex. 1008, pg 4
`
`

`
`US. Patent
`
`May 28, 1996
`
`Sheet 4 of 11
`
`5,521,922
`
`MECKA
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`
`LG Ex. 1008, pg 5
`
`

`
`US. Patent
`
`May 28, 1996
`
`Sheet 5 0f 11
`
`5,521,922
`
`I‘
`
`I2
`
`I3
`
`I4
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`ECC
`
`RING I
`
`[,5 DATA DEMULTIPLEXER
`T ?ak-5F ____________________________ n
`I
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`IIIIIRIIION
`@
`:
`CIRCUIT
`{9
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`I g
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`26
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`GENERATOR 27
`
`CONTROL
`C'RCU'T
`28;
`
`VIDEO SYNC
`SIGNAL
`
`INPUT
`uNIT “29
`
`@@
`
`LG Ex. 1008, pg 6
`
`

`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 6 of 11
`
`5,521,922
`
`FIG. 4(B)
`
`VIDEO SYNC SIGNAL
`
`?III IIII
`
`VIDEO
`4 CODE
`BUFFER
`
`VIDEO
`DECODER
`I
`
`VIDEO DECODING
`START SIGNAL
`
`In;
`L..I2_J
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`PARATOR
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`OUTPUT
`
`AU D I O
`OUTPUT
`
`AUDIO
`DECODER
`I
`
`AUDIO DECODING
`START SIGNAL
`
`FIG 4
`
`FIG. 4(A) FIG. 4(8)
`
`LG Ex. 1008, pg 7
`
`

`
`US. Patent
`
`May 28, 1996
`
`Sheet 7 of 11
`
`5,521,922
`
`FIG. 5(A)
`( PRIOR ART)
`S2
`
`ra- DRIVE —>DEMODULATOR—
`
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`CIRCUIT
`
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`LG Ex. 1008, pg 8
`
`

`
`US. Patent
`
`May 28,1996
`
`Sheet 8 0f 11
`
`5,521,922
`
`F I G. 5(8)
`( PRIOR ART)
`
`6
`(7
`I
`VIDEO
`@—* CODE —-' éétéggm
`I
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`SIGNAL
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`OUTPUT
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`AUDIO DECODING START
`SIGNAL
`
`FIG.I5
`
`FIG.5(A) AFIG.5(B)
`
`LG Ex. 1008, pg 9
`
`

`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 9 of 11
`
`h._xo<n_O_D34.
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`LG Ex. 1008, pg 10
`
`LG Ex. 1008, pg 10
`
`
`
`
`
`
`
`
`

`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 10 of 11
`
`5,521,922
`
`
`
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`LG Ex. 1008, pg 11
`
`LG Ex. 1008, pg 11
`
`

`
`U.S. Patent
`
`May 28,1996
`Sheet 11 of 11
`F I G. 8
`( PRIOR ART)
`
`5,521,922
`
`AMOUNT
`OF DATA
`\
`
`t3
`
`t6
`
`>TIME
`
`8 Mbps
`2 Mbps
`8 Mbps
`(HIGH RATE) (LOW RATE) (HIGH RATE)
`
`AMOUNT
`OF DATA
`A
`
`F\~ PICTURE W
`START-UP DEEAY
`OF PICTURE w
`i
`'[5
`
`l
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`w TIME
`
`ts
`
`LG Ex. 1008, pg 12
`
`

`
`5,521,922
`
`1
`DATA DEMULTIPLEXER
`
`BACKGROUND OF THE INVENTION
`
`2
`parators 23 and 25 respectively so as to be compared with
`the ST C signal outputted from the STC register 26. A control
`circuit 28 consists of a CPU or the like and serves to control
`the data separation circuit 21 in response to a command
`received from an input unit 29 by a user’s manipulation.
`The video data stored in the video code bu?er 6 is read out
`therefrom and is supplied to a video decoder 7. Then, the
`video data is decoded to become a video signal, which is
`subsequently outputted to an unshown circuit. To the video
`decoder 7, there is also supplied a video decoding start
`signal which is outputted from the comparator 23.
`Similarly, the data outputted from the audio code bu?er 8 V
`is supplied to an audio decoder 9 so as to be decoded. To the
`audio decoder 9, there is also supplied the output of the
`comparator 25 as an audio decoding start signal.
`Now the operation will be described below with reference
`to a timing chart of FIG. 7. First, the input unit 29 is
`manipulated for instructing the control circuit 28 to start
`reproduction. Then, the control circuit 28 sends a command
`to the drive 1 to thereby reproduce the data recorded on an
`optical disk incorporated in the drive 1. The reproduced data
`outputted from the drive 1 is supplied to the demodulator 2,
`and the demodulated data obtained therefrom is supplied to
`the ECC circuit 3 where a process of error detection and
`correction is executed. The data thus processed is supplied
`via the ring buffer 4 to the data separation circuit 21 in the
`data demultiplexer 5.
`The data separation circuit 21 is controlled by the control
`circuit 28 and separates the output data of the ring buffer 4
`into video data and audio data, which are then supplied to the
`video code bu?fer 6 and the audio code buffer 8, respectively.
`The circuit 21 further separates the timing data into SCR,
`DTSV and DTSA, which are supplied respectively to the
`STC register 26, the DTSV register 22 and the DTSA
`register 24 and then are stored therein.
`The STC register 26 having stored the timing data SCR
`therein counts the clock pulses outputted from the clock
`generator 27 and increments the storage value in response to
`the clock pulses. The storage value of the STC register 26 is
`supplied as a system time clock (STC) signal to the com
`parators 23 and 25.
`The DTSV register 22 holds the video timing data DTSV
`supplied ?rst thereto after the start of reproduction by the
`drive 1. Consequently, the register 22 has a decoding start
`time relative to a top picture out of the entire data stored in
`the video code buffer 6.
`Similarly, the DTSA register 24 holds the audio timing
`data DTSA supplied ?rst thereto after the start of reproduc
`tion, so that the register 24 has a decoding start time relative
`to a top decode unit out of the entire data stored in the audio
`code buffer 8.
`The reference timing data SCR corresponds to the time
`when demultiplexing is started after supply of the data from
`the ring buffer 4 to the data demultiplexer 5. More speci?
`cally, it corresponds to a time t1 in the timing chart of FIG.
`7. Therefore the STC register 26 outputs the time data
`(current time) from the time t1 to one input terminal of each
`of the comparators 23 and 25.
`The DTSV register 22 supplies the video timing data
`DTSV, which indicates the decoding start time of the video
`decoder 7, to the other input terminal of the comparator 23.
`When the current time outputted from the STC register 26
`has become coincident with the decoding start time output
`ted from the DTSV register 22 (i.e., at a time t2 in FIG. 7),
`the comparator 23 outputs a video decoding start signal to
`the video decoder 7. In response to the video decoding start
`
`l0
`
`15
`
`25
`
`35
`
`The present invention relates to a data demultiplexer
`adapted for reproducing time-division multiplex data
`recorded on an optical disk or the like and separating the
`same into video data and audio data.
`FIG. 5 is a block diagram showing an exemplary consti
`tution of a conventional data demultiplexer known hereto
`fore. In this diagram, a drive 1 reproduces the data recorded
`on an optical disk incorporated therein. On this optical disk,
`there are recorded both video data and audio data in a
`time-division multiplex form. The reproduced data output
`ted from the drive 1 is supplied to a demodulator 2 so as to
`be demodulated. An ECC circuit 3 detects and corrects any
`error in the data outputted from the demodulator 2 and
`supplies the processed data to a ring buifer 4. Then the ring
`buffer 4 stores a predetermined amount of the supplied data
`therein and subsequently outputs the data to a data demul
`tiplexer 5.
`The data demultiplexer 5 has a data separation circuit 21
`which demultiplexes the data supplied from the ring buifer
`4 to thereby separate the same into video data and audio
`data, and further into timing data such as SCR (system clock
`reference) and DTS (decoding time stamp) inclusive of
`DTSV for the video data and DTSA for the audio data.
`The format of the data supplied to the data demultiplexer
`5 is so standardized as shown in FIG. 6 for example. This
`format is prescribed as a multiplex bit stream in the MPEG
`30
`(15011172). As shown in FIG. 6, a multiplex bit stream is
`composed of one or more packs (PACKS), each of which is
`composed of one or more packets (PACKETS). A pack
`header (PACK HEADER) is disposed at the top of each pack
`and has a pack start code (PACK START CODE) indicating
`a start point of the pack, and also SCR and MUX_RATE.
`This SCR indicates the time when the last byte is inputted to
`the data demultiplexer 5 (the time when demultiplexing is
`started), and the MUX_RATE signi?es a transfer rate.
`In the example of FIG. 6, a video packet (VIDEO
`PACKET) and an audio packet (AUDIO PACKET) are
`disposed next to the pack header. A packet header is dis
`posed at the top of each of such packets and has a video
`packet start code (VIDEO PACKET START CODE) or an
`audio packet start code (AUDIO PACKET START CODE)
`indicating a start point of the video or audiolpacket, and
`further has DTSV or DTSA indicating a decoding start time
`of the video or audio data. Video data or audio data is
`disposed next to each packet header. However, since the
`amount of video data per unit time is greater than that of
`audio data, video timing data DTSV is disposed at a rate of
`once per plural packs.
`Such timing data of SCR and DTS (DTSV or DTSA) are
`represented by count values of 90-kHz clock pulses and
`have 33-bit effective digits.
`The video data is supplied to a video code buffer 6 (FIFO).
`Meanwhile the audio data is supplied to an audio code buffer
`8 (FIFO). The reference timing data SCR is supplied to an
`STC register 26 to be stored therein. The STC register 26
`counts 90-kHz clock pulses outputted from a clock generator
`27 and increments its storage value to generate an STC
`(system time clock) signal.
`The timing data DTSV and DTSA are supplied to a DTSV
`register 22 and a DTSA register 24 respectively so as to be
`65
`stored therein. The timing data thus stored in the DTSV
`register 22 and the DTSA register 24 are supplied to com
`
`55
`
`LG Ex. 1008, pg 13
`
`

`
`5,521,922
`
`15
`
`20
`
`25
`
`30
`
`35
`
`3
`signal thus received, the video decoder 7 reads out one frame
`of the video data written in the video code buffer 6 and then
`starts its decoding.
`In FIG. 7, a straight line A represents a state of writing the
`data in the video code buifer 6 (with an inclination signi
`fying a write and transfer rate), and a line B represents a state
`of reading out the data from the video code buffer 6 by the
`video decoder 7. It follows, therefore, that the data within a
`shaded area in FIG. 7 is left in the video code buffer 6. The
`storage capacity of the video code buffer 6 is expressed by
`a distance perpendicular to the time axis extending from line
`A to a line C.
`The video decoder 7 starts its decoding in response to the
`video decoding start signal supplied thereto and generates a
`video vertical synchronizing signal upon completion of the
`decoding, i.e., after a lapse of a video decode delay (VIDEO
`DECODE-DELAY) from the start of the decoding, and then
`outputs a video signal in succession thereto. More speci?
`cally, a display is started after a lapse of the video decode
`delay from the start of the decoding.
`Similarly, the comparator 25 outputs an audio decoding
`start signal when the current time outputted from the STC
`register 26 has become coincident with the audio decoding
`start time outputted from the DTSA register 24. The audio
`decoder 9 reads out the data from the audio code buffer 8 in
`response to the audio decoding start signal and starts its
`decoding. An audio signal generated as a result of such
`decoding is outputted to an unshown circuit.
`The above is the operation performed when the transfer
`rate is a ?xed one. FIG. 8 shows a timing chart of signals in
`the case of adopting a variable transfer rate. A high rate
`mode of 8 Mbps is selected in the operation before a time t3
`and after a time t6, and a low rate mode of 2 Mbps is selected
`during a period between the times t3 and t6. The latter
`transfer rate is designated when the data are encoded by an
`unshown encoder.
`In FIG. 8, a line D represents a state of writing the data
`in the video code buffer 6, and its inclination signi?es a
`transfer rate. A line F represents a state of reading out the
`data from the video code buffer 6 by the video decoder 7. It
`follows, therefore, that the data within a shaded area in FIG.
`8 is left in the video code buffer 6. The storage capacity of
`the video code buffer 6 is expressed by a distance perpen
`dicular to the time axis extending from line D to a line E.
`In the lower diagram of FIG. 8 (an enlarged view of the
`period from time L3 to time t6), a picture W is a subject to
`be noted now as an example. The data of the picture W
`begins to be loaded in the video code bu?rer 6 at the time t4,
`which is indicated by the timing data SCR affixed to the pack
`where the head G of the data of the picture W is stored. The
`data of the picture W begins to be decoded at a time t5,
`which is indicated by the timing data DTSV a?ixed to the
`packet where the head of the picture W is stored.
`The input unit 29 is manipulated for instructing the
`control circuit 28 to start reproduction of the data from the
`picture W. The control circuit 8 sends a command to the
`drive 1, which then accesses a desired position on the optical
`disk incorporated therein and reproduces the recorded data.
`The reproduced data outputted from the drive 1 is supplied
`to the demodulator 2 so as to be demodulated, and the output
`therefrom is supplied to the ECC circuit 3 where a process
`of error detection and correction is executed. The data thus
`processed is supplied via the ring buffer 4 to the data
`separation circuit 21 in the data demultiplexer 5.
`Data MUX_RATE is disposed at the top of each pack, so
`that the transfer rate of the relevant pack can be detected by
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`referring to this data. For example, the data separation
`circuit 21 controls the transfer rate in accordance with the
`value of this data. As to control of variable rate data, an
`exemplary description is disclosed in UK Patent GB 2 259
`229 A (Date of publication: Mar. 3, 1993).
`The data separation circuit 21 controlled by the control
`circuit 28 separates the video data from the output data of the
`ring buffer 4 and supplies the video data to the video code
`buffer 6. The circuit 21 further separates the timing data into
`SCR and DTSV, which are then supplied to the STC register
`26 and the DTSV register 22 respectively and are stored
`therein. Since the operation of the audio section is similar to
`that mentioned above, a repeated description is omitted here.
`The STC register 26 having stored the reference timing
`data SCR therein counts the clock pulses outputted from the
`clock generator 27 and increments the storage value in
`response to the clock pulses. The storage value of the ST C
`register 26 is supplied as a system time clock (STC) signal
`to the comparators 23 and 25.
`The timing data SCR corresponds to the time when
`demultiplexing is started after supply of the data of the
`picture W to the data demultiplexer 5. More speci?cally, it
`corresponds to a time t4 in the timing chart of FIG. 8.
`Therefore, the STC register 26 outputs the timing data
`(current time) from the time t4 to one input terminal of each
`of the comparators 23 and 25.
`The DTSV register 22 supplies the video timing data
`DTSV, which indicates the picture-W decoding start time of
`the video decoder 7, to the other input terminal of the
`comparator 23. When the current time outputted from the
`STC register 26 has become coincident with the decoding
`start time outputted from the DTSV register 22 (i.e., at a time
`t5 in FIG. 8), the comparator 23 outputs a video decoding
`start signal to the video decoder 7. In response to the video
`decoding start signal thus received, the video decoder 7
`reads out one frame of the video data written in the video
`code buifer 6 and then starts its decoding.
`In the conventional demultiplexer of FIG. 5, as described,
`the time period from SCR (t4) to DTS (t5) is controlled by
`counting clock pulses of a ?xed frequency, and the data are
`written in the buffer during such time period. Consequently,
`the data transfer rate is ?xed at one value designated on the
`encoder side, so that it has been impossible heretofore to
`shorten the start-up delay even when the data supply rate to
`the demultiplexer 5 is lower than the maximum transfer rate
`and a margin thereof is still left.
`
`SUMMARY OF THE INVENTION
`
`The present invention has been accomplished in view of
`the circumstances mentioned above and it is an object of the
`present invention to provide an improvement which is
`capable of enhancing the responsivity of the system by
`shortening the start-up delay.
`According to a ?rst aspect of the present invention, there
`is provided a data demultiplexer for separating multiplex
`data which includes at least ?rst coded data such as video
`data, ?rst timing data indicative of a decoding start time of
`the ?rst coded data, and second timing data indicative of a
`system clock reference time. The demultiplexer comprises a
`separation means for separating the multiplex data into the
`?rst coded data, the ?rst timing data and the second timing
`data; and a comparison means for comparing the time, which
`is indicated by the ?rst timing data separated by the sepa
`ration means, with the time indicated by the second timing
`data; wherein, when the time indicated by the second timing
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`data is temporally anterior to the time indicated by the ?rst
`timing data, the multiplex data is supplied at the maximum
`transfer rate to the separation means.
`The data demultiplexer further comprises a system time
`clock generation means for generating a system time clock
`signal by setting an initial value thereof on the basis of the
`?rst timing data and then incrementing predetermined clock
`pulses; and a means for generating a ?rst decoding start
`signal by comparing the ?rst timing data with the system
`time clock signal.
`The multiplex data further includes second coded data
`such as audio data, and third timing data indicative of a
`decoding start time of the second coded data. The demulti
`plexer further comprises a means for generating a second
`decoding start signal by comparing the third timing data
`with the system time clock signal.
`According to a second aspect of the present invention,
`there is provided a data demultiplexer for separating multi
`plex data which includes at least ?rst coded data such as
`video data, ?rst timing data indicative of a decoding start
`time of the ?rst coded data, second coded data such as audio
`data, and second timing data indicative of a decoding start
`time of the second coded data. The demultiplexer comprises
`a separation means for separating the multiplex data into the
`?rst coded data, the ?rst timing data, the second coded data
`and the second timing data; and a comparison means for
`comparing the time, which is indicated by the ?rst timing
`data separated by the separation means, with the second
`timing data; wherein the separation means does not supply
`the second coded data when the time indicated by the second
`timing data is temporally anterior to the time indicated by
`the ?rst timing data.
`According to a third aspect of the present invention, there
`is provided a data demultiplexing method for separating
`multiplex data which includes at least ?rst coded data such
`as video data, ?rst timing data indicative of a decoding start
`time of the ?rst coded data, and second timing data indica
`tive of a system clock reference time. The demultiplexing
`method comprises the steps of: separating the multiplex data
`into the ?rst coded data, the ?rst timing data and the second
`timing data; comparing the time, which is indicated by the
`separated ?rst timing data, with the time indicated by the
`second timing data; and reading out the multiplex data from
`a buffer at the maximum transfer rate when the time indi
`cated by the second timing data is temporally anterior to the
`time indicated by the ?rst timing data.
`The data demultiplexing method further comprises the
`step of generating a system time clock signal by setting an
`initial value thereof on the basis of the ?rst timing data and
`then incrementing predetermined clock pulses.
`The demultiplexing method further comprises the step of
`generating a decoding start signal by comparing the ?rst
`timing data with the system time clock signal.
`The multiplex data further includes second coded data
`such as audio data, and third timing data indicative of a
`decoding start time of the second coded data. The demulti
`plexing method further comprises the step of generating a
`second decoding start signal by comparing the third timing
`data with the system time clock signal.
`According to a fourth aspect of the present invention,
`there is provided a data demultiplexing method for separat
`ing multiplex data which includes at least ?rst coded data
`such as video data, ?rst timing data indicative of a decoding
`start time of the ?rst coded data, second coded data such as
`audio data, and second timing data indicative of a decoding
`start time of the second coded data. The demultiplexing
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`method comprises the steps of: separating the multiplex data
`into the ?rst timing data, the ?rst coded data, the second
`coded data, and the second timing data; comparing the time,
`which is indicated by the separated ?rst timing data, with the
`time indicated by the second timing data; and supplying
`none of the second coded data to a decoder when the time
`indicated by the second timing data is temporally anterior to
`the time indicated by the ?rst timing data.
`In the data demultiplexer of the constitution mentioned,
`the video timing data DTSV is compared with the reference
`data SCR by the comparison means. In accordance with the
`result of such comparison, the video and audio data can be
`inputted at a higher transfer rate designated in the bit stream,
`hence enhancing the responsivity at the start of reproduc
`tron.
`The above and other features and advantages of the
`present invention will become apparent from the following
`description which will be given with reference to the illus
`trative accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram showing an exemplary consti
`tution of a ?rst embodiment which represents the data
`demultiplexer of the present invention;
`FIG. 2 is a timing chart of signals for explaining the ?rst
`embodiment of FIG. 1;
`FIG. 3 is a conventional timing chart of signals for
`comparison with FIG. 2;
`FIG. 4 is a block diagram showing an exemplary consti
`tution of a second embodiment which represents the data
`demultiplexer of the invention;
`FIG. 5 is a block diagram showing an exemplary consti
`tution of a conventional data demultiplexer in the related art;
`FIG. 6 is an explanatory diagram of a multiplex bit stream
`in the example of FIG. 5;
`FIG. 7 is a timing chart of signals for explaining the
`operation of the example shown in FIG. 5; and
`FIG. 8 is a timing chart of signals for explaining the
`operation at a variable transfer rate in the example of FIG.
`5.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Hereinafter preferred embodiments of the present inven
`tion will be described in detail with reference to the accom
`panying drawings.
`FIG. 1 is a block diagram showing an exemplary consti
`tution of a ?rst embodiment which represents the data
`demultiplexer of the invention, wherein any like component
`circuits or elements corresponding to those in the aforemen
`tioned conventional example of FIG. 5 are denoted by the
`same reference numerals. In this ?rst embodiment, a data
`demultiplexer 5 comprises a data separation circuit 21, a
`DTSV register 22, a DTSA register 24, comparators 23 and
`25, an STC register 26, a clock generator 27 , an SCR register
`31, and switch circuits 51, 52, 53 and 54.
`The output of the DTSV register 22 is supplied to the
`comparator 23, while being also supplied to one input
`terminal al of the switch circuit 51. Similarly, the output of
`the DTSA register 24 is supplied to the comparator 25 while
`being also supplied to another input terminal a2 of the switch
`circuit 51. The output obtained from an output terminal b of
`the switch circuit 51 is supplied to the STC register 26 so as
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`to be stored therein. The STC register 26 counts clock pulses
`of 90 kHz produced from the clock generator 27 and
`increments its storage value to thereby generate a system
`time clock STC. The STC thus outputted from the STC
`register 26 is connected to an input terminal c2 of the switch
`circuit 52.
`To the SCR register 31, there is supplied a system clock
`reference SCR separated as timing data by the data separa
`tion circuit 21. The output of the SCR register 31 is
`connected to another input terminal cl of the switch circuit
`52.
`An output terminal d of the switch circuit 52 is connected
`to another input terminal of each of the comparators 23 and
`25.
`The output of the comparator 23 is connected to an input
`terminal e of the switch circuit 53. One output terminal f1 of
`the switch circuit 53 is connected to a video decoder 7, while
`another output terminal f2 thereof is connected to a control
`circuit 28.
`Similarly, the output of the comparator 25 is connected to
`an input terminal g of the switch circuit 54. One output
`terminal hl of the switch circuit 54 is connected to an audio
`decoder 9, while another output terminal h2 thereof is
`connected to the control circuit 28.
`The switch circuits 51, 52, 53 and 54 are controlled by the
`control circuit 28.
`The operation of the ?rst embodiment will now be
`described below. First, the input unit 29 is manipulated for
`instructing the control circuit 28 to start reproduction of an
`optical disk. In this stage, the control circuit 28 sets the data
`demultiplexer 5 in its initialize mode. More speci?cally, the
`switch circuit 52 is closed through the contact cl so that the
`output of the SCR register 31 is supplied to the comparators
`23 and 25. Meanwhile, the switch circuit 53 is closed
`through the contact f2, and the switch circuit 54 is closed
`through the contact h2 so that the resultant outputs of the
`comparators 23 and 25 are supplied to the control circuit 28.
`The data separation circuit 21 is controlled by the control
`circuit 28 and separates the output data of a ring buffer 4 into
`video data and audio data, which are then supplied to a video
`code buffer 6 and an audio code buffer 8, respectively. The
`circuit 21 further separates the timing data into SCR, DTSV
`and DTSA, which are then supplied to the SCR register 31,
`the DTSV register 22 and the DTSAregister 24, respectively
`so as to be stored therein.
`The SCR register 31 stores the latest one of the reference
`timing data SCR supplied thereto successively and outputs
`the stored data therefrom. The DTSV register 22 holds the
`video timing data DTS