VWGoA - Ex. 1011
`Case No. IPR2015-01613
`Volkswagen Group of America, Inc. - Petitioner
`Joao Control & Monitoring Systems, LLC - Patent Owner
`
`1
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`

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`5,875,486
`Page 2
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`U.S. PATENT DOCUMENTS
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`5/1989 K_1uCh1 ................................... .. 395/595
`4,827,405
`7/1989 Yoshimoto ......................... 365/189.05
`4,849,937
`5/1990 Hayakawa et al.
`.............. .. 365/230.08
`4,922,461
`
`9/1990 Hashimoto
`.... .. 365/233
`4,956,820
`4,962,487 10/1990 Suzuki
`............................... .. 365/233.5
`4,967,397 10/1990 Walck ................................... .. 365/222
`N 327/141
`4,975,593
`12/1990 Kurakazu et al.
`
`6/1991 Nishikawa ............................ .. 395/299
`5,021,950
`5,054,000 10/1991 Miyaji
`.............................. .. 365/230.03
`5,058,074 10/1991 Sakamoto .............................. .. 365/236
`
`5,073,733
`.......................... .. 327/261
`12/1991 Tanno etal.
`5,235,545
`8/1993 McLaury .......................... .. 365/230.08
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`3/1994 F““1Yf* 6‘ a1~
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`5305377
`4/1994 Dem“ 6‘ a1~
`365/23002
`5311437
`5/1994 Toda eta1~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~ 365/236
`5,323,358
`6/1994 Toda et al.
`....................... .. 365/230.09
`5,341,341
`8/1994 Fukuzo ............................. .. 365/230.08
`5,343,438
`8/1994 Choietal.
`............................ .. 365/233
`5,390,149
`2/1995 Vogley etal.
`................... .. 365/189.01
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`SPECIFICATION
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`U.S. Patent
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`Feb. 23, 1999
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`Feb. 23, 1999
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`U.S. Patent
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`Feb. 23, 1999
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`Sheet 18 of 18
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`5,875,486
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`1
`SEMICONDUCTOR MEMORY DEVICE
`WITH CLOCK TIMING TO ACTIVATE
`MEMORY CELLS FOR SUBSEQUENT
`ACCESS
`
`This application is a continuation of application Ser. No.
`08/720,309, now U.S. Pat. No. 5,737,637, Sep. 27, 1996;
`which is is a continuation of prior application Ser. No.
`08/427,270, filed on Apr. 24, 1995; which is a divisional of
`Ser. No. 08/223,222, filed Apr. 5, 1994 now U.S. Pat. No.
`5,500,829; which is a divisional of Ser. No. 07/775 ,602, filed
`Oct. 15, 1991, now U.S. Pat. No. 5,313,437.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor memory
`device comprising a plurality of easily-controllable memory
`cells which can be accessed at high speed.
`2. Description of the Prior Art
`A conventional, standard, general-purpose DRAM has a
`page mode for access at a high speed cycle time. As is
`commonly known, in this page mode it is possible to access
`specified memory cells in a row of a memory cell array
`selected by means of a row address, by arbitrarily changing
`a column address in a string of simultaneously sensed
`memory cells.
`High speed access is possible with this type of mode for
`the following reasons. Considerable time is required for
`sense amplification of the cell data in a DRAM, but once the
`data has been sensed, the read-out of this data proceeds very
`quickly. Once a column address has been changed in the
`page mode operation, the access to the sense amplifier which
`has sensed that cell is commenced and the data is output
`when a CAS signal is switched to “L.” Accordingly, the page
`mode is a random access mode.
`
`Recently, the capacity of memory chips has been increas-
`ing year after year. Accordingly, the number of chips used in
`a system has been reduced. Therefore, when large volume
`chips are used in the prior art, namely when many chips are
`used in a system, these chips are divided into a number of
`groups which are interleaved, making it possible to construct
`and utilize a memory system in which the apparent cycle
`time is short, but this method cannot be used in a system
`having small volume chips.
`On the other hand,
`the speeds of MPUs have been
`increasing year after year, and even in a small scale system
`there is a necessity to achieve high speeds. For these reasons,
`it has become necessary for a memory to operate at even
`higher cycle speeds. Also, from these requirements it is not
`absolutely necessary for the access operation to be random;
`there are many cases in which all that is required is the
`ability to read or write a string of data at high speed.
`Amethod for providing a high speed operation for RAML
`including SRAM and the like has been reported in the
`following literature.
`Chikai Ohno, “Self-Timed RAM: STRAM”, FUJITSU
`Sci. tech. J., 24, 4, pp 293-300, December 1988.
`In the literature,
`the following method is disclosed. A
`RAM (STRAM) operates in synchronization with a system
`clock, namely in the RAM, an address signal and R/W
`signals for a read-out or for write-in are received in syn-
`chronization with the clock signal at a timing, then at the
`next timing a content of the memory cell addressed by the
`address signal is output.
`the address signal must be
`However,
`in this method,
`provided at every cycle of the system clock. Therefore, there
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`is a disadvantage that the access operation to a memory cell
`in the RAM cannot be followed by the period of the system
`clock when the period becomes high.
`When a conventional page mode is used, an address
`change is absolutely necessary. Therefore, it is impossible to
`operate with a higher access cycle time which is more than
`the time needed by the address control of the system. Speed
`increases for the memory access operation are therefore
`limited.
`
`Control signals such as RAS signals and CAS signals
`must be supplied to the memory chip. These control signals
`are produced by the system. Accordingly, the control for
`supplying the control signals to the memory chip is an
`obstacle to providing a high speed operation with a memory
`system which includes an access means. In this case, the
`operation control of the system becomes so complex that it
`is difficult to use the control of the system.
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide, with due
`consideration to the drawbacks of such conventional
`
`devices, a semiconductor memory device provided with an
`easily-controllable dynamic memory which can be accessed
`at high speed.
`Access by the semiconductor device of the present inven-
`tion commences with an internal operation synchronized
`with a basic clock signal which is input at an almost
`continuous, fixed frequency. After the address is obtained,
`the operation which determines “read-out” or “write-in”,
`begins after a certain cycle number of fixed cycles which are
`basic clock cycles, input at an almost fixed frequency. The
`operation is controlled by a specifying signal for specifying
`a cycle which acts as the starting point for counting these
`cycles.
`A first type semiconductor memory device according to
`the first embodiment of the present invention, comprises:
`a memory cell group comprising a plurality of memory
`cells arranged in matrix;
`specification means for specifying sequentially memory
`cells addressed by consecutive addresses in the memory
`cells, and for entering them in an active state;
`data input/output
`(I/O) means for performing a data
`read-out/write-in operation (data I/O operation) for the con-
`secutive memory cells specified by the specification means
`under a control based on a read-out/write-in signal provided
`from an external section;
`count means for counting the number of cycles of a basic
`clock signal provided from an external section; and
`control means for receiving at least one or more specifi-
`cation signals provided from an external section,
`for outputting a control signal per specification signal for
`specifying a particular cycle as a starting cycle to count the
`number of the cycles of the basic clock signal, and
`for instructing the count means to count the number of
`counts of the basic clock signal based on the control signal,
`and for controlling a specification operation executed by the
`specification means and the data I/O operation of the data
`I/O means, so that the memory access operations for the
`memory cell group are controlled.
`A second type semiconductor memory device according
`to the second embodiment of the present invention, com-
`prises:
`a memory cell group comprising a plurality of memory
`cells grouped into a plurality of cell blocks arranged in
`matrix;
`
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`3
`selection means for outputting a selection signal provided
`based on a basic clock signal provided consecutively from
`an external section and an address signal for specifying an
`address of the cell block in order to select and activate the
`
`cell block by interleaving consecutively the memory cell
`blocks;
`specification means for specifying sequentially and acti-
`vating the memory cells addressed by consecutive addresses
`in the memory cell block in accordance with the address
`signal and the selection signal for activating and enterring
`the cell block in an active state by the selection means;
`data input/output
`(I/O) means for performing a data
`read-out/write-in operation (data I/O operation) for the con-
`secutive memory cells specified by the specification means
`under a control based on a read-out/write-in signal provided
`from an external section;
`count means for counting the number of cycles of the
`basic clock signal provided from an external section; and
`control means for receiving at least one or more specifi-
`cation signals provided from an external section.
`For outputting a control signal per specification signal for
`specifying a particular cycle as a starting cycle to count the
`number of the cycles of the basic clock signal, and
`for instructing the count means to count the number of
`counts of the basic clock signal based on the control signal,
`and for controlling a selection and activation operation
`executed by the selection means, a specification operation
`executed by the specification means and the data I/O opera-
`tion executed by the data I/O means, so that by which the
`memory access operations for the memory cell group are
`controlled.
`
`A third type semiconductor memory device according to
`the third embodiment of the present invention, comprises:
`a memory cell group comprising a plurality of memory
`cells arranged in matrix;
`specification means for specifying and activating at once
`a fixed number of the memory cells, as a package memory
`cell, addressed by consecutive addresses in the memory cells
`in accordance with a basic clock signal and an address signal
`provided from an external section;
`store means for storing temporarily data from or to the
`fixed number of the memory cells specified at once by the
`specification means;
`control means for carrying at once a data transfer opera-
`tion between the fixed number of the memory cells specified
`at once by the specification means and the store means in
`accordance with the basic clock signal and the specification
`signal;
`data input/output (I/O) means for executing sequentially a
`data read-out/write-in operation (data I/O operation) for the
`store means in accordance with the basic clock signal; and
`count means for counting the number of cycles of a basic
`clock signal,
`wherein the control means receives at least one or more
`
`specification signals provided from an external section,
`outputs a control signal per specification signal for speci-
`fying a particular cycle as a starting cycle to count the
`number of the cycles of the basic clock signal,
`instructs the count means to count the number of counts
`
`of the basic clock signal based on the control signal,
`controls a specification operation executed by the speci-
`fication means and the data I/O operation of the data I/O
`means based on the number of the cycles including the
`number of the cycles at least two or more counted from the
`particular cycle by the count means, and
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`so that the control means controls the memory access
`operations for the memory cell group.
`These and other objects, features and advantages of the
`present invention will be more apparent from the following
`description of preferred embodiments, taken in conjunction
`with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a semiconductor memory
`device as a first embodiment according to the present
`invention;
`FIG. 2A, 2B, 2C and 2D are timing charts showing an I/O
`operation of the semiconductor memory device shown in
`FIG. 1;
`FIGS. 3A—5H are timing charts showing I/O operations
`based on various I/O control methods for the semiconductor
`memory device shown in FIG. 1;
`FIG. 6 is a block diagram of a semiconductor memory
`device as a second embodiment according to the present
`invention;
`FIG. 7 is a diagram showing an arrangement of a cell
`array mat of memory cell groups as a part in the semicon-
`ductor memory device shown in FIG. 6;
`FIG. 8 is a circuit diagram of a column decoder incorpo-
`rated into the semiconductor device shown in FIG. 6;
`FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, 91, 9] and 9K are
`timing charts showing an I/O operation of the semiconductor
`memory device shown in FIG. 6;
`FIGS. 10 to 14 are configuration diagrams showing cir-
`cuits which produce various types of cycles of clock signals;
`FIG. 15 is a configuration diagram showing a counter
`circuit for use in serial access;
`FIG. 16 is a block diagram of a semiconductor memory
`device as a third embodiment according to the present
`invention;
`FIG. 17A, 17B, 17C, 17D and 17E are timing charts
`showing an I/O operation of the semiconductor memory
`device shown in FIG. 16;
`FIG. 18 is a block diagram of a semiconductor memory
`device as a fourth embodiment according to the present
`invention;
`FIGS. 19A, 19B, 19C, 19D and 19E are timing charts
`showing an I/O operation of the semiconductor memory
`device shown in FIG. 18; and
`FIG. 20 is a block diagram of a semiconductor memory
`device as a fifth embodiment according to the present
`invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Other features of this invention will become apparent in
`the course of the following description of exemplary
`embodiments which are given for illustration of the inven-
`tion and are not intended to be limiting thereof.
`FIG. 1 is a configuration drawing showing the essential
`parts of a first embodiment of the semiconductor memory
`device of the present invention. The memory device illus-
`trated in the drawing uses a dynamic memory cell, a static
`memory cell, or a non-volatile memory cell. In this memory
`device, control of the internal circuit operations is based on
`the number of cycles of a continuous external clock signal,
`to perform the memory access operation.
`As shown in FIG. 1, a memory device 1 comprises a
`memory cell group 2 provided with a normal memory
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`device, a specification section 3, and a data I/O section 4, to
`which are added a counting section 5 and a control section
`6, which are the main structural elements for performing the
`operation which is the special feature of the present inven-
`tion.
`
`The dynamic memory cell, the static memory cell, or the
`non-volatile memory cell of the memory cell group 2 is
`arranged in the form of a matrix. The data which is written
`in and read out is stored in this memory cell. The specifi-
`cation section 3 allots consecutive addresses in the memory
`cell group 2 according to a series of externally-provided
`address signals, and designates, in order, the memory cells
`which are to be accessed. The specification section 3, for
`example, fetches a row address signal, then fetches a series
`of column address signals for a string of memory cells
`designated by the row address signal. The specification
`section 3 designates a series of memory cells consecutively
`by means of the column address signal.
`The data I/O section 4 performs a read or write operation
`on a memory cell designated by the specification section 3
`based on a read/write signal obtained externally. The read-
`out data is output to an external destination through the data
`I/O section 4. The data to be stored is provided to the
`designated memory cell from an external source through the
`data I/O section 4 by the specification section 3.
`The counting section 5 is a counter for counting the
`number of cycles of a basic clock signal CLK continuously
`input at an almost fixed frequency from an external source.
`The counter 5 is capable of counting a fixed number of
`clock cycles of the basic signal CLK and discriminating
`some clock cycles from other cycles. A circuit essentially
`having the function can be considered as the counter 5.
`Therefore a circuit having the function described above can
`be used instead of the counter 5 when there is the circuit in
`
`the semiconductor memory device.
`The external basic clock signal CLK used in this embodi-
`ment is a clock signal with a cycle time of, for example, less
`than the 30 ns access time of the memory device. The
`counting section 5 provides the control section 6 with the
`count of the number of cycles of the clock signal CLK.
`The control section 6 receives a specification signal which
`is provided from an external source and stipulates the
`conditions for the memory device, for example, a E (chip
`enable) signal or an E (output enable) signal, for specify-
`ing a particular cycle of the clock signal CLK by means of
`a level transition, designates the particular cycle of the clock
`signal CLK for each signal, and, in addition, initiates the
`count of the clock signals CLK in the counting section 5.
`The control section 6, based on the number of cycles of the
`clock signal CLK counted by the counting section, 5,
`controls the fetching of the address signal in the specifica-
`tion section 3 and the internal I/O operation of the data in the
`data I/O section 4, and the like.
`Next, the operation of the device shown in FIG. 1 will be
`explained using timing charts shown in FIGS. 2A—FIGS.
`5H.
`
`FIGS. 2A—2D are diagrams showing one example of the
`timing chart of an operation I/O signal for the memory
`device shown in FIG. 1. In FIGS. 2A—2D, a signal CLK is
`a clock signal with a cycle time of 30 ns or less for
`continuous input and output, which is provided into the
`counting section 5.
`A signal E is a signal which indicates the active period
`of the memory device 1. The operation of the memory
`device 1 is controlled by means of the value of the signal
`CLK during the period when a signal E is at the “L” level.
`
`6
`
`In FIGS. 2A—2D, the signal E enters the “L” level, and the
`value of an address signal Add is fetched as a row address
`R to the specification section 3 at the rise of the initial clock
`signal CLK (CYCLE 1). Following this, the value of the
`address signal Add at the rise of the clock signal CLK of the
`fifth CLK cycle (CYCLE 5) is fetched to the specification
`section 3 as a column address CN. The data of the column
`
`address CN is output to the data I/O section 4 from the eighth
`active clock cycle (CYCLE 8) which is the third clock signal
`after the column address CN has been fetched.
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`10
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`According to the progress of the clock signals 9, 10,
`11,
`.
`.
`.
`,
`the data from a previously decided order of
`addresses CN+1, CN+2, CN+3, .
`.
`. is output serially to the
`data I/O section 4. When the CE signal is switched to the
`“H” level, a fixed number of clock cycles is ignored after the
`signal E enters the “H” cycle on the rise of the clock signal
`CLK, and the memory enters the inactive state. In FIGS.
`2A—2D, the rise of the clock signal CLK occurs following
`the 14th clock cycle (CYCLE 14).
`Several variations have been considered in a control
`
`method for this type of memory. Examples of these varia-
`tions will be illustrated. In FIGS. 3A—FIG. 5H, specific
`examples of timing waveforms are shown.
`In addition,
`representative values of stipulated timing periods are also
`shown simultaneously in FIGS. 3A—5H.
`A CE/RL signal in FIGS. 3A—FIG. 5H corresponds to the
`E signal in FIGS. 2A—2D. However, the E signal is based
`on the negative logic and the CE/RL signal on the positive
`logic. The logic of the E signal differ from the logic of the
`CE/RL signal.
`An R/W signal provides instructions as to whether or not
`the memory operates for a read-out or for a write-in. A0 to
`A9 (shown in FIGS. 3A—3G and 4A—4H) and A0 to A19
`(shown in FIGS. 5A—5H) are address signals. A signal CM
`indicates that the memory does not receiving a clock signal
`while the CM signal is “H”.
`DOUT/,N indicates data read out of an accessed memory
`cell or data written into that memory cell.
`An T signal is a control signal. When the T signal is
`“L”, data is output in DOUT/,N, and when “H”, the memory
`output related to DOUT/,N is in a high impedance state.
`FIGS. 3A—3G are diagrams showing the specific fetch
`timing of an R/W signal for a read out
`instruction,
`in
`addition to the case in FIGS. 2A—2D. In FIGS. 3A—3G, the
`column address is fetched to the specification section 3 at the
`clock signal designated by the CLK @, and the memory cell
`data begins to be output to the data I/O section 4 at the clock
`signal denoted by the CLK
`FIGS. 4A—4H are timing charts in the case where a clock
`cycle in which the column address is fetched can be indi-
`cated by a clock signal
`independent of the timing for
`fetching the row address. In FIGS. 4A—4H, after the row
`address is fetched to the specification section 3, if a CL
`signal enters the “H” level when the clock signal rises, the
`column address is fetched to the specification section 3
`during that clock cycle, and access to the cell commences.
`During this fetch cycle,
`the data following the column
`addresses CN, CN+1, CN+2, CN+3, CN+4 from the clock
`cycle (CLK 3) shown in FIG. 4, which is a fixed number of
`cycles, is output in serial order.
`FIGS. 5A—5H are timing charts of I/O operations for the
`memory device in which the R/W signal is controlled based
`on level change of a RWL signal. This figure shows the
`timing chart in the case where the clock signal which fetches
`the address can be independently and freely set. This is the
`case where the address is fetched without being divided into
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`the address is not
`row and column parts (specifically,
`multiplexed). In FIGS. 5A—5H, if the RWL signal is at the
`“H” level at the rise of the clock signal CLK, the R/W signal,
`which determines whether there is a read out or a write in
`
`from the clock cycle, is fetched. The output of data starts at
`the CLK 3 which follows the above-mentioned cycle by a
`fixed number of cycles. Read-outs are shown in the above
`three timing examples in FIGS. 3A—5H, but
`it
`is also
`possible to perform a write operation by setting the R/W
`signal. In such a case, external data is input to the memory
`from DOUT/,N.
`In addition, many combinations of control operation
`methods are also possible in the above examples. For
`example, it is possible to combine the RWL signal and the
`CL signal as one signal. It
`is also possible to fetch the
`column address and the R/W signal simultaneously, fetch the
`row address, column address, and the R/W signal
`independently, and to commence the read/write operation at
`the cycle following a fixed number of clock signals which
`has become the final fetch cycle.
`In addition, instead of the method mentioned above, it is
`possible to fetch the external signals such as the R/W signal
`and the like during a fixed period between cycles, for
`example between the M-th cycle and the N-th cycle. It goes
`without saying that the same data read/write operation can
`also be continued during a fixed period between cycles.
`In FIG. 6, the control method in the first embodiment
`described above is applied to an interleaved type of memory
`device according to a second embodiment of the present
`invention. This diagram shows the main configuration of a
`memory device for which the above-mentioned control
`method functions effectively.
`In FIG. 6, a memory device 10 comprises a memory cell
`group 11, a selection section 12, a specification section 13,
`and a control section 4.
`
`The functions of components in FIG. 6 which bear the
`same reference numbers as components in FIG. 1 have the
`same functions as those components. Further explanation is
`therefore omitted here. In the memory cell group 11, for
`example, a dynamic type memory cell is formed as a block
`and arranged in matrix form. This memory cell also includes
`a column decoder. An example of a specific configuration of
`the memory cell group 11 will be later described. The
`selection section 12 is based on one part of an external basic
`clock signal and an address signal. The respective blocks of
`the memory cell in the memory cell group 11 are interleaved,
`and consecutive selection is activated.
`
`The selection section 12 provides a series of selection
`activation signals (IDA, (ID8, (IDC, and (IDD to the memory cell
`group 11. The specification section 13 specifies the row
`address based on an address signal, and specifies the column
`address of the selectively activated block, based on a signal
`which is one part of the address signal and one part of the
`selection activation signals.
`Specific examples of the configuration of the selection
`section 12 and the specification section 13 will be later
`described. The control section 14 controls the operations of
`the selection section 12 and the specification section 13
`based on the number of cycles of an external basic clock
`signal.
`FIG. 7 is a diagram showing the arrangement of a memory
`cell array mat (a memory cell array) of the memory cell
`group 11. In FIG. 7, the memory cell comprises a total of 16
`memory cell array mats. A plurality of column decoders
`takes up eight columns, each column decoder being inter-
`posed between two memory cell array mats. This memory
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`system performs four separate operations. When a certain
`row address is selected, for example, the cell array mats 1,
`2, 9, and 10 enclosed in the heavy lines in FIG. 7 are
`activated. Specifically, one fourth of the memory cell group
`11 corresponding to row addresses are activated. In FIG. 7
`there are four combinations of parts of the memory cell array
`mats, (1, 2, 9, 10) (3, 4, 11, 12) (5, 6, 13, 14) and (7, 8, 15,
`16).
`FIG. 7 shows the conditions under which the first com-
`
`bination (1, 2, 9, 10) is activated. Part of the memory cells
`which are activated simultaneously, as shown in the example
`in FIG. 7, are divided into equal part cell array blocks, and
`serial access is carried out in the order predetermined for this
`array.
`The example of FIG. 7 is divided into four cell blocks, and
`this selection is performed by means of the selection acti-
`vation signals (IDA, (IDB, (IDC and (IDD.
`the cell array mat
`In the example shown in FIG. 7,
`corresponds to the cell array block one to one.
`In addition,
`the column direction access is serial.
`Accordingly, the input to the column decoder is the output
`from the serial counter. Because the memory arrays 1, 2, 9
`and 10 are interleaved in serial order and accessed, the
`counter output from the serial counter, which is input to the
`column decoders 1 and 5, is also interleaved. This interleav-
`ing operation will be later explained.
`FIG. 8 shows a specific example of one configuration of
`a column decoder used in the semiconductor memory device
`shown in FIG. 6. The configuration of the column decoder
`shown in FIG. 8, shows parts of the column decoders 1, 5
`from FIG. 7 combined. In addition, the DOUT/,N shown in
`FIG. 2A—FIG. 5H is assumed to be an I/O of four bits, and
`the data transmission routes linked to this input/output
`circuit are shown as I/01 to I/04. In addition, a bit line
`constructed from a complementary signal pair, and the
`above-mentioned I/O line, are shown as one line for sim-
`plicity.
`In FIG. 8, a column decoder C/Dn formed from a NAND
`gate is selected by means of serial counter output.
`Subsequently, when the decoder output is at the “L” level
`and the signal (IDA rises, the bit lines B1 to B4 are connected
`to the I/O lines, and data access begins. This is a latch
`circuit, so this selection state is maintained even when the
`signal (IDA enters the “L” level and is maintained until the
`signal (IDA next rises.
`Next, when the signal (IDB rises, the bit lines B1‘ to B4‘ are
`connected to the I/O lines I/01‘ to I/04‘. In this manner, data
`items are transmitted consecutively from the memory arrays
`1, 2, 9, 10 by the consecutive rising of the signals (IDA, (IDB,
`(IDC, (IDD. In addition, the data can be written in through the
`I/O lines in the reverse manner.
`(IDD are
`(IDC,
`(IDB,
`Accordingly,
`if the signals (IDA,
`interleaved, the clock signal can utilize three cycles from the
`initiation of access until the output of the data, as illustrated
`in the lower portion of the timing waveforms of FIGS.
`9A—9K. Accordingly, the data can be output at three times
`the speed set by the circuit operation. In addition, because
`three cycles elapse until the same memory cell array can be
`accessed once again, the data received from an external
`source can be transmitted at a high speed cycle for a write-in,
`in the same manner as for a read-out.
`
`FIGS. 9A—9K show the timing chart for the internal
`signals with interleaving operation,
`illustrating the case
`where interleaving based on four phases of the clock signals
`is