Paper No. ____
`Filed: July 25, 2016
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`Case: IPR2015-01524
`U.S. Patent No. 6,366,130
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`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
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`Case IPR2015-01524
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`TABLE OF CONTENTS
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`B.
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`C.
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`D.
`E.
`F.
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`INTRODUCTION .......................................................................................... 1
`I.
`II. SUKEGAWA AND LU RENDER CLAIMS 1, 2, 5, 6, AND 9
`OBVIOUS ....................................................................................................... 1
`Sukegawa in View of Lu Teaches a “Differential Data Bus” .............. 1
`A.
`Sukegawa’s Signal Lines Constitute a “Bus” ............................ 2
`1.
`2.
`Similar to Other Lines Admitted by PO to be Buses, the
`Pink Lines in Sukegawa Have Nodes ........................................ 6
`Sukegawa in View of Lu Teaches Precharging Two Buses to a
`Voltage Between 0 and Vdd ................................................................. 7
`One of Ordinary Skill Would Have Been Motivated to Combine
`Sukegawa and Lu .................................................................................. 8
`1.
`Sukegawa Does Not Teach Away ............................................. 8
`2.
`One of Ordinary Skill Would Have Been Motivated to
`Modify Sukegawa in View of Lu ............................................. 10
`Sukegawa in View of Lu Would Have Been Workable ..................... 12
`Lu Discloses Precharging ................................................................... 15
`The Combination of Sukegawa and Lu Discloses or Suggests
`the Features of Claim 5 ...................................................................... 16
`Petitioner Did Not Rely on Hindsight ................................................ 18
`G.
`III. SUKEGAWA, LU AND WATANABE RENDERS CLAIM 3
`OBVIOUS ..................................................................................................... 18
`IV. SUKEGAWA, LU, AND HARDEE RENDERS CLAIM 7 OBVIOUS........ 21
`The Hardee Combination Would Have Resulted in Area
`A.
`Savings ............................................................................................... 22
`Latch-up Would Have Been a Concern ............................................. 22
`The Hardee Combination Would Not Have Required Signal
`Boosting .............................................................................................. 23
`Implementing Pull Up and Pull Down Drivers in NMOS Would
`Have Been a Predictable Design Choice ............................................ 24
`V. CONCLUSION ............................................................................................. 25
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`B.
`C.
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`D.
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`TABLE OF AUTHORITIES
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`Case IPR2015-01524
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` Page(s)
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`Cases
`In re ICON Health & Fitness, Inc.,
`496 F.3d 1374 (Fed. Cir. 2007) .......................................................................... 13
`
`In re Keller,
`642 F.2d 413 (C.C.P.A. 1981) ............................................................................ 10
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 12, 24
`
`On-Line Techs., Inc. v. Bodenseewerk Perkin-Elmer GmbH,
`386 F.3d 1133 (Fed. Cir. 2004) .......................................................................... 16
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`ii
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`

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`Exhibit
`No.
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`1001
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`1002
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`1003
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`1004
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`1005
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`1006
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`1007
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`1008
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`1009
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`1010
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`1011
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`1012
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`1013-
`1019
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`1020
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`1021
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`Case IPR2015-01524
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`LIST OF EXHIBITS
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`Description
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`U.S. Patent No. 6,366,130 (“the ’130 Patent”) to Podlesny et al.
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`Declaration of Dr. R. Jacob Baker
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`File History of the ’130 Patent
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`Excerpts from File History of the Inter Partes Reexamination of the
`’130 Patent
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`U.S. Patent No. 5,828,241 to Sukegawa
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`U.S. Patent No. 6,108,254 to Watanabe et al.
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`U.S. Patent No. 6,249,469 to Hardee
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`“Half-VDD Bit-Line Sensing Scheme in CMOS DRAM’s,” IEEE
`Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1984 by
`Lu et al.
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`Excerpts from the Modern Dictionary of Electronics (7th ed. 1999)
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`Excerpts from the IEEE Standard Glossary of Computer Hardware
`Terminology, IEEE Standard 610.10-1994 (1995)
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`Deposition of William R. Huber, D.Sc.
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`Fairchild Semiconductor, Application Note AN-600 Understanding
`Latch-Up in Advanced CMOS Logic, March 1998
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`Reserved
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`United States Patent 6,366,130, Samsung Exhibit 1001, with
`drawings by Dr. Huber
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`U.S. Patent 5,828,241, Samsung Exhibit 1005, with drawings by Dr.
`Huber
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`iii
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`Case IPR2015-01524
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`1022
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`1023
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`Declaration of William R. Huber, D.Sc., P.E. in Support of Patent
`Owner's Response to Petition
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`United States Patent 6,366,130, Samsung Exhibit 1001, with
`drawings by Dr. Huber
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`1024
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`Handwritten drawing by Dr. Huber
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`Case IPR2015-01524
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`I.
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`INTRODUCTION
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`Samsung Electronics Co., Ltd. (“Petitioner”) submits this reply to Patent
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`Owner’s Response (“POR”) concerning claims 1-3, 5-7, and 9 of U.S. Patent No.
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`6,366,130 (“the ’130 Patent”) (Ex. 1001). Patent Owner’s (“PO”) arguments
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`should be rejected and the claims found unpatentable for at least the reasons below
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`and in the Petition (“Pet.”) and accompanying exhibits, the Board’s decision to
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`institute inter partes review (“Dec.”), and the cross-examination testimony.1
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`II.
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`SUKEGAWA AND LU RENDER CLAIMS 1, 2, 5, 6, AND 9 OBVIOUS
`Contrary to PO’s arguments, the evidence shows Sukegawa and Lu render
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`claims 1, 2, 5, 6, and 9 obvious.
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`Sukegawa in View of Lu Teaches a “Differential Data Bus”
`A.
`PO repeats its argument rejected by the Board that Sukegawa and Lu fail to
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`teach a “differential data bus” because Sukegawa’s signal lines highlighted in pink
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`by Petitioner do not constitute a “bus.” POR at 18-26; Dec. at 11, 14; Prelim. Resp.
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`1 Petitioner does not necessarily agree with PO’s representations about the ’130
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`Patent or prior art. POR at 2-5, 13-17. Petitioner also does not agree with PO’s
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`positions regarding the construction of “latching sense amplifier” and “stage”
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`(POR at 9-12) for the reasons set forth in the Petition. Pet. at 8-11.
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`1
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`at 15-16.2 But as explained in the Petition, and below, Sukegawa’s pink signal lines
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`are a “bus.”
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`Sukegawa’s Signal Lines Constitute a “Bus”
`1.
`To begin, contrary to PO’s focus on nodes “C” (POR at 20), Petitioner
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`identified the pink lines as the claimed bus. See Pet. at 19; Ex. 1002, ¶31; see also
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`Dec. at 8. Further, the parties and the Board agree that the term “bus” should be
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`given its plain and ordinary meaning. Pet. at 9; POR at 9-12; Ex. 1011 at 82:1-7;
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`Dec. at 5. “Bus” is a term of art widely used and understood at the time of the
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`alleged invention to be “one or more conductors that are used for the transmission
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`of signals, data, or power.” Ex. 1010 at 13.3 This understanding is consistent with
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`the use of the term in the claims and specification of the ’130 patent. See e.g., Ex.
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`2 The Board also rejected PO’s position that the pink lines are not differential. Dec.
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`at 11, 14. This no longer appears to be a dispute. See Ex. 1011 at 36:19-21, 37:14-
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`38:18; POR at 26 (“Sukegawa nodes C (N3 and N4) exhibit differential
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`voltages.”).
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`3 Ex. 1010 was published by the IEEE in 1995 and defines terms pertaining to
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`computer hardware, including circuit and computer components. Id. at 7.
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`2
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`Case IPR2015-01524
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`1001 at Fig. 1, 2:1-22, 4:2-18. It is also consistent with Petitioner’s expert
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`understanding. Ex. 2003 at 49:4-9, 15-17.
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`PO’s proposed understanding of a “bus” (POR at 22) is flawed as it relies on
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`a definition from a document dated over 13 years after the alleged invention date.
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`See POR at 22; Ex. 2005; Ex. 1001 at 1; Ex. 1011 at 65:24-66:2. Even if
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`considered, PO’s interpretation appears consistent with Petitioner’s understanding
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`(i.e., conductor or path, transfers data, etc.). And as explained in the Petition and
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`below, the pink lines in Sukegawa constitute a “bus” under both parties’
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`understanding.
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`For instance, the pink lines in Sukegawa are conductors consistent with
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`Petitioner’s understanding because these lines are used to carry electrical signals
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`(e.g., voltages) in Sukegawa’s “signal transmission” system and thus conduct
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`electricity. See e.g., Pet. at 19; Ex. 1005 at Fig. 1, 9:14-24; 9:4-7; Abstract. PO’s
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`expert has a similar understanding. See Ex. 1011 at 49:12-20. PO even identified
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`the pink lines as “wires.” Prelim. Resp. at 16.
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`The pink lines are also used for the transmission of signals, data, or power,
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`consistent with Petitioner’s understanding of a “bus.” Sukegawa explains that
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`signals must be transmitted along the pink lines, which are located in the receiver
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`circuit,4 on their path from the input to reach the output of Sukegawa’s “signal
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`transmission” system. Ex. 1005 at 9:14-24, Abstract, Fig. 1. PO’s expert has a
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`similar understanding. See e.g., Ex. 1011 at 56:5-15 (describing the transmission of
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`signals in the circuitry of Sukegawa). See also id. at 37:10-38:18 (indicating
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`“data”)
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`Likewise, Sukegawa’s pink lines are a “bus” under PO’s understanding of
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`the term. The pink lines are a common path along which signals are transmitted
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`between multiple devices. For instance, for a signal to travel from the input, “IN,”
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`to the differential output, “OUT_” and “OUT,” in Sukegawa’s system, the signal
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`4 The pink signal lines in Sukegawa’s “receiver 4” are similar to the embodiment
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`disclosed in the ’130 Patent. For instance, Fig. 2 of the ’130 Patent shows that
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`signals are transmitted from what PO has alleged to be the “differential bus” (lines
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`“LT” and “LC”) through two transistors “N2” and “N3” to what PO has alleged to
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`be the “differential data bus” in “receiver 16” and having nodes “IC” and “IT.”
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`See, e.g., Ex. 1001 at Fig. 2; Abstract; 2:7 (“receiver 16”); 3:7. Likewise,
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`Sukegawa’s Fig. 1 shows that signals are transmitted from the “differential bus”
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`(lines “LINE” and “LINE_”) through two transistors “34” and “35” to the
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`“differential data bus” in “receiver 4” and having nodes “N3” and “N4.” Ex. 1005
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`at Fig. 1.
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`must travel along a common path that includes the pink lines. See, e.g., Ex. 1005 at
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`9:14-24. In doing so, the signal travels from at least two sources, namely transistor
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`34 and transistor 35, to at least two destinations, namely inverter 36 and inverter
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`37. See e.g., id. at 8:59-64, Fig. 1; Ex. 1011 at 37:14-38:18. This is no different
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`than what is disclosed in the ’130 Patent where a signal that traverses what is
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`alleged to be the “differential data bus” must travel from transistor N2 (a “source”)
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`to transistor N8 (a “destination”) and from transistor N3 (another “source”) to
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`transistor N6 (another “destination”). See also POR at 3 (citing Ex. 2004, ¶47).
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`The pink lines in Sukegawa also have “a span” and “act[] like a bridge
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`between two points” as PO contends a “bus” must do. For instance, the pink lines
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`connect or act like a bridge between transistors 34, 38, 39, and inverter 36 as well
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`as between transistors 35, 40, 41, and inverter 37. See Ex. 1001 at Fig. 1; Ex. 1005
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`at 8:59-64. These connections thus span a distance between the aforementioned
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`devices. It is of no import whether Sukegawa discloses specific dimensions of such
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`connections. See Ex. 1011 at 39:9-23 (PO’s expert agreeing the differential bus in
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`Sukegawa has some “finite distance” despite not disclosing specific dimensions).
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`To argue that Sukegawa’s pink lines do not span a distance, PO tries to twist
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`Petitioner’s expert testimony into something that purportedly supports its position.
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`POR at 22-23. PO, however, ignores that Petitioner’s expert also testified that there
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`is a “wire on the input of [inverters] 36 and 37.” Id., citing Ex. 2003 at 48:16-49:2.
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`The record is clear that the pink lines do span some distance. Pet. at 19-23; Ex.
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`1002, ¶31; Ex. 2003 at 50:23-51:25. PO’s argument is also flawed because
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`minimizing parasitics, including those associated with buses, is customary in
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`circuit design generally, including in the ’130 Patent as PO’s expert admits. See
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`Ex. 1011 at 36:6-10. Minimizing area, even in a bus, in no way indicates that the
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`area would not span any distance whatsoever, and PO does not provide any
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`evidence to rebut this understanding.
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`2.
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`Similar to Other Lines Admitted by PO to be Buses,
`the Pink Lines in Sukegawa Have Nodes
`PO attempts to muddy the issue whether Sukegawa discloses the claimed
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`differential data “bus” by interjecting an argument regarding the meaning of
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`“node.” POR at 20-21. But the fact that the pink lines in Sukegawa have nodes in
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`no way precludes these lines from being a “bus.” Indeed, PO’s expert admitted that
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`other signal lines in Sukegawa that also have nodes, constitute a “differential bus.”
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`See Ex. 1011 at 116:14-18, 38:19-21. PO’s expert also agreed that even the
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`“differential data bus” disclosed in the preferred embodiment of the ’130 Patent
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`has nodes. See Ex. 1011 at 115:5-9; Ex. 1001 at 3:7-9. In short, PO’s argument
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`about the pink lines having nodes does not detract from the evidence showing that
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`Sukegawa discloses the claimed differential data bus.
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`B.
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`Sukegawa in View of Lu Teaches Precharging Two Buses to a
`Voltage Between 0 and Vdd
`PO’s argument that Sukegawa does not precharge two buses to a voltage
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`between 0 and Vdd is misplaced. POR at 26-27. Petitioner relied on Sukegawa and
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`Lu, not just Sukegawa for this teaching. As described in the Petition, Sukegawa
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`discloses that the “differential bus” is precharged to Vdd/2, which is a voltage
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`between 0 and Vdd, and the “differential data bus” is precharged to Vdd. Pet. at
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`25-26. One of ordinary skill would have understood that precharging to an
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`intermediate voltage such as Vdd/2 instead of Vdd would have been desirable to
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`speed up the operation of the signal transmission circuit. Ex. 1002, ¶31. PO’s
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`expert acknowledges this in connection with Sukegawa’s disclosure. Ex. 1011 at
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`58:15-59:2. Lu likewise teaches this advantage and others. See e.g., Ex. 1008 at 1
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`(Abstract), 3, § III (listing advantages (1)-(4)). The advantages of intermediate
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`voltage precharging were well-known to those of ordinary skill at the time of the
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`alleged invention. See e.g., Pet. at 26-27; Ex. 1002, ¶31; see also Ex. 1011 at 59:3-
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`15. Given these known advantages, the knowledge of such a skilled person, and the
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`disclosure of Sukegawa and Lu, one of ordinary skill would have had reason to
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`modify Sukegawa to precharge the “differential data bus” to an intermediate
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`voltage Vdd/2. See e.g., Pet. at 25-27; Ex. 1002, ¶31, pp. 28-32.
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`C. One of Ordinary Skill Would Have Been Motivated to Combine
`Sukegawa and Lu
`PO raises several arguments against the combination of Sukegawa and Lu.
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`However, as the Board noted (Dec. at 12-14), and as explained below, a person of
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`ordinary skill would have had sufficient reason to combine Sukegawa and Lu.
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`Sukegawa Does Not Teach Away
`1.
`PO argues one of ordinary skill is taught away from precharging Sukegawa’s
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`“differential data bus” to Vdd/2 allegedly because it teaches precharging that bus
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`to Vdd. POR at 28-30. PO’s argument, if accepted, would mean that one of skill
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`would never implement a change to a circuit disclosed in a reference even if the
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`reference does not criticize the change and there is a benefit to making the change.
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`That is not the law. In fact, the Board has already considered this type of argument
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`in deciding to institute review. See Prelim. Resp. at 21-22; Dec. at 10-11, 13. PO’s
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`argument should be rejected again.
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`Notably, Sukegawa provides no criticism of precharging the “differential
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`data bus” to a value under Vdd, such as Vdd/2. Thus, one skilled in the art would
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`not have been turned away from implementing such features. Instead, as explained
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`above and in the Petition, given the advantages of precharging lines to Vdd/2, as
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`disclosed by Lu, such a skilled person would have been motivated to do the same
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`for Sukegawa’s “differential data bus.” Pet. at 25-27; Ex. 1002, ¶31; supra, Section
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`II.B. The lack of criticism is telling in the context of PO’s position because under
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`PO’s reasoning, the ’130 Patent could be said to teach away from using certain
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`components for disclosed others even when the patent does not criticize such
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`substitutions, such as using PMOS transistors in place of NMOS transistors N1 and
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`N3 (which connect part of the circuit to the voltage supply) where the ’130 Patent
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`discloses using PMOS transistors (e.g., P1, P4-P7) to connect other portions of the
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`circuit to the voltage supply, as illustrated below from PO’s expert’s declaration
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`annotated Figure A.
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`Ex. 2004 at 21, Figure A (further annotated in black).
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`PO’s expert did not subscribe to this logic. Instead, he confirmed that the
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`’130 Patent does not criticize the use of PMOS transistors in place of NMOS for
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`N1 and N3, and that there was nothing to prevent such a substitution. Ex. 1011 at
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`19:14-20:10. Just as PO’s expert agrees that the ’130 Patent does not teach away
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`from using PMOS transistors in place of the NMOS transistors to connect the
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`circuit to Vdd merely by disclosing PMOS transistors to connect other portions of
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`the circuit to Vdd, Sukegawa does not teach away from precharging the
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`“differential data bus” to a voltage Vdd/2 instead of Vdd simply by disclosing the
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`“differential bus” is precharged to Vdd/2.
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`2. One of Ordinary Skill Would Have Been Motivated to
`Modify Sukegawa in View of Lu
`PO’s arguments against the combination of Sukegawa and Lu ignore what
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`the combined teachings of those references would have suggested to those of
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`ordinary skill. See In re Keller, 642 F.2d 413, 425 (C.C.P.A. 1981). One of
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`ordinary skill would have been motivated to combine the teachings of Sukegawa
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`and Lu to obtain a signal transmission system with reduced delay and power
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`consumption. One of ordinary skill would have been motivated to apply Lu to
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`Sukegawa given their overlapping subject matter and the stated benefits of
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`precharging to Vdd/2. See e.g., Pet. at Sec. VII.A, B; Ex. 1002, ¶¶25-29, 31; Ex.
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`2003 at 18:5-19:5; Ex. 1011 at 58:15-59:18. Both Sukegawa and Lu describe signal
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`transmission circuits. Pet. at 12, 25-27; Ex. 1002, ¶¶25-29, 31. Both describe the
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`need to develop such systems with faster speed and lower power consumption. Id.
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`Both teach precharging buses to speed up signal transmission and lower power
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`consumed during such transmission. Id.; Ex. 1005 at 4:25-37; Figs. 10-13, and 16.
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`Sukegawa discloses a system comprising “a driver circuit, a receiver circuit,
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`an equalizer circuit, and an intermediate amplifier circuit.” Pet. at 12; Ex. 1005 at
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`4:62-65. Sukegawa focuses its disclosure primarily on the “wiring electrically
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`connecting [the] driver circuit and receiver circuit,” which has been identified as
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`the “differential bus.” See, e.g., Pet. at 16-18; Ex. 1005 at Abstract. To decrease
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`signal delay and power consumption, Sukegawa
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`teaches precharging
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`the
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`“differential bus” to Vdd/2. Pet. at 11-12; 25-26; Ex. 1005 at 7:26-37. Indeed, by
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`precharging the “differential bus” in this manner, Sukegawa is able to increase the
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`speed by about 10% and reduce power consumption by about 30-40% over
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`conventional signal transmission circuits. See Ex. 1005 at 4:25-37; Figs. 10-13, and
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`16. Sukegawa’s additional bus (“differential data bus”) is also precharged (to Vdd).
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`Pet. at 26; Ex. 1002, ¶31; Ex. 1005 at 9:4-7. Moreover, one of ordinary skill would
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`have further recognized Lu’s teachings that signal delay and power consumption
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`could be reduced by generally precharging buses to an intermediate voltage. See
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`supra Section II.B.
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`Based on such disclosures, one of ordinary skill would have realized that by
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`precharging the “differential data bus” to Vdd/2 like the “differential bus,” similar
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`reductions in signal delay and power consumption, among others advantages,
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`could also be obtained. Pet. at 11-12, 25-27; Ex. 1002, ¶31. Thus, one of ordinary
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`skill would have modified Sukegawa to precharge the “differential data bus” to
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`Vdd/2. Id. See also Ex. 2003 at 76:20-77:4 (agreeing that a person of skill would
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`recognize using Vdd over two on the differential data bus), 77:24-78:11, 79:15-
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`81:23. Indeed, such a skilled person would have recognized, based on the
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`Sukegawa and Lu disclosures, that doing so would have amounted to nothing more
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`than the use of a known technique to improve similar devices in the same way and
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`would have yielded nothing more than predictable results. Id.; KSR Int’l Co. v.
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`Teleflex Inc., 550 U.S. 398, 417 (2007).
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`Sukegawa in View of Lu Would Have Been Workable
`D.
`PO argues that the Sukegawa and Lu combination is unworkable. POR at
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`30-34. This argument is flawed in multiple respects. First, PO does not and cannot
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`argue that the Sukegawa and Lu combination would be inoperable. Second, PO’s
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`argument is premised on the assumption that the Sukegawa and Lu system would
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`have been designed poorly. POR at 32-33 (citing testimony of Petitioner’s expert
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`(Ex. 2003 at 85:6-9), where he discussed issues “[i]f the circuit isn’t designed
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`correctly,” see also id., 83:5-11). PO fails to explain that even a poorly designed
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`system would have been inoperable. Further, the combination of Sukegawa and Lu
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`is not premised on an incorrect design, but instead takes into account the
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`knowledge and abilities of one of ordinary skill in the art at the time of the alleged
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`invention. Pet. at 9 n.5 (citing Ex. 1002, ¶15); Ex. 1002, ¶31; Ex. 2003 at 79:15-
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`81:23 (explaining that one skilled in the art would have been able to make the
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`adjustments to accommodate the modification to Sukegawa), 75:9-16 (explaining
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`that one skilled in the art would make adjustments to inverters 36 and 37 so that
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`would function properly), 77:24-78:11 (explaining that one of ordinary skill would
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`design the modified Sukegawa system to work), 109:23-110:8 (explaining how one
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`skilled in the art reading Sukegawa would understand what Logic 0 is and what a
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`Logic 1 is), 63:20-64:1, 64:7-12. See also In re ICON Health & Fitness, Inc., 496
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`F.3d 1374, 1382 (Fed. Cir. 2007).
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`It is axiomatic that in the design and implementation of circuits, the
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`dimensions and type of transistors, the supply voltages, and other aspects are
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`considered. This goes for the implementations of the circuits described in the ’130
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`Patent, the circuits described in Sukegawa, Lu, and the rest of the prior art in this
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`proceeding. See e.g., Ex. 1011 at 34:7-22 (PO’s expert explaining that transistor
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`size, technology, and “a whole raft of things that enter into the design of the
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`circuit” would dictate the capacitance of IT and IC in the ’130 Patent), 35:16-
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`36:10. Indeed, the ’130 Patent does not indicate the specific width or length
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`dimensions of the many disclosed transistors or the threshold voltages of the
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`specific transistors. Yet, PO does not suggest that its own disclosed circuits are
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`beyond the knowledge of those skilled in the art. Nor can it make the same claim
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`against Sukegawa and Lu. To the contrary, PO acknowledges with respect to
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`Sukegawa and Lu that the transistors could have different sizes. See, e.g., POR at
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`Case IPR2015-01524
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`32 (“ΔV [is] an amount determined by the relative sizes of transistors 38 and 39
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`(and 41 and 40).”).
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`PO’s complaint of “undesirable current paths” that allegedly cause the
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`voltage on nodes N3 and N4 to rise by an amount ΔV” (POR at 31-32) ignores the
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`testimony of Petitioner’s expert that one of ordinary skill would have known
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`multiple ways to minimize any such ΔV and related current. For example,
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`Petitioner’s expert explained that by making transistors 39 and 40 weaker (e.g.,
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`having a longer transistor length, L), ΔV and the related current that PO complains
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`of could be minimized. Ex. 2003 at 83:12-84:14; see also Ex. 1011 at 109:9-14. He
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`also explained that by making transistors 39 and 40 to have a higher threshold
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`voltage, ΔV and the related current that PO complains of could be minimized. Ex.
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`2003 at 84:6-23. Likewise, PO’s complaints regarding bias issues (POR at 32) also
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`disregard the testimony of Petitioner’s expert that ways to minimize ΔV and any
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`such related current would have been in the realm of one of ordinary skill and
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`easily minimized. Ex. 2003 at 78:5-11; see also Ex. 2003 at 79:21-80:12; 83:8-11;
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`83:18-84:23. Further, PO fails to acknowledge advantages, such as reduced delay
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`and power consumption, achieved by modifying Sukegawa in view of Lu. One of
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`ordinary skill would have understood these advantages, would have been
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`motivated to combine the teachings of Sukegawa and Lu, and that system would
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`have been desirable and operable. Pet. at 11-14; 25-27; Ex. 1002, ¶¶29, 31.
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`14
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`Case IPR2015-01524
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`Lu Discloses Precharging
`E.
`PO’s arguments that Lu fails to disclose a precharge source or a “fixed”
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`single value should be rejected. See POR at 34-37.
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`As to PO’s first argument, Lu discloses a “voltage precharge source.” To
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`illustrate, Lu discloses two mechanisms for precharging to Vdd/2, namely via (1) a
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`bit-line shorting mechanism or (2) a voltage regulator. See, e.g., Ex. 1008 at 1
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`(“The bit lines are precharged to a reference voltage approximately equal to Vdd/2,
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`which can be obtained from a voltage regulator as suggested by Foss and Harland
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`[3], or by shorting two bit-line halves after restoring the signal [1], [2].”)5 See also
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`Ex. 2003 at 18:5-19:5.
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`In the voltage regulator mechanism, a voltage precharge source, Vref, is
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`used to precharge at that same level Vref. Ex. 1008 at Fig. 1 (showing voltage
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`precharge source “Vref”). Alternatively, in the bit-line shorting mechanism, two
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`source voltages are used to precharge to a level midway between those source
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`voltage levels. Ex. 1008 at 2 (“At the end of the previous active cycle, one bit-line
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`half is at VDD and the other is at 0 V. A precharge of the bit line before sensing is
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`initiated by switching on Φ3 to turn on the equalization device QEQ, which shorts
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`5 Sukegawa also discloses a voltage precharge source. See Pet. at 16; Ex. 1002,
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`¶31.
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`Case IPR2015-01524
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`two bit-line halves together. The charge sharing between two bit-line halves results
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`in a precharge level at nearly half VDD.”) (emphasis added).
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`PO’s second argument that the voltage level to which precharging occurs
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`must be “fixed at a single value” (POR at 35-37) is an example of PO
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`impermissibly reading limitations into the claims. PO explains that by “fixed,” it
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`means the precharging level is not “approximate” and cannot deviate whatsoever
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`from this “fixed” value. See Ex. 1011 at 111:14-20 (PO’s expert alleging why he
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`believes that the precharge value relating to Lu’s bit-line shorting precharging
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`mechanism did not meet the claim limitation because it is “not a fixed value”); see
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`also id. at 113:24-114:5. However, such a limitation appears nowhere in the
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`challenged claims. Further, adopting such a limitation would improperly read out
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`the preferred embodiment of the ’130 Patent which discloses that the precharge
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`voltage, Vpr, deviates and is approximate. See, e.g., Ex. 1001 at 3:4-9, 3:52-55.
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`See also On-Line Techs., Inc. v. Bodenseewerk Perkin-Elmer GmbH, 386 F.3d
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`1133, 1138 (Fed. Cir. 2004).
`
`F.
`
`The Combination of Sukegawa and Lu Discloses or Suggests the
`Features of Claim 5
`PO argues that Petitioner fails to show Sukegawa and Lu discloses or
`
`suggests a precharge voltage less than a logic high voltage or greater than a logic
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`low voltage, as recited in Claim 5. POR at 37-42. PO is wrong. Petitioner
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`explained that the “differential bus” LINE and LINE_ in Sukegawa gets
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`precharged to a voltage less than a logic high and greater than a logic low as the
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`bus lines are precharged to an intermediate voltage source Vdd/2 provided by BLR
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`(i.e., the voltage precharge source). Pet. at 29; Ex. 1005 at 7:26-37, 8:28-31, 9:14-
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`21; Ex. 1002, ¶33.
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`In fact, an example PO provides in its Response actually supports
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`Petitioner’s position that one of ordinary skill would have understood that in a
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`signal transmission system with power supply voltage Vdd, Vdd/2 is less than a
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`logic high voltage and greater than a logic low voltage. Pet. at 29; Ex. 1002 at ¶33.
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`Specifically, as shown below, PO’s example based on JEDEC 1984 (Ex. 2006)
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`confirms that Vdd/2 (the precharge voltage in the Sukegawa and Lu combination)
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`was known to be less than a logic high voltage (“VIH”) and greater than a logic low
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`voltage (“VIL”).6 See POR at 38-40. As shown, the 1.65 V power supply voltage
`
`(Vdd) / 2 value is higher than the 0.8 V VIL value and lower than the 2.0 V VIH
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`value.
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`
`
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`6 While JEDEC 2005 document is dated in 2005, given that PO relies on the
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`document (albeit incorrectly), Petitioner shows in the table how that document also
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`shows similar Vdd/2 value characteristics.
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`Case IPR2015-01524
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`Voltage Parameter
`Maximum logic low voltage, VIL (max)
`Minimum logic high voltage, VIH (min)
`Power Supply Voltage
`(Power Supply Voltage) / 2
`
`G.
`Contrary to PO’s assertion, Petitioner did not rely on hindsight. Instead, one
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`JEDEC 1984
`0.8 V
`2.0 V
`3.3 V
`1.65 V
`
`JEDEC 2005
`0.2 * Vdd
`0.8 * Vdd
`Vdd
`0.5 * Vdd
`
`Petitioner Did Not Rely on Hindsight
`
`of ordinary skill would have been motivated to combine the teachings of Sukegawa
`
`and Lu as explained in the Petition and above. For example, both Sukegawa and Lu
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`disclose signal transmission systems. Pet. at 11-12, 25-27; Ex. 1002, ¶31. Both
`
`references disclose the precharging of buses to reduce delay in the signal
`
`transmission. See id. While Sukegawa describes how precharging the “differential
`
`bus” to an intermediate voltage can help reach this goal, Lu discloses how
`
`precharging buses
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`to an
`
`intermediate voltage generally can offer
`
`these
`
`improvements. See e.g., Pet. at 25-27; Ex. 1002, ¶31; Ex. 1005 at 4:25-37; Figs.
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`10-13, 16; Ex. 1008 at 1, 3. As explained in the Petition, one of ordinary skill
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`would have had reason to modify Sukegawa in light of Lu to arrive at the claimed
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`subject matter. Id.; Dec. at 12.
`
`III. SUKEGAWA, LU AND WATANABE RENDERS CLAIM 3 OBVIOUS
`PO’s argument that Sukegawa, Lu, and Watanabe (the “Watanabe
`
`combination”) fails to show “each source terminal of the input pass transistors is
`
`coupled to an input” and the “drains of input pass transistors coupled to the drains
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`of the cross-coupled latch” (POR at 46-50) is based on an unreasonable narrow
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`interpretation of “coupled” to mean “directly connected.” Under PO’s reasoning,
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`claim 3 requires that each input pass transistor source terminal (labeled “S” below)
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`be “directly connected” to an input (e.g., “LT” and “LC”).
`
`
`Ex. 2004, ¶83. But PO’s narrow interpretation reads out a preferred embodiment of
`
`
`
`the ’130 Patent, which describes the following operating modes:
`
`i.
`
`a mode where the bus drivers are in precharge phase and sense amplifier is
`
`in data transfer phase; Ex. 1001 at 2:12-22; 2:41-45; 2:60-3:3; and
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`ii.
`
`a mode where the bus drivers are in data transfer phase and sense amplifier
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`is in precharge phase. Id. at 2:12-13; 2:23-38; 2:41-59.
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`See also Pet. at 5; Ex. 1002, ¶18.
`
`Depending on the operating mode, the voltages applied to the pass transistor
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`terminals differ. This is important because the identification of “source” and
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`Case IPR2015-01524
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`“drain” terminals depends on the voltages applied to these terminals. See POR at
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`48-49 (“For an NMOS transistor, the drain is identified as the terminal
`
`(considering source and drain) with the more positive voltage. For a PMOS
`
`transistor, the drain is i