SAMSUNG EXHIBIT 1024
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
`
`Page 1 of 5
`
`

`
`IEEE JOURNAI. or SOLID-STATE CIRCUITS, VOL. 5019, NO. 4, AUGUST 1984
`
`451
`
`Papers
`
`
`
`Half-VDD Bit—Line Sensing Scheme in
`CMOS DRAM’s
`
`NICKY CHAU-CHUN LU, MEMBER, IEEE, AND HU H. CHAO, MEMBER, IEEE
`
` I
`
`FROM X Z
`oscoorn
`
`V55
`
`NUDE i OHS
`
`CELL AND
`MODE 2
`
`\O0 nS
`
`Fig. 1.
`
`Schematic of the NMOS half—VD,, bit—line sensing circuitry with
`‘
`associated timing signals [3}.
`
`2) for static pull-up loads [41, dc power is consumed on
`the low bit—line side. For an active restore circuit [5]. the
`timing control is sensitive. Without pull-up circuits, only
`partial signal is restored and both sensing speed and sensi-
`tivity are degraded because of voltage droop at two sensing
`nodes, due to latch-device gatocapacitance coupling as
`latching speed is fast (Fig. 3).
`Recently, CMOS is beginning to be used in DRAM
`designs. Advantages include decreasing the radiation-im
`duced soft errors and isolating cells from substrate noise by
`putting the array in a well, reducing the number of clock
`generators in peripheral circuits, and obtaining lower
`standby power
`[6],
`[7]. For grounded-substrate 11-well
`CMOS technology, an NMOS array may be difficult to use
`because minority carrier
`injection due
`to localized
`forwardbiasing of junctions will cause destruction of stored
`
`Abstract —A sensing scheme in which the bit line is precharged to half
`VDD is introduced for CMOS DRAM’s. The study shows that the half- V0,,
`bit-line sensing scheme has several unique advantages, especially for high-
`performance high-density CMOS DRAM’s, when compared to the full- VDD
`hit-line sensing scheme used for NMOS memory arrays or the grounded
`bit-line sensing scheme for PMOS arrays in CMOS DR4.M’s.
`
`I.
`
`INTRODUCTION
`
`N this paper a sensing scheme for CMOS DRAM’s in
`which the bit line is precharged to half V0,,
`is intro-
`duced. The study shows that half-VDD bit-line sensing has
`several unique advantages, especially for high—performance
`high—density CMOS DRAM’s, when compared to the full-
`VDD bit—Iine sensing scheme used for NMOS memory
`arrays or the grounded bit-line sensing scheme for PMOS
`arrays in CMOS DRAM’s (n-well CMOS technology is
`assumed in this paper).
`The half» VDD bit-line sensing was used in early NMOS
`DRAM chips with 4 kbits [1]—[3]. One of the most widely
`used variants is shown in Fig.
`1
`[3]. The bit lines are
`precharged to a reference voltage approximately equal to
`VDD/2, which can be obtained from a voltage regulator as
`suggested by Foss and Harland [3]. or by shorting two
`bit-line halves after restoring the signal [1], [2]. After the
`sense latching clock Q35 is activated, the load clock ID,‘
`is
`turned on, pulling up the high bit line to fully overdrive the
`cross-coupled latch and also to restore a full signal. After
`the 4 kbit NMOS DRAM generation, a 5 V—only VDD
`power supply was widely adopted. Sensing was converted
`to full-VDD bit-line precharge, sometimes with an active
`restore circuit, such as shown in Fig. 2 [4] or in Fig. 5 of
`[S], to obtain sufficient overdrive on the NMOS latch for
`higher speed and to restore the full signal. Half-VDD bit-line
`sensing lost its importance in NMOS DRAM’s because of
`the following disadvantages:
`1)
`there is less overdrive on the NMOS latch,
`degrading the latching speed: and
`-
`
`thus
`
`Manuscript received October l7. 1983; revised December 22, 1983.
`The authors are with IBM T. J. Watson Research Center, Yorktown
`Heights, NY 10598.
`
`0Ol 8-9200/84/0800—O451$01.00 ©1984 IEEE
`
`Page 1 of 4
`
`SAMSUNG EXHIBIT 1008
`
`Page 2 of 5
`
`
`Page 2 of 5
`
`

`
`452
`
`user»: JOCRNAI. or SOLID~STATE CIRCUITS, VOL. sc-19, NO. 4, AUGUST 1984
`
`1
`O
`0
`
`1
`
`C
`
`o
`
`‘T
`
`0
`
`O
`
`l
`
`'
`
`C
`
`i
`
`J
`2
`
`L
`3
`
`4
`4
`
`-
`O
`2
`Z
`R
`Lu
`U7
`5
`V5
`§
`2
`-
`§
`5
`‘$’
`<(
`El
`n:
`
`3
`
`‘
`
`—
`
`!
`4
`.
`t
`:5
`
`*
`‘l
`
`r
`
`0
`
`ClRCUlT TYPE
`PMOS
`2 NMOS lalth and PMOS pilii-up
`l VMON Ieltli with-int
`77ulI»Utv It \\\,l\ (in: NM()S 4YfI‘v
`O€\|\.ts Hui NMOS Arms‘ using
`»
`v Mm tin -‘W nmmrzu
`»;,,, hi!-hm. pfLs,h.sI’fi\'l
`I’Vl( )\. Hid‘.
`rid ‘vM( )5 puH—dL)Wrt
`5 NMHS huh and VMC H nu!‘-up
`ll‘ ‘ "t ‘ “"5 PM‘ 7‘ 1'51)’ "V"!
`dents» blur PKM V\
`.irv.iv menu
`L'll7LlMd(L' m—m,t
`[V.:hivvy:t1
`Mint 15,, p...;.,.. ,,,.__.‘_..m
`
`0
`-
`E
`E:
`0
`(0
`Z
`2
`W
`~
`,_
`‘S
`<
`E
`
`I
`
`[
`1
`0 t
`C
`
`1
`
`Fig. 3. Sensing speed‘ and minimum sensible signalz (both in normal-
`ized linear scale)
`for different cross—coupled sense amplifiers with
`device mismatches. Depletion NMOS decoupling transistors are used.
`
`
`
`at
`
`~—4[}<uTL—-o
`tit
`@l
`l
`
`(P1
`Fig. 4. Schematic of the CMOS half-VDD bit»line sensing circuitry.
`and (D2 clocks are used for multiplexing bit lines. <93 clock controls the
`equalization device and <l’>_, clock is used to establish the reference
`voltage.
`<1)‘ and (P5
`are complementary clocks to control
`the sense-
`amplifier latching (1137), is the column-selection clock.
`
`complementary sense amplifier consisting of NMOS and
`PMOS cross—coupled pairs, 2) clocked pulldown of the
`latching node, 3) complementary clocking of the PMOS
`pullup. 4) full-sized dummy cell generation of reference
`potential for sensing, 5) shorting transistor to equalize
`precharge potential of bit lines, and 6) depletion NMOS
`decoupling transistors for multiplexing bit lines (4 and 6
`are not mandatory).
`The operation of the circuit is described by the simulated
`waveforms in Fig. 5. At the end of the previous active
`cycle, one bit-line half is at VDD and the other is at 0 V. A
`precharge of the bit line before sensing is initiated by
`switching on CD3
`to turn on the equalization device Q EQ,
`which shorts two bit-line halves together. The charge shar-
`ing between two bit—line halves results in a precharge level
`at nearly half VDD. The reference voltage established on a
`full—size dummy cell is obtained by activating (D4
`to turn
`on QD5 for charge sharing between two dummy cells (QD1
`
`1Time for a differential signal of 0.3 V to be amplified to 2.5 V across
`two bit—line halves.
`21-Iigh-performance design.
`
`Van
`
`‘$2
`
`('.‘vE
`
`$0 —-'T—‘ T C?
`*1
`§ azrenencz
`CELL
`
`Ca 7
`
`
`
`dm —T-——
`it.’
`T
`STORAGE Q
`CELL
`
`Cs
`
`I
`
`/I
`
`1
`i
`
`,
`»
`._
`
`i
`l
`l
`
`F
`"
`
`5 I
`
`l
`'
`I
`l
`;
`
`__
`CE
`
`$1
`
`¢2
`
`‘
`
`r
`
`;
`F’
`I
`I
`.
`.
`
`31.2
`
`:
`1
`p
`>
`E
`i
`.'
`i
`‘
`'
`:
`-
`ii
`E
`Schematic of the NMOS VDD bit»line sensing circuitry with
`associated timing signals [4].
`
`Fig. 2.
`
`
`
`information in the array [8].‘ If a PMOS array in the well is
`used. full— VDD bit-line preeharge is not desirable because it
`gives large junction capacitance and high sensitivity of the
`junction capacitance to voltage variation. which can in-
`crease sense-amplifier mismatch and any word-line noise
`can easily cause stored charge leakage. For grounded bit-
`line precharge, a PMOS cross-coupled latch must be used.
`which has slower sensing speed even when used with an
`NMOS restore circuit (Fig. 3). This is because the PMOS
`device has lower mobility and higher threshold voltage,
`since it is also used as cell transfer device? In comparison,
`half-V0,) bit-line sensing gives almost the same speed for
`the latching operation. as shown in Fig. 3. Although the
`NMOS cross—coupled latch with PMOS restore circuit using
`VDD precharge is fastest, the NMOS array may be difficult
`to use for grounded-substrate n-well CMOS technology.
`
`I]. CMOS HALF-VDD BIT—LINE SENSING
`CIRCUITRY
`
`The proposed CMOS sense-amplifier circuitry for the
`half-VDD sensing scheme using a PMOS memory array is
`shown in Fig. 4. It incorporates the following features: 1) a
`
`‘Applying a substrate bias in n-well CMOS has the advantages of
`relaxing the constraints of junction fOfW3.Td'lDl£LS111g and latchup, decreas-
`ing the junction capacitanocs, and reducing the substrate sensitivity of the
`threshold voltage, thus allowing high-performance peripheral circuits. If
`the system solution to the soft error problem is acceptable to the memory
`applications [9]. use of an NMOS array may be considered due to some
`superior device characteristics.
`3Uriless an extra mask plus ion—implantation is used to generate a
`second PMOS threshold voltage.
`
`Page 2 of 4
`Page 3 of 5
`
`
`Page 3 of 5
`
`

`
`LU AND CHAD: HALF V3,, BIT-LINE smsmc sci-n=..~rr
`
`453
`
`VOLTAGE
`
`(V)
`
`TIME (nsecl
`
`Fig. 5. Simulated waveforms for the CMOS half-VDD sensing circuitry.
`Refer to Fig. 4 for node numbers.
`
`and QD2), one having a stored high and the other a stored
`low level. READ can be performed by selecting a word line
`and the corresponding dummy word line (DWLI), which
`establishes a differential signal on the two sensing nodes (4
`and 5) of the flip-flop pair. The worst-case charge transfer
`is to read the stored low level or 0 V, which starts after the
`word line is pulled down to (VDD/2)- ]V,.,,|, where V7,.
`is
`the PMOS threshold voltage. The stored charge is fully
`transferred to the bit line without threshold loss even if the
`
`word line is not boosted. The word-line boosting can be
`used subsequently for restoring the full signal (0 V) into
`the cell and does not delay the read access time.
`To amplify the signal, the NMOS crosseoupled pair (Q1
`and Q2) and the PMOS cross-coupled pair (Q3 and Q4)
`are switched on by <l>_, and its complementary signal <13”),
`respectively. The NMOS latch gives fast initial sensing.
`The PMOS cross-coupled pair pulls up the high bit-line—half
`to give full overdrive on the latch and full signal for
`restoring. The PMOS cross-coupled pair also pulls up the
`voltage droop at the high sensing node (5 in Fig. 5) due to
`the gate capacitance of the NMOS cross—coupled transis-
`tors, which can seriously degrade the sensitivity of the
`sense amplifier, especially for high performance. To activate
`a PMOS cross-coupled latch in the grounded bit-line sens-
`ing scheme,
`the latching node charges from 0 to 5 V;
`however, the half- VDD sensing is activated by discharging
`the latching node only from V0,)/2 to O V, thus reducing
`the voltage droop at the two sensing nodes. Since half- V5,,
`is close to the switching point of both the NMOS and
`PMOS cross-coupled pairs. the active pullup of the droop-
`ing voltages at two sensing nodes by the PMOS cross-cou-
`pled pair is more effective. As a result, the sensitivity of the
`sense amplifier is also improved (Fig. 3).
`
`III.
`
`FEATURES or HAL!-‘—VDD BlT—Llne Sensing
`
`As mentioned earlier, the half- VDD bit-line sensing gives
`almost the same latching speed as grounded bit-line sens-
`ing, as shown in Fig. 3, because NMOS devices are used in
`the sensing latch and the PMOS cross-coupled pair can
`effectively avoid the voltage droop on the two sensing
`
`Page 3 of 4
`
`for
`nodes and also supplies sufficient overdrive. Also,
`half—l/DD bit-line sensing,
`the stored charge can be fully
`transferred onto the bit lines during the read cycle without
`boosting the word line. If a boosted word line is used to
`store a full-level charge into the cell, the boosted level is
`needed only during the restore period,
`thus causing no
`extra delay during read access due to boosting. This makes
`the word line boosting attractive using the half-VDD sens-
`ing scheme. By comparing the speed of a complete charge
`transfer from the memory cell to the bit lines, the half- VDD
`sensing scheme has a much faster rate than the grounded
`bit-line sensing scheme because the complete transfer can
`start when the word line is pulled down to one lVT,,| below
`VDD/2 rather than being boosted down below 0 V in the
`grounded bit-line sensing scheme. As a result, the elapsed
`time from word-line activation to turning on the bit switch
`is faster in the half-VDD bit-line sensing scheme.
`In addition, the NMOS cross-coupled pair and the PMOS
`cross-coupled pair form a complementary pair, which does
`not have dc power dissipation and can be clocked simply.
`In CMOS DRAM’s, therefore, half- V50 bit-line sensing
`has none of the disadvantages which it has when used in
`NMOS DRAM’s and also shows advantages in comparison
`to the grounded bit-line sensing scheme. It has other addi-
`tional advantages, which are very important for high-den-
`sity high—performance DRAM design:
`1) Reduces the peak currents at both sensing and bit-line
`precharge by almost a factor of two due to the half- VDD
`swing, which reduces the electrornigration problem and the
`IR drop. The chip reliability can be increased and the
`resulting narrower metal lines decrease the parasitic wiring
`capacitances thus giving better speed.
`2) Reduces the d1/dt by a factor of two during bit-line
`precharge and discharge if the time is fixed, which de-
`creases the voltage bouncing noise due to wiring induc-
`tance. lf the voltage bouncing is not the limit, the pre-
`charge and discharge time can be shortened by a factor of
`two.
`
`3) Reduces the ac power for charging and discharging
`the bit lines because the precharge voltage is obtained by
`charge sharing between the two bit-line halves instead of
`charging bit lines to VDD.
`4) Atsensing and bit-line precharge in half- VDD sensing,
`the pullup and pulldown of bit lines are balanced and have
`only ha1f—VDD swing. By using folded bit lines, coupled
`noises due to bit-line swing to the memory cell plate, the
`array substrate, and word lines can be largely reduced due
`to local cancellation. This also relaxes the requirement of
`using a low-impedance cell plate. Even if the plate has
`voltage bumping (for example, write at high plate voltage
`and read at low plate voltage), there will be no significant
`signal loss because the cell transfer device is operated in
`the linear region in half- VDD sensing.
`In contrast,
`in
`grounded bit-line sensing, only one of the two segments of
`bit lines is pulled up (at sensing) or down (at precharge) by
`full-VDD, which gives much larger coupling noises. The
`signal
`loss due to plate voltage bumping is also larger
`because the cell transfer device is operated in the satura-
`tion region.
`
`Page 4 of 5
`
`
`Page 4 of 5
`
`

`
`454
`
`IEEE JOURNAL or soup-srsre Crkcurrs. VOL. sc—19, NO. 4, AUGUST 1984
`
`The only drawback may be a longer period of bit—line
`floating such that
`the bit-line precharge levels can be
`perturbed to cause mismatch due to radiation noise, sub-
`strate noise, and leakage effects. However. studies show
`that this is tolerable by using the following design ap-
`proach, some of which is unique to CMOS technology:
`1) Use folded metal bit
`lines to minimize the noise
`mismatch between two halves and also to minimize the
`
`junction area which reduces the leakage, substrate noise,
`and radiation noise.
`
`2) Use a PMOS array in an n-well such that the p ‘ ~n
`junctions are protected by the n-well. This reduces the
`leakage current, the substrate noise, and radiation-induced
`soft error rates.
`3) Keep the bit-line equalization device. on until just
`before the word-line activation. Differential noises occur-
`ring on a bit—line half during precharge will be distributed
`over
`the two halves in a common mode to minimize
`mismatch. The noise distribution is fast because the metal
`
`bit line gives very small resistance. For example. if a PMOS
`equalization device has W/L=4 }LIT1/ 1.2 pm and each
`bit-line half has 200 F, a 500 nA 10 ns square-pulse noise
`gives less than 3 mV mismatch noise which decays with a
`time constant of 2 ns.
`
`4) Use a dummy cell to generate the reference potential
`so that the absolute bit-line precharge level and the word-
`line to bit-line coupling noise causing sensing signal mis-
`match are not crucial at least to first-order.
`5) Use distributed refresh to shorten the time of bit—line
`floating at chip standby.
`
`V}. CONCLUSION
`
`The use of a half- VDD bit-line sensing scheme in CMOS
`DRAM’s has been described. It shows several advantages
`over the grounded bit-line sensing schemes used in existing
`CMOS DRAM’s. The half-VD,/, sensing has not been em-
`ployed in NMOS DKAM’s with chip density larger than 16
`kbits; however,
`in CMOS DKAM’s,
`the following ad-
`vantages have been demonstrated:
`1) Comparable sensing speed with better sensitivity of
`sense amplifier.
`2) Complete charge transfer can be :.read from the cell
`without word-line boosting provided that g ’T,,} is less than
`3)),/2 minus the sensing signal which depends on the
`charge transfer ratio.
`3) Faster when compared to the word-line boosting 7
`scheme to read full signal.
`4) Delayed word-line boost for full-signal restoring gives
`no penalty on read speed.
`5) Smaller peak currents at both sensing and bit—line
`precharge.
`6) Smaller ac power consumption for bit-line charge and
`discharge.
`7) Smaller dI/dz,
`wiring inductance.
`the array
`8) Smaller coupling noises to the cell plate,
`substrate, and word lines because of balanced bit-line
`swing.
`9) Less signal loss due to cell-plate voltage bumping.
`
`thus smaller bouncing noise due to
`
`ACKNOWLEDGMENT
`
`The authors wish to thank Drs. L. M. Terman and H. N.
`
`Yu for many helpful discussions and support of this study.
`
`REFERENCES
`
`l5}
`
`ll] K. U. Stein. A Sihlin , and E. Doering. “Storage array and sense/re
`fresh circuits for sing e-transistor memory cells.” IEEE J. Solid~Szaze
`Circuits, vol. SC—7, pp. 336—340, Oct. 1972.
`[2] K. U. Stein and H. Friedrich, “A 1 mi.‘ singletransistor memory
`cell in n silicon-gate technology,“ IEEE J. Solid-State Circuits, vol.
`S08. 13
`. 319-323, OcL 1973.
`[3] R. C.
`oss and R. Harland. “Peripheral circuits for one-transistor
`cell MOS RAM’s," IEEF J. S0Zid—SIute Circuits, vol. SC-10, pp.
`255-261, Oct. 1975.
`[4] C. N. Ahlquist, J. R. Breivogel, J. T. Koo, J. L. McCollum. and
`W. G. Oldham. “A 16384-bit dynamic RAM,” IEEE J. Solid—State
`Circuits, vol. SC-11, pp. 570-574, Oct. 1976.
`5. S. Eaton, “A 5 \-only 2K>’.8 dynamic RAM.” in Proc.
`ISSCC. 1979, p. 144-145.
`{6} K. Shimohigas
`. H. Masuda, Y. Karnigalri, K. ltoh, N. Hashimoto,
`and E. Arai, “An n-well CMOS dynamic RAM,” IEEE J. Solid-State
`Circuits, vol. SC~17, pp. 344-348. Apr. 1982.
`{7} R. Chwang. M. Choi, D. Creek, 3. Stem, P. Pelley. J. Schutz, M.
`Bohr, P. Warlcentin, and K. Yu, “A 70 ns high density CMOS
`DRAM.” in Prue. IEEE ISSCC. 1983, pp. 56-57.
`{8} H. Masuda er al., “A S V-only 64K dynamic RAM based on ffigh
`S/N design," IEEE J. Solid-Stale Circuits, vol. SC-15. pp. 846-854.
`Oct. 1980.
`{9} D. C. Bossen and M. Y. Hsiao. “A system solution to the memory
`soft error problem." IBM J. Res.
`I)eueIop.. vol. 24. no. 3. pp.
`390-397, 1980.
`
`IEEE
`
`
`
`Nicky Chan-Chun Lu (M’82) received the B.S.E.E.
`from National Taiwan University, Taipei. Re-
`public of China,
`in 1975. and MS. and Ph.D.
`degrees in electrical engineering from Stanford
`University, Stanford. CA, in 1978 and 1981. re-
`spcctively.
`From 1975 to 1977, he served ROTC service in
`the Chinese Air Force. From 1977 to 1981, he
`was a Stanford Fellow and then Research Assis-
`tant at
`the Integrated Circuits Laboratory at
`Stanford University. He was Visiting Associate
`Professor at the Institute of Electronics, National Chiao-Tung University,
`and Lecturer at Electronic Research and Service Organization. ITRI,
`Taiwan. ROC, from 1981 to 1.982. He is now a Research Staff Member at
`IBM Thomas J. Watson Research Center, Yorktown Heights, NY, His
`current technical interests focus on the design of high-performance VLS1
`MOS memory chips, exploratory silicon devices and technology, and
`physics of polysilicon devices. in these
`he has published 24 papers
`and filed 21 invention disclosures for patent applications.
`Dr. Lu is a member of Sigma Xi and Phi Tau Phi.
`
`
`
`Hu H. Chao (M’8l) was born in the Republic of
`China on June 12, 1947. He received the BS.
`degree in electrical engineering from National
`Taiwan University in 1968.
`the ME. degree in
`electrical engineering from Syracuse University,
`Syracuse, NY, in 1970. the Ph.D. degree in elec-
`trical engineering from Princeton University,
`Princeton. NJ. in 1978.
`In 1976, he joined Texas Instruments Inc. and
`was involved in the research and development of
`charged-coupled devices. In 1978 he joined the
`IBM T. J. Watson Research Center. Yorktown Heights, NY. and has been
`engaged in the research and development of MOS devices.
`
`Page 4 of 4
`
`Page 5 of 5
`
`
`Page 5 of 5