SAMSUNG EXHIBIT 1023
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
`
`Page 1 of 8
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`US. Patent
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`s»xm.2.2:1:;2
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`Sheet 1 «:2
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`Us 6,366,139 B1
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`Bus drivers Prechargc Bus Einas Bus recicvcr
`circuit
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`35;
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`US. Patent
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`Apr, 2. 2%:
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`Sheet 2. of 2
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`Us 6,366,138 B1
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`Page 3 of 8
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`1
`HIGH SPEED LOW l’O‘WER DATA
`TRANSFER SCHEME
`
`2
`DETAILED DESCRIPTION OF THE
`PREFERRED EXEMPLARY EMBODIMENTS
`
`US 6,366,130 B1
`
`LA
`
`10
`
`HG. 1 illustrates a data transfer arrangement circuit 10
`that includes two bus drivers 11, 12, a precharge circuit 13,
`and two complementary bus lines 14, 15. The bus lines are
`inputs to a bus receiver 16 that is arranged as a latching sense
`amplifier.
`The two bus drivers are complementary and consist,
`preferably, of two active pull up/active pull down bus
`drivers.
`
`'1‘
`
`20
`
`Operation of the data transfer arrangement consists of two
`phases: A bus precharge phase and a data transfer phase.
`During the bus precharge phase,
`the control input PR
`(control signal for bus precharge circuit 13) is high and
`signal inputs DT (true phase of dual-rail data function) and
`DC (complement phase of dual-rail data function) are low.
`The true phase driver on transistors 20 and 21 and the
`complement phase driver on transistors 22 and 23 are in high
`impedance state and both bus lines are equalized and pre-
`charged to a potential Vpr (buses precharging voltage level)
`through the turned on transistors 24, 25 and 26.
`During the data transfer phase, the control input PR is low.
`The signal inputs become dillcrential: DT is high and DC‘ is
`low, and vise versa. One of the drivers is pulled up and
`charges the appropriate bus line from the precharged level
`VP, toward a more positive V,,,,——V, (where V, is the thresh-
`old voltage of the pull tip NMOS transistor ofthe driver). At
`the same time, the other driver is pulled down and discharges
`the opposite bus line from the precharged lcvcl VP, towards
`a more negative level V53 (ground). This provides a dilTer-
`ential voltage: +dV and —dV from the precharging level V’P_,.
`between true and complement bus lines. To provide proper
`U9 Jr
`operation of the bus receiver (the sensing amplifier), the
`-' minimum voltage ditference 2* dV
`mm (swing) between the
`lines may be about 0.05—(l.2OV. This low voltage swing is a
`basis to obtain high frequency of data transfer through the
`bus.
`
`This application claims priority from US. Provisional
`Patent Application No. 605'] 20531, filed Feb. 17, 1999, the
`disclosure of which is incorporated herein by reference in its
`entirety.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a data transfer scheme,
`and more particularly, to a high speed and low power CMOS
`data transfer scheme.
`
`2. Description of the Prior Art
`Today’s requirements for electronic circuits require high
`speed. Additionally,
`the circuits should be as “small and
`simple as possible due to the ever increasing number of
`circuits that are crowding today’s chip devices. Furthermore,
`circuits for data transfer should not be sensitive to circuit
`parameter mismatches, noise, and deviations in various
`applied voltages.
`SUMMARY OI’ THE INVENTION
`
`The present invention provides a high speed and low
`power CMOS data transfer arrangement that includes two
`active pull up/pull down bus drivers, a dillerential bus that
`precharges to a specific voltage level and a latched differ-
`ential sense amplifier that serves as a bus receiver.
`In accordance with one embodiment of the present
`invention, a data transfer arrangement
`includes two bus
`drivers,
`a voltage prccharge source,
`a differential bus
`coupled to the bus drivers and to the voltage prccharge
`source, and a latching sense amplifier coupled to the difier-
`cntial bus.
`
`In accordance with another embodiment of the present
`invention, the latching sense amplifier is arranged as a cross
`coupled latched amplifier.
`In accordance with a further embodiment of the present
`invention, the two bus drivers consist of active pull up/pull
`down bus drivers.
`
`invention provides a data transfer
`the present
`Thus,
`arrangement that operates at a high speed and uses low
`power. The data transfer arrangement is faster because the
`bus voltage swing passes directly to high gain nodes of the
`cross-coupled latched amplifier. Additionally, the data trans-
`fer arrangement uses a lower number of stacked transistors
`coupled between the Supply voltage and the high gain nodes
`when compared to the prior art. Additionally, the arrange-
`ment according to the present invention is less sensitive to 5
`deviations in voltage sources and the deviation of threshold
`voltage concerns of the input transistors. Additionally, the
`arrangement
`is
`less sensitive to circuit parameter
`mismatches, data bus common mode noise and power bus
`noises.
`
`Other features and advantages of the present invention
`will be understood upon reading and understanding the
`detailed description of the preferred embodiments below, in
`conjunction with reference to the drawings, in which like
`numerals represent like elements.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic of a differential data transfer
`arrangement in accordance with the present invention; and
`FIG. 2 is a schematic of a circuit for a sense amplifying
`latch for use in the data transfer arrangement illustrated in
`FIG. 1.
`
`65
`
`40
`
`FIG. 2 illustrates sensing amplifier 16. Preferably.
`sensing amplifier is a cross—couplcd latched amplifier.
`The sense amplifier operates in two phases, a prccharge
`phase and a data transfer phase. However.
`the sensing
`amplifier operates opposite to analogous phases of the bus
`driver.
`
`the
`
`When the control input CLK is low and the bus driver is
`in the data transfer mode,
`the sensing amplifier is in the
`precharge mode. The cross-coupled latched amplifier is
`isolated from the power buses (transistors 30 and 31 are
`turned off).
`the bus
`Transistors 32 and 33 are turned on and thus,
`voltage swing passes to the internal nodes IT (positive
`binary single—rail internal point of the sensing amplifier) and
`IC (negative binary single—rail data input phase internal
`point of the sensing amplifier) of the latched amplifier. The
`output nodes of both dynamic gates are precharged to VM
`and the complementary outputs QT (true phase of dual-rail
`data output signal) and QC (complement phase of duaI—rail
`output data signal) of the sensing amplifier become high.
`When the control input CLK is high and the bus driver is
`in the precharge mode, the sensing amplifier is in the data
`transfer mode. Transistors 32 and 33 are turned of and
`isolate the internal nodes IT and IC of the latched amplifier
`from the bus lines. The cross-coupled latched amplifier is
`connected to power buses (transistors 30 and 31 are turned
`on) and it begins to amplify the low voltage swings of the
`internal nodes IT and IC to full logic levels. The output node
`
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`US 6,366,130 B1
`
`3
`of one of the dynamic gates is discharged to ground and the
`appropriate output QT or QC of the sensing amplifier
`becomes low.
`
`The use of domino output stages in accordance with the
`present invention instead of static inverters is necessary to
`avoid leakage currents and output glitches, which may
`appear because potentials of nodes IT and 1C are approxi-
`mately equal to VP, during the operating cycle of the bus
`driver. Weak PMOS transistors 34 and 35 are preferably
`included in the sensing amplifier to help prevent output
`glitches.
`in accordance with the
`The data transfer arrangement
`present invention provides an increase in speed due to the
`differential
`low voltage swing bus driver in combination
`with the use of the latched differential sense amplifier as the A
`bus receiver.
`
`L4 (3
`
`4
`
`What is claimed is:
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`dilferential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`input of the output stage;
`wherein the ditferential bus and the differential data bus
`are precharge to a voltage Vpr between Vdd and
`ground, where Vpr=K*Vdd, and K is a precharging
`voltage factor.
`2. The data transfer arrangement in accordance with claim
`1 wherein the bus drivers comprise active pull—up and active
`pull—down bus drivers.
`3. The data transfer arrangement in accordance with claim
`1, wherein the first stage of the latching sense amplifier
`comprises:
`a plurality of input pass transistors each having a gate, a
`source terminal, and a drain: and
`a plurality of NMOS and PMOS transistors each having
`a gate, a source terminal, and a drain;
`wherein the drains of the input pass transistors are
`coupled to the drains of the cross-coupled latch ampli~
`.
`-
`.
`.
`_
`-
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`fier NMOS and PiVlOS.l1’dHSL.SIOYS, each source terminal
`.
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`of the Input pass mmslsmrs 15 Couplfid 10 an mpm’ the
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`sources of the PMOS transistors are coupled to ma
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`an Inverted clock ‘signal mpm.’
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`4. The data transfer arrangement in accordance with claim
`~
`..
`1. wherein the output stage of the latching sense amplifier
`Compusesj
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`gate, a source terminal, and a drain;
`3 M5‘ PMOS lmnslslm hafing 3 $5133: 3 501"“ terminal»
`and a drain» the gate bcins Coupled to 8 clock signal
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`a second PMOS transistor having a gate,
`lfifminaly 91351 H dfaifl, WC gate being C0UP1Cd *0 3 CIOCK
`Signal input; the SOUFCE being C0UPl€d 10 ‘ht? SOUFCC Of
`a second of the cross-coupled PMOS transistors; and
`the drain being coupled to the drain of the second of the
`"191" ”aU51~‘10FS;
`wherein the sources of the input transistors are coupled to
`a source of an NMOS transistor having a gate coupled
`‘O 3 CIOCR Slgflfil input;
`wherein the sources of the cross-coupled PMOS transis-
`tors are coupled to a voltage supply, the drains of the
`cross-coupled PMOS transistors are coupled to the
`drains Of tbfi input transistors; and
`wherein the drains of the cross—cou led transistors uro-
`P
`i
`vide a true and a complement phase of a data output
`signal.
`
`no
`
`30
`
`A further increase in speed is attained with the data
`transfer arrangement due to the pull up/‘pull down bus
`drivers, which provide equal low differential voltage swings
`+dV,/ —dV in both bus lines. This allows both bus lines to be
`active during the data transfer phase, eliminates the neces-
`sity to use special circuits for holding the precharged level
`and leads to a reduction in the capacitance load of the driver.
`The buses precharging to the specific level between
`ground and \’d(Vp,=K*\7a,d, where K=’/3 for the ideal MOS
`model) also provides: equal charge and discharge driver
`currents I(.,,=ldC,‘, provided by the NMOS pull up follower
`and the NMOS pull down switch,
`respectively, and
`therefore, equal differential voltage swings dV in both
`charged and discharged bus during the data transfer phase
`Pd[f:+CW.=IVh* Ddfl;,CLOAD; and _dV=IdCh*TdrF_,C1 “AU Id’
`represents the driver pull up output current (which, provides
`the C1/(MD charging from VW. up to VdJ); Idd, represents the
`driver pull down output current (providing the CLOAD dis»
`Charging from V” up to V”); CIOAD represents the bus is
`lines’ compacitanlces +dV represents the bus voltace change
`.
`,
`,
`if
`i
`O
`up from VP, during data transfer phase; ~dV represents the
`bus voltage chance down from V during data transfer
`phase. and T rcgrcgcnfi the dam frranqfer phase duration
`~
`-
`=2
`'
`The big“ prggharging ‘O the Specific level bmween ground
`and Vdd also provides high noise immunity due to active
`mode for both buses that equal low output resistances of the
`drivers in pull up and pull down mode and; low total power
`consumed bv drivers during the cvcle of operation (transfer
`Pius prechargq
`The latched sense amplifier is faster due to the bus voltage
`swing passing directly to the high—gain nodes IT and IC of
`the cross— coupled latched amplifier, the lower number of
`stacked transistors that are connected between the supply
`voltage Vdd(or Vm.) and riodeslT andIC, the fact that during 59
`latching of the IT and IC nodes, the nodes are charged by
`1<;*\/dd and (1_K)*V”,d instead of simply Vda,_/\ddj1jQn3Hy’
`the speed of the latched sensing amplifier is effected little by
`the deviation of voltage VP, and the deviation of the thresh-
`Old vottagc of the) input transistors,
`In addition 10 the higher Speed and low power C0n5ump_
`tion of the data transfer arrangement in accordance with the
`present invention, the arrangement is also less sensitive to
`circuit parameters mismatching, data bus common mode
`noise and power buses’ noises since both drivers are active an
`during data transfer phase. During the appropriate bus
`precharge phase, the bus receiver is isolated from the bus
`lines.
`Although the invention has been described with reference
`to s ecific exem larv embodiments it will be a
`ireciated 65
`P
`P
`.
`7
`Pl
`that it is intended to cover all modifications and equivalents
`within the scope of the appended claims.
`
`4-3
`
`4,
`U
`
`55
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`Page 5 of 8
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`Page 5 of 8
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`US 6,366,t30iB1
`
`5
`5. The data transfer arrangement in accordance with claim
`1, wherein the voltage precharge source is configured to
`precharge the differential bus to a predetermined voltage that
`is less than a logic high voltage and greater than a logic low
`voltage.
`6. The data transfer arrangement in accordance with claim
`1 further comprising a precharge circuit coupled between the
`precharge source and the diflferential bus.
`7. The data transfer arrangement in accordance with claim
`2 wherein the active pull up and pull down bus drivers are
`NMOS transistors.
`
`8. A method of operation of a data transfer arrangement
`comprising:
`two bus drivers;
`
`3 V’01l‘*g¢ Prechafge SOUFC47;
`a dilferential bus coupled to the bus drivers and to the
`voltage precharge source; and
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to
`a differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an
`input, and
`wherein the sense amplifier operates in two phases:
`a precharge phase and a data transfer phase;
`wherein the precharge phase operates when a control
`input clock signal is low, said phase comprising the
`steps of:
`
`‘J!
`
`10
`
`15
`
`:0
`
`L) in
`
`6
`isolating the cross«coupled latch amplifier from a pm»
`rality of power buses by turning off an NMOS
`transistor coupled to the clock signal input and a
`PMOS transistor coupled to the inverted clock signal
`input;
`passing a bus voltage swing to a plurality of internal
`nodes IT and IC of the latched amplifier;
`precharging both dynamic gates to Vdd; and
`providing a high true phase and a high complement
`phase of a data output signal; and
`wherein the data transfer phase operates when a control
`input clock signal is high, said phase comprising the
`steps of:
`isolating the internal nodes of the latched amplifier
`from the bus lines by turning off the pass input
`transistors;
`connecting the eross—coupled latched amplifier to
`power buses by turning on an NMOS transistor
`coupled to the clock signal
`input and 21 PMOS
`transistor coupled to an inverted clock signal input;
`amplifying each low voltage swing of the internal
`nodes to full logic levels;
`discharging an output node of one of the dynamic gates
`to ground; and
`providing a low true phase and a low complement
`phase of the data output signal.
`
`Page 6 of 8
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`US 6.366.130 C}
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`{H3} Number:
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`Pediesny et 3!.
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`—;4s,: (fertiiicaie Issued:
`
`Aug. 4, 23314
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`Page 7 of 8
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`

`
`1
`
`INTER PARTES
`
`US 6,366,130 C1
`
`2
`
`REEXAMINATION CERTIFICATE
`
`ISSUED UNDER 35 U.S.C. 316
`
`in
`
`THE PATENT IS HEREBY AI»/{ENDED AS
`INDICATED BELOW.
`
`Matter enclosed in heavy brackets [ ] appeared in the
`patent, but has been deleted and is no longer a part of the 10
`patent; matter printed in italics indicates additions made
`to the patent.
`
`AS A RESULT OF REEXAMINATION. IT HAS BEEN
`DETERMINED THAT:
`
`is
`
`The patentabiiiiy ofclaiins L2 and 5—7 is confirmed.
`New claim 9 is added and determined to be patent-able.
`Claims 3-4 and 8 were 1101 reexamined.
`
`9. 7729 dam transfer arrangemeni of(:/ainz I wherein the 3"
`output stage im:-lzzdcs Cross-roupledfeedback
`FF
`*
`3%
`>14
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`
`Page 8 of 8
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`Page 8 of8
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`Page 8 of 8