SAMSUNG EXHIBIT 1022
`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
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`Page 1 of 69
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`Samsung Electronics Co., Ltd. v. Elbrus International Limited
`Trial IPR2015-01524
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`Page 1 of 69
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`Case lPR20l5—Ol 524
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`U.S. Patent 6,366,130
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`Table of Contents
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`Executive Summary
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`II.
`
`Introduction
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`lll. Qualifications
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`IV. Obviousness Law
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`V.
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`Level of Skill in the Art
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`V1. The 6,366,130 Patent
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`Vll. Disputed Claims ofthe ‘130 Patent
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`VIII. Claim Construction
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`IX. Alleged Prior Art
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`X.
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`Patent Trial and Appeal Board Decision to Institute
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`X1. Discussion of ‘13O Claims and Alleged Prior Art
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`A.
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`Independent Claim 1
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`1.
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`2.
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`3.
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`4.
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`5.
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`What is K‘?
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`The Sukegawa ‘24l Reference
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`Nodes and Buses
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`Precharging of Nodes “C”
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`The Lu J SSC Reference
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`Dependent Claims 2, 3, 5, 6, 7 and 9
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`Dependent Claim 3
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`1.
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`The Watanabe ‘254 Reference
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`Dependent Claim 5
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`Dependent Claim 7
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`1.
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`The I-lardee ‘469 Reference
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`B.
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`C.
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`D.
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`E.
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`XII. Oath
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`Appendix A
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`ii
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`10
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`10
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`13
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`15
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`17
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`19
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`24
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`26
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`31
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`U.S. Patent 6,366,130
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`List of Figures
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`Figure A—-Annotated FIGS. 1 and 2 of the ‘I30 Patent
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`Figure B—Annotated FIG. 2 of the ‘I30 Patent
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`Figure C—Annotated FIG. I of the ‘24I Patent
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`Figure [}—Portion of Sukegawa FIG. 1 with Dr- Baker’s Changes for
`Vdd/2 Precharging of Nodes N3 and N4
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`Figure E——Portion of Sukegawa FIG. I with Attempt at Vdd/2 Precharging
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`Figure F—Annotated Fig. 4 of the Lu JSSC paper
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`21
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`23
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`25
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`34
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`35
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`38
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`Figure G—Portion of Sukegawa FIG. I with Added Precharge Device per Lu
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`40
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`Figure H—Annotated Portion of FIG. 2 of ‘I30 Patent and
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`FIG. 7 of Watanabe ‘254
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`Figure I—Annotated Portion of FIG. 2 of ‘I30 Patent Showing
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`Sources and Drains Required by Claim 3
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`Figure J—Annotated Portion of FIG. 2 of ‘ I 30 Patent With
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`PMOS Input Pass Transistors Added
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`Figure K—Annotated Portion of FIG. 2 of ‘I30 Patent
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`With Only PMOS Input Pass Transistors of Watanabe ‘254
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`Figure L—Logic Low Voltage and Logic High Voltage
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`Figure M-—FIG.
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`1 ofPodlesny ‘ 130; Portion of FIG. I of Sukegawa ‘24l;
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`and FIG. 5 of Hardee ‘469
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`42
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`44
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`45
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`46
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`50
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`52
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`U.S. Patent 6,366,130
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`1. Executive Summafl
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`1.
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`This Declaration is in support of patent owners in inter parres
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`review before the Patent Trial and Appeal Board of U.S. Patent 6,366,130 to
`
`Podlesny et al.
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`2.
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`The Board has decided to institute review with respect to the
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`following grounds:
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`A. Whether independent claim 1 and dependent claims 2, 5, 6, and 9
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`are unpatentable under 35 U.S.C. § 103 as obvious over the
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`combination of U. S. Patent 5,828,241 to Sukegawa and Lu
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`JSSC;
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`B. Whether dependent claim 3 is unpatentable under 35 U.S.C. §
`
`103 as obvious over the combination of Sukegawa, Lu, and U. S.
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`Patent 6,103,254 to Watanabe; and
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`C. Whether dependent claim 7 is unpatentable under 35 U.S.C. §
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`103 as obvious over the combination of Sukegawa, Lu, and U. S.
`
`Patent 6,249,469 to Hardee;
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`3.
`
`Evidence detailed in this Declaration demonstrates that
`
`A. Regarding Issue A above:
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`1) The combination of Sukegawa and Lu fails to disclose or
`
`suggest the differential data bus required by claim I.
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`2)
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`The combination of Sukegawa and Lu fails to disclose or
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`suggest
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`precharging
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`the
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`nodes
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`identified
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`as
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`the
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`differential data bus to a voltage Vpr between Vdd and
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`ground, as required by claim 1 .
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`3)
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`Modifications to Sukegawa and Lu necessary to provide
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`precharging of the nodes identified as the differential
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`data bus to the required voltage would not have been
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`obvious to one of ordinary skill in the art at the time of
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`the invention of the ‘I30 patent.
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`4)
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`The combination of Sukegawa and Lu fails to disclose or
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`suggest
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`the following elements required by claim 5:
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`“logic high voltage" and “logic low voltage.”
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`B. Regarding Issue B above:
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`1)
`
`The combination of Sukegawa, Lu and Watanabe fails to
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`disclose or suggest the following requirement stated in
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`claim 3: “...wherein the drains of the
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`input pass
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`transistors are coupled to the drains of the cross-coupled
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`latch amplifier NMOS and PMOS transistors, each
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`source terminal of the input pass transistors is coupled to
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`an input...’’.
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`in.)
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`C. Regarding Issue C above:
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`U.S. Patent 6,366,130
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`1) The combination of Sukegawa, Lu and Hardee fails to
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`disclose or suggest the following requirement stated in
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`claim 7: “...the active pull up and pull down bus drivers
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`are NMOS transistors.”
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`II. Introduction
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`4.
`
`I, William R. Huber, D.Sc., P.E,., a resident of West End, North
`
`Carolina, declare as follows:
`
`5.
`
`I have been retained on behalf of Elbrus international Limited, to
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`provide declaratory evidence in inter partes review of U.S. Patent 6,366,130
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`C“ l 30 patent”) to Podlesny et al.
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`6.
`
`I am being compensated for my work related to this inter parres
`
`review proceeding. My compensation is not dependent on and in no way affects
`
`the substance of my statements in this Declaration.
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`7.
`
`I have reviewed and am familiar with the specification and the
`
`claims ofthe ‘ 130 patent. I will cite to the specification using the following format:
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`(Ex. 1001, ‘I30 patent, l:l-I0). This example citation points to the ‘I30 patent
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`specification at column 1, lines 1-10.
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`L.)
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`8.
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`Along with the petition for inter parres review of the ‘130 patent
`
`(Paper 1; “Petition"), I have reviewed and am familiar with following references:
`
`I U.S. Patent 6,366,130 to Podlesny et al. (Ex. 1001; “I30 patent" or
`
`“Podlesny et al.‘’);
`
`I Prosecution File History for U.S. Patent 6,366,130 (Ex. 1003);
`
`I Declaration of Jacob Baker (Ex. 1002; “Baker Dec”);
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`I U.S. .Patent 5,828,241 to Sukegawa (Ex. 1005; “Sukegawa ‘241”);
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`I Lu, N. C-C. and Hu, H. C.; “Ha1f—VDD Bit-Line Sensing Scheme in
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`CMOS DRAM’s;” IEEE Journal of So1id~State Circuits; Vol. SC-19,
`
`No.4; August 1984; pp. 451-454 (Ex. 1008; “Lu JSSC”);
`
`I U.S. Patent 6,108,254 to Watanabe et al.
`
`(Ex.
`
`I006; “Watanabe
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`‘254");
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`I U.S. Patent 6,249,469 to I-Iardee (Ex. 1007; “I-Iardee ‘469”); and
`
`I Patent Owner’s Preliminary Response (Paper 8).
`
`9.
`
`I have also reviewed and refer to the Board’s Decision to Institute
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`Inter Partes Review in this proceeding (Paper 9; “Decision"), and the transcript
`
`from the deposition of Jacob Baker, Samsung’s declarant (Ex. 2003).
`
`10.
`
`I am familiar with the technology at issue and the state of the art at
`
`the time the application leading to the ‘130 patent was filed.
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`
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`1 I.
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`I have been asked to provide my technical
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`review, analysis,
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`insights, and opinions regarding the above—noted references, as well as various
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`Semiconductor industry practices.
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`III.
`
`ualifications
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`12. My academic and professional pursuits are closely related to the
`
`subject matter of the ‘ 1 30 patent.
`
`I3.
`
`I have more than 50 years of experience in the semiconductor field.
`
`I have over 30 years of experience in the hands-on product development, research,
`
`and management of complex semiconductor
`
`integrated circuit products. This
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`experience includes the design of memory devices.
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`I also have over 20 years of
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`technical consulting experience in the field of semiconductor memory devices.
`
`14.
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`I earned a Bachelor of Science degree in Electrical Engineering in
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`1962 from the University of Pittsburgh in Pittsburgh, Pennsylvania. One year later,
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`I earned a Master of Science degree in Electrical Engineering from The Ohio State
`
`University in Columbus Ohio. In 1969,
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`I earned a Doctor of Science degree in
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`Electrical Engineering from the University of Pittsburgh.
`
`15.
`
`I am currently the President of Electronics Consulting Engineers
`
`(ECE). I founded ECE in 1993. ECE has locations in Florida and West End, North
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`Carolina and provides patent-related services such as licensing evaluation, validity
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`and infringement assessment, and litigation support.
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`I have provided litigation
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`support to various integrated circuit companies in a wide array of semiconductor
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`technologies such as DRAM, SDRAM, and Flash memory.
`
`In providing this
`
`support, I rely on my technical experiences in the field of semiconductor memory:
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`(1) over 30 years of hands—on and management experience in the semiconductor
`
`field, including the design of semiconductor memory devices; (2) my involvement
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`with semiconductor standards committees,
`
`including the Joint Electron Device
`
`Engineering Council (IEDEC) Committee on semiconductor memory devices; and,
`
`(3)
`
`authoring
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`continuing
`
`education
`
`courses
`
`on
`
`semiconductor memory
`
`technologies.
`
`16. My hands-on and management experience in the semiconductor
`
`field started at Bell Telephone Laboratories in 1962, where I was a Member of
`
`Technical Staff and Supervisor. While at Bell, along with my group, I developed
`
`and applied the concept of redundancy to semiconductor memory chips. This
`
`development was quite significant
`
`in the semiconductor memory field since it
`
`reduced the impact of manufacturing defects on production yield and overall
`
`product cost.
`
`I co-authored and presented a paper on this memory redundancy
`
`concept. The paper won the Best Paper Award at the International Solid-State
`
`Circuits Conference in 1979.
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`I also authored/co-authored three other papers
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`focusing on semiconductor memory devices during my time at Bell. 1 left Bell in
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`1982.
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`17.
`
`From 1982 to 1989,
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`I was Manager of Integrated Circuit
`
`Development and Manager of Reliability and Quality Assurance at General
`
`Electric Company Microelectronics Center in Research Triangle Park, North
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`Carolina.
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`I planned and directed new product and technology development and
`
`characterization. One of the products we developed during this time was a 64K
`
`radiation-hardened SRAM.
`
`18.
`
`From 1989 to 1994, I worked at Harris Corporation in Melbourne,
`
`Florida as Senior Scientist and Director of Engineering—Military and Aerospace
`
`Division. I planned and directed new product development and characterization.
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`This effort included the development of radiation-hardened field—programmable
`
`gate array devices and also involved the design of a 256K radiation-hardened
`
`SRAM.
`
`19.
`
`In addition to my engineering experiences described above,
`
`I
`
`played an active role in various Joint Electron Device Engineering Council
`
`(JEDEC) committees. I was an active member of the JEDEC JC-42 Committee on
`
`Semiconductor Memory Devices from its early days in 1972 until 1984. As a
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`member, I met regularly with specialists from companies that designed or bought
`
`memories to develop physical, electrical and performance standards for a wide
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`variety of semiconductor memories. For the last two years of my tenure at JEDEC
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`JC—42,
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`I chaired the Task Group on IC Operating Voltage Standards. We
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`developed standards for low—voltage (3.3V) operation and interface requirements
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`for memory and logic devices.
`
`20.
`
`In addition to my semiconductor industry experience,
`
`I am an
`
`inventor on three U.S. patents that relate to semiconductor devices. Two of the
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`patents directly relate to semiconductor memory devices—in particular, DRAM
`
`devices.
`
`I am also a Life Senior Member of the Institute of Electrical and
`
`Electronics Engineers (IEEE) and have been a member for over 50 years.
`
`I am
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`currently registered as a Professional Engineer in Florida and North Carolina.
`
`21. Additional information on my education, technical experience and
`
`professional associations can be found in my curriculum vitae (attached as
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`Appendix A).
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`IV. Obviousness Law
`
`22.
`
`I understand that a patent claim is invalid if the claimed invention
`
`would have been obvious to a person of ordinary skill in the field at the time the
`
`application was filed. This means that even if all of the requirements of the claim
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`cannot be found in a single prior art reference that would anticipate the claim, the
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`claim can still be invalid.
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`23.
`
`To obtain a patent, the claimed invention must have, as of the
`
`priority date, been nonobvious in view of the prior art in the field. I understand that
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`an invention is obvious when the differences between the subject matter sought to
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`be patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
`
`in the art.
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`24.
`
`I understand that to prove that prior art or a combination of prior
`
`art renders a patent obvious, it is necessary to: (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to
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`create the inventions claimed in the asserted claim.
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`25.
`
`I understand that certain objective indicia can be important
`
`evidence regarding whether a patent
`
`is obvious or nonobvious. Such indicia
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`include: commercial success of products covered by the patent claims; a Iong—felt
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`need for the invention; failed attempts by others to make the invention; copying of
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`the invention by others in the field; unexpected results achieved by the invention as
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`compared to the closest prior art; praise of the invention by the infringer or others
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`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art.
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`V.
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`Level of Ordinagg Skill in the Art
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`26.
`
`As part of this inquiry, I have been asked to consider the level of
`
`ordinary skill in the field that someone would have had at the time the claimed
`
`invention was made.
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`In deciding the level of ordinary skill,
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`I considered the
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`following:
`
`0
`
`I
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`the levels of education and experience of persons working in the field;
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`the types of problems encountered in the field; and
`
`I
`
`the sophistication of the technology.
`
`27.
`
`Based on the technologies disclosed in the ‘130 patent, a person
`
`of ordinary skill in the art would have a Bachelor of Science degree in Electrical
`
`Engineering or an equivalent field, as well as at
`
`least 2 years of experience
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`designing and analyzing data transfer or equivalent circuits.
`
`VI. The 6,366,130 Patent
`
`28.
`
`Let us now examine the technical challenges addressed by the
`
`‘I30 patent. This will help define certain terms in the ‘130 patent claims in view of
`
`its specification as well as what a person of ordinary skill in the art would have
`
`understood during the 1999-2000 timeframe (also referred to herein as “the
`
`relevant timeframe”).
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`I 0
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`29.
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`The ‘I30 patent describes circuitry for efficiently transferring
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`data signals over long distances at high speeds while consuming low power. In
`
`describing the advantages of the invention, the ‘ 130 patent specification states:
`
`(Ex. l00l_,’l30 patent, 1:42-55):
`
`invention provides a data transfer
`the present
`Thus,
`arrangement
`that operates at a high speed and uses low
`power. The data transfer arrangement is faster because the
`bus voltage swing passes directly to high gain nodes of the
`cross-coupled latched amplifier. Additionally, the data trans-
`fer arrangement uses a lower number of stacked transistors
`coupled between the Supply voltage and the high gain nodes
`when compared to the prior art. Additionally, the arrange-
`ment according to the present invention is less sensitive to
`deviations in voltage sources and the deviation of threshold
`voltage concerns of the input transistors. Additionally, the
`arrangement
`is
`less sensitive to circuit para meter
`mismatches, data bus common mode noise and power bus
`noises.
`
`30.
`
`Several
`
`factors of the claimed invention of the ‘130 patent
`
`contribute to the higher data transfer speeds, lower power, and reduced sensitivity
`
`to component and environmental variations. As identified in the specification,
`
`these factors include:
`
`(Ex. l00l,’l30 patent, 3:12-16):
`
`in accordance with the
`The data trans er arrangement
`present invention provides an increase in speed due to the
`dilferential low voltage swing bus driver in combination
`with the use of the latched differential sense amplifier as the
`
`bus receiver.
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`l
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`I
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`(Ex. 1001 ,’l30 patent, 3: I 7-23):
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`A further increase in speed is attained with the data
`transfer arrangement due to the pull up/pull down bus
`drivers, which provide equal low dilferential voltage swings
`+dV,/' -dV in both bus lines. This allows both bus lines to be
`
`active during the data transfer phase, eliminates the neces-
`sity to use special circuits for holding the precharged level
`
`and leads to a reduction in the capacitance load of the driver.
`charged and discharged bus during the data transfer phase
`plus precharge).
`
`(Ex. 1001,‘l30 patent, 3:23-30):
`
`The buses precharging to the specific level between
`ground and Vd(Vp,=K* Vdd, where K=‘/3 for the ideal MOS
`model) also provides: equal charge and discharge driver
`currents ICh=ldC,,, provided by the NMOS pull up follower
`and the NMOS pull down switch,
`respectively, and
`therefore, equal differential voltage swings dV in both
`
`(Ex. 1001 ,’ I 30 patent, 3:40-45):
`
`The buses precharging to the specific level between ground
`and Vdd also provides high noise immunity due to active
`mode for both buses that equal low output resistances of the
`drivers in pull up and pull down mode and; low total power
`consumed by drivers during the cycle of operation (transfer
`
`I2
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`(Ex. 1001,’ I 30 patent, 3:46-55):
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`The latched sense amplifier is faster due to the bus voltage
`swing passing directly to the high—gain nodes IT and IC of
`the cross- coupled latched amplifier, the lower number of
`stacked transistors that are connected between the supply
`voltage V,“ (or Va.) and nodes IT and I C, the fact that during
`latching of the IT and IC nodes, the nodes are charged by
`K*V,,d and (l——K)*Vdd instead of simply Vdd. Additionally,
`the speed of the latched sensing amplifier is effected little by
`the deviation of voltage VP, and the deviation of the thresh-
`
`old voltage of the input transistors.
`lines.
`
`(Ex. l0Ol,’l30 patent, 3:56-63):
`
`In addition to the higher speed and low power consump-
`tion of the data transfer arrangement in accordance with the
`present invention, the arrangement is also less sensitive to
`circuit parameters mismatching, data bus common mode
`noise and power buses’ noises since both drivers are active
`during data transfer phase. During the appropriate bus
`precharge phase, the bus receiver is isolated from the bus
`
`VII. Disputed Claims ofthe ‘I30 Patent
`
`31.
`
`The following claims of the ‘I30 patent are disputed before the
`
`Patent Trial and Appeal Board:
`
`1. A data transfer arrangement comprising: two bus drivers; a voltage
`precharge source; a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid a latching sense amplifier coupled to the
`differential bus; wherein the latching sense amplifier comprises: a first
`stage including a cross~coupIed latch coupled to a differential data bus;
`and an output stage coupled to an output of said first stage; wherein the
`output of the first stage is coupled to an input of the output stage; wherein
`the differential bus and the differential data bus are precharge to a voltage
`
`13
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`Vpr between Vdd and ground, where Vpr=K*Vdd, and K is
`precharging voltage factor.
`
`a
`
`2. The data transfer arrangement in accordance with claim I wherein the
`bus drivers comprise active pull up and active pull-down bus drivers.
`
`3. The data transfer arrangement in accordance with claim 1, wherein the
`first stage of the latching sense amplifier comprises: a plurality of input
`pass transistors each having a gate, a source terminal, and a drain; and a
`plurality of NMOS and PMOS transistors each having a gate, a source
`terminal, and a drain; wherein the drains of the input pass transistors are
`coupled to the drains of the eross—coupled latch amplifier NMOS and
`PMOS transistors, each source terminal of the input pass transistors is
`coupled to an input, the sources of the cross-coupled latch amplifier
`NMOS transistors are coupled to the drain of the NMOS transistor
`coupled to a clock signal input, and the sources of the PMOS transistors
`are coupled to the drain of the PMOS transistor having a gate coupled to
`an inverted clock signal input.
`
`5. The data transfer arrangement in accordance with claim 1, wherein the
`voltage precharge source is configured to precharge the differential bus to
`a predetermined voltage that is less than a logic high voltage and greater
`than a logic low voltage.
`
`further
`6. The data transfer arrangement in accordance with claim 1
`comprising a precharge circuit coupled between the precharge source and
`the differential bus.
`
`7. The data transfer arrangement in accordance with claim 2 wherein the
`active pull up and pull down bus drivers are NMOS transistors.
`
`9. The data transfer arrangement of claim 1 wherein the output stage
`includes eross—coupled feedback.
`
`14
`
`Page 17 of 69
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`Page 17 of 69
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`
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`Case 1PR2015—01524
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`U.S. Patent 6,366,130
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`VIII. Claim Construction
`
`32.
`
`“During patent examination, the pending claims must be ‘given
`
`their broadest
`
`reasonable
`
`interpretation consistent with the
`
`specification’.’’
`
`M.P.E.P. § 2111 referring to Phiilips v. AWH Corp., 415 F.3d 1303 (Fed. Cir.
`
`2005). The statement has two parts: 1) broadest reasonable interpretation, and 2)
`
`Consistent with the specification. The M.P.E.P. also requires the use of the ordinary
`
`meaning of a word to a person of ordinary skill in the art unless it is otherwise
`
`defined by the specification. See M.P.E.P. § 2llI.0l(IIl). Strange or unusual
`
`meanings are not allowed unless specifically elucidated in the specification. In an
`
`inter parres review, the Board applies the same standard. Office Practice Trial
`
`Practice Guide, 77 Fed. Reg. 48,756 48, 764 (Aug. 14, 2012).
`
`33.
`
`The Petitioner proposes that two claim terms be construed by the
`
`Board: 1) “latching sense amplifier”, and 2) “stage.” As discussed in Patent
`
`Owner’s Preliminary Response (POPR), both of these terms were in common use
`
`in the relevant time period, and would have been clearly understood by one of
`
`ordinary skill at that time.
`
`34.
`
`Consider first the term, “latching sense amplifier." In the book,
`
`“DRAM Circuit‘ Design—A Tut0riaI,”' co—authored by Petitioner’s expert, R.
`
`Jacob Baker and first published in 2001, many sense amplifier designs and their
`
`‘ Keeth, B. and Baker, R.J.; IEEE Press, 2001
`
`15
`
`Page 18 of 69
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`Page 18 of 69
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`
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`Case IPRIZOIS-01524
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`U.S. Patent 6,366,130
`
`operation are discussed in detail. But nowhere is there a definition of “sense
`
`amplifier." The closest such statement seeks to define the function of sensing and
`
`appears on p. 22: “Sensing is essentially the amplification of the digitline signal or
`
`the differential voltage between the digitlines.” A similar lack of formal definition
`
`of “latching sense amplifier” or even “sense amplifier” occurs in what has been
`
`called the “bible" of semiconductor memories, “Semiconductor Mem0ries—A
`
`Handbook of Design, Manufacture, and AppI:'can'0n.”2 Despite over 50 page
`
`cites to “sense amplifier” in the index, there is no definition of the term.
`
`It is one
`
`of the terms understood by those of skill in the art, but lacking a formal definition.
`
`35.
`
`Now consider the term “stage?” Stage is another term which
`
`everyone in the field understands but which almost defies formal definition.
`
`Clearly Petitioner’s proposed construction, “a portion of a circuit” is excessively
`
`broad as it could include anything from a wire to thousands of components. But
`
`establishing a concise definition of stage, even within the restrained context of the
`
`‘ 1 30 patent, is neither productive nor necessary.
`
`36.
`
`On p. 5 of their DECISION issued January 19, 2016, the Patent
`
`Trial and Appeal Board states, “We determine that no express claim construction is
`
`required for purposes of this Decision.”
`
`2 Prince, 3; John Wiley & Sons; 1983 (First Edition) and 1991 (Second Edition)
`
`16
`
`Page 19 of 69
`
`Page 19 of 69
`
`
`
`37.
`
`The following table summarizes the positions of the parties on
`
`Case IPR2015—0l 524
`
`U.S. Patent 6,366,130
`
`construing the two terms.
`
`
`
`PTAB
`
`Decision
`
`
`
`
`Petitioner’s
`Patent Owner
`Patent Owner
`Proposed
`Position
`Proposed
`
`Construction
`
`
` "a circuit, Ordinary meaning “circuit that
`amplifier
`
`latching sense
`including a latch,
`amplifies low-
`that detects and
`level signals and
`
`lilies sinals"
`stores the result"
`"a portion ofa
`a portion ofa
`Ordinary meaning
`
`construction
`circuit"
`circuit that has an
`
`
`required
`
`input, an output
`and some
`
`
`
`
`
`
`No express
`claim
`
`
`
`
`
`IX. Allged Prior Art
`
`38.
`
`The following references were cited by the Petitioner as prior art
`
`relevant to the ‘ 1 30 patent.
`
`39.
`
`Sukegawa, S.; U. S. Patent 5,828,241; “Signal Transmission
`
`Circuit Providing Amplified Output from Positive Feedback of Intermediate
`
`Amplifier Circuit;” Filed June 5, 1996; Continuation to November 19, 1992
`
`Abstract:
`
`A signal transmission circuit which enables the distance of signal
`transmission as measured by the length of the wiring electrically
`connecting a driver circuit and a receiver circuit of the signal
`transmission circuit to be increased, while the signal delay and
`power consumption are reduced. The signal transmission circuit
`includes the driver circuit, the receiver circuit, an equalizer circuit
`that flattens the output of the driver circuit, and an intermediate
`amplifier circuit. The intermediate amplifier circuit is connected to
`inputfoutput shared terminals in the wiring that connects the driver
`circuit and the receiver circuit. With the aid of the positive
`feedback of the intermediate amplifier circuit. a differential signal
`
`I?’
`
`Page 20 of 69
`
`Claim Term
`
`stage
`
`Page 20 of 69
`
`
`
`Case 1PR2015-01524
`U.S. Patent 6,366,130
`output from the driver circuit is amplified and then transmitted to
`the receiver circuit.
`
`40.
`
`Lu, N.C.C. et al.; “Half V99 Bit—Line Sensing Scheme in
`
`CMOS DRAM’s;” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4,
`August 1984; pp. 451-454
`
`Abstract:
`A sensing scheme in which the bit line is precharged to half Vim is
`introduced for CMOS DR/—\M's. The study shows that the half-
`Vpn bit—line sensing scheme has several unique advantages,
`especially for high-performance high-density CMOS DRAM’s_.
`when compared to the full-V99 bit-line sensing scheme used for
`NMOS memory arrays or the grounded bit-line sensing scheme for
`PMOS arrays in CMOS DR:-’\M’s.
`
`41.
`
`Watanabe, Y. et a1.; U. S- Patent 6,108,254; “Dynamic Random
`
`Access Memory Having Continuous Data Line Equalization Except at
`Address Transition During Data Readingf’ Filed November
`12,
`1993;
`Continuation to June 4, 1991
`
`Abstract:
`A Dynamic Random Access Memory (DRAM) in which a data
`inputfoutput buffer
`is connected between first data lines and
`second data lines. An equalizing circuit and a data latch circuit are
`connected to the second data
`lines. The equalizing circuit
`maintains the second data lines in reset condition, during normal
`operation.
`it temporarily releases the second data lines from the
`reset condition, in response to an output from an address-transition
`detecting circuit,
`thereby to transfer the data from the data
`inputloutput buffer. The data latch circuit
`latches
`the data
`transferred to the second data lines, in response to the output from
`the address—transition detecting circuit.
`
`Page 21 of 69
`
`I8
`
`Page 21 of 69
`
`
`
`42.
`
`Hardee, K; U. S. Patent 6,249,469; “Sense Amplifier with Local
`
`Sense Drivers and Local Read Amplifiersg” Filed July 1, I996; Continuation to
`
`Case lPR20l5-01524
`
`U.S. Patent 6,366,130
`
`November 12, 1992
`
`Abstract:
`
`A sense amplifier for a very high density integrated circuit memory
`using CMOS technology is described. Each sense amplifier
`includes first and second local sense amplifier drive transistors,
`one connecting the P channel
`transistors to VCC;
`the other
`connecting the N channel
`transistors to VSS. A read amplifier
`circuit is provided within each sense amplifier and is operated by
`read control signals.
`lntemal nodes of the latch of the sense
`amplifier are coupled by pass transistors that are responsive to
`column write control signals. Local data write driver transistors are
`also provided to selectively couple the pass transistors to VCC-Vt
`or VSS in response to further data write control signals. A
`relatively wider power line is coupled to the drive transistors to
`provide VCC thereto, and a narrower line is used to control those
`first sense amplifier drive transistors. Corresponding wide and
`narrow lines are used for the second local sense amplifier drive
`transistors which couple the N channel transistors to ground. Each
`sense amplifier may be shared between first and second pairs of bit
`lines through the use of isolation transistors and a corresponding
`isolation signal.
`
`X.
`
`Patent Trial and Appeal Board Decision to Institute
`
`43.
`
`On January 19, 2016 the Patent Trial and Appeal Board ordered
`
`as follows:
`
`ORDER
`
`For the reasons given, it is hereby
`an inter partes
`§ 3l4(a),
`ORDERED that pursuant
`to 35 U.S.C.
`review is hereby instituted as to claims 1-3, 5-7, and 9 of the ’130 patent
`with respect to the following grounds:
`1. Whether claims 1, 2, 5, 6, and 9 are unpatentable under 35 U.S.C.
`§ 103 as obvious over the combination of Sukegawa and Lu;
`2. Whether claim 3 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Watanabe; and
`
`19
`
`Page 22 of 69
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`Page 22 of 69
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`
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`Case lPR20l5-01524
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`U.S. Patent 6,366,130
`
`3. Whether claim 7 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Harclee;
`FURTHER ORDERED that no ground other
`than those specifically
`listed above is authorized for the i'm.‘er partes review as to the ’l30 patent;
`and
`
`to 35 U.S.C.
`FURTHER ORDERED that pursuant
`37 C.F.R. § 42.4, notice is given of the institution of the trial.
`
`§
`
`314(0)
`
`and
`
`XI. Discussion of ‘I30 Claims and Alleged Prior Art
`
`44.
`
`Throughout my declaration, I will annotate various figures from
`
`the ‘I30 patent, Sukegawa ‘2-4], Lu JSSC, Watanabe ‘254 and I-lardee ‘469. These
`
`annotated figures are drafted based on the ‘I30 patent claims and visually highlight
`
`the distinctions between the disputed claims and the applied references.
`
`45.
`
`For example, Figures A and B below show the memory system
`
`disclosed in FIGS.
`
`l and 2 of the ‘130 patent, with color—coding to identify some
`
`of the claim elements of Claim 1.
`
`Page 23 of 69
`
`20
`
`Page 23 of 69
`
`
`
`
`
`=_3.$=2.25weNEau.m.U—._.~_..35o=:¢|<on:E
`
`usuau
`
`
`
`
`
`uu>omuBmamno.5mam.umumnunumm._u>m..m.mam
`
`Km_o-m_8?:38
`
`om_.8352$.m.:
`
`Page 24 of 69
`
`Page 24 of 69
`
`
`
`A.
`
`Independent Claim 1
`
`Case lPR2015—0l524
`
`US. Patent 6,366,130
`
`46.
`
`Claim I reads as follows (Ex. l00l,’130 patent, 4:2-17):
`
`1. A data transfer arrangement comprising: two bus drivers;
`a voltage precharge source; a differential bus coupled to the
`bus drivers and to the voltage precharge source; aid a
`latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises: a first stage
`including a cross-coupled latch coupled to a differential data
`bus; and an output stage coupled to an output of said first
`stage; wherein the output of the first stage is coupled to an
`input of the output stage; wherein the differential bus and
`the differential data bus are precharge to a voltage Vpr
`between Vdd and ground, where Vpr=K*Vdd, and K is a
`precharging voltage factor.
`
`47.
`
`Refer to Claim 1 and Figure A on the previous page.
`
`items 1] and 12 are the “two bus drivers," highlighted in I
`discussed at ‘I30 patent, 2:9-38.
`I
`
`H i
`
`and
`
`Items 24, 25 and 26, along with voltage source Vpr and control signal PR
`
`constitute “a voltage precharge source,” highlighted in :| and
`
`discussed at ‘130 patent, 2:14-22.
`
`Items 14 and 15 are “a differential bus coupled to the bus drivers and to the voltage
`
`precharge source,” highlighted
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