United States Patent
`
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`Watanabe et al.
`
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`19
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`[54] DYNAMIC RANDOM ACCESS MEMORY
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`HAVING CONTINUOUS DATA LINE
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`EQUALIZATION EXCEPT AT ADDRESS
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`[75]
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`_
`__
`__
`Inventors: YOIIJI Watanabe; KEHJI Tsuchlda, both
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`of Kawasaki’ Japan
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`[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
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`Japan
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`[21] Appl. No.: 08/150,782
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`[22]
`Filed:
`Nov. 12, 1993
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`Related U.S. Application Data
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`[63] Continuation of application No. 07/709,873, Jun. 4, 1991,
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`abandoned.
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`Foreign Application Priority Data
`[JP]
`Japan .................................. .. 2—144442
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`Jun. 4, 1990
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`[30]
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`[51]
`Int. Cl.7 .......................... .. G11C 7/06; G11C 11/407
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`[52] U.S. Cl.
`........................ .. 365/202; 365/203; 365/205;
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`365/207; 365/233.5
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`[58] Field of Search ................................... .. 365/154, 156,
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`365/189.05, 190, 202, 203, 205, 207, 233.5,
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`230.08; 307/494, 530, 355, 269
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`References Cited
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`U.S. PATENT DOCUMENTS
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`4,616,342 10/1986 Miyamoto ........................ .. 365/189.05
`4,811,295
`3/1989 Shinoda ......... ..
`365/189.05
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`4,870,617
`9/1989 Nakano et al.
`.... ..
`365/190
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`
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`11/1989 Watanabe et al.
`.................... .. 365/203
`4,881,203
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`[56]
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`US006108254A
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`11
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`El 611
`P t
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`t N
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`[45] Date of Patent:
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`11111 61'!
`b
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`6,108,254
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`Aug. 22, 2000
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`4,891,792
`.............. .. 365/189.05
`1/1990 Hanamura et al.
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`4,894,803
`1/1990 Aizaki
`.............. ..
`365/189.05
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`4,922,461
`5/1990 HayaRaWa et al.
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`365/230.08
`5,146,247
`9/1992 Sasaki 61 al.
`.................... ..
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`
`
`FOREIGN PATENT DOCUMENTS
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`0281 889
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`
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`60-119698
`63—007591
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`.
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`.
`
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`ELlI0p68.I1 Pat.
`
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`9/1988 European Pat. Off.
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`6/1985
`JaPan~
`1/1988
`Japan .
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`
`OTHER PUBLICATIONS
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`
`
`ISSCC 84/Thursday, Feb. 23, 1984/Continental Ballrooms
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`5-9/3:45 P.M.;Session XV: Static RAMs; Osamu Minato et
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`al; 1984 IEEE International Solid—State Circuits Confer-
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`
`
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`ence; pp. 222-223.
`
`
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`Primary Examiner—Jack A. Lane
`
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`Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
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`Maier & Neustadt, P.C.
`
`
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`ABSTRACT
`
`[57]
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`A Dynamic Random Access Memory (DRAM) in which a
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`data input/output buffer is connected between first data lines
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`and second data lines. An equalizing circuit and a data latch
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`circuit are connected to the second data lines. The equalizing
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`circuit maintains the second data lines in reset condition,
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`during normal operation. It temporarily releases the second
`data lines from the reset condition, in response to an output
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`from an address-transition detecting circuit, thereby to trans-
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`fer the data from the data input/output buffer. The data latch
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`circuit latches the data transferred to the second data lines,
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`in response to the output from the address-transition detect-
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`ing circuit.
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`13 Claims, 9 Drawing Sheets
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`27,
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`25
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`EQL LATCH
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`SAMSUNG EXHIBIT 1006
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`SAMSUNG EXHIBIT 1006
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`U.S. Patent
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`Aug. 22,2000
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`Sheet 1 of9
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`QUALIZING
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`H E
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`READ
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`Page 2 of 15
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`U.S. Patent
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`Aug. 22,2000
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`Sheet 2 of9
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`6,108,254
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`CAS
`CLOCK
`GENERATOR
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`29
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`8E<L:%"3'Ea
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`SENSE AMP.
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`ARRAY
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`Page 3 of 15
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`U.S. Patent
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`Sheet 3 of9
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`6,108,254
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`mm
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`COLUMN
`ADDRESS
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`Sheet 4 of9
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`LATCH
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`FIG. 7
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`vout
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`Aug. 22,2000
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`Sheet 6 of9
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`6,108,254
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`Aug. 22,2000
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`Sheet 7 of9
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`6,108,254
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`Sheet 8 of9
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`Page10of15
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`6,108,254
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`1
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`DYNAMIC RANDOM ACCESS MEMORY
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`HAVING CONTINUOUS DATA LINE
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`EQUALIZATION EXCEPT AT ADDRESS
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`TRANSITION DURING DATA READING
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`This application is a Continuation of application Ser. No.
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`07/709,873 filed on Jun. 4, 1991, now abandoned.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to a dynamic random access
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`memory (DRAM) which has synchronous data transfer
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`means.
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`2. Description of the Related Art
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`Two of the important points in designing a largescale
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`integrated circuit (LSI) are an increase in the operating
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`speed at which the LS1 operates, and a reduction in the
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`data lines which connects the circuit blocks of the LS1.
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`resistance, the performance of the LS1 decreases. To set the
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`LS1 performance at a sufficiently great value despite the
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`great capacitance and high resistance of the data lines, a data
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`transfer control system is used. This system comprises a
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`differential amplifier connected between an input data line
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`connected to the output terminal of the differential amplifier.
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`First, the equalizing circuit resets the data on the output data
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`line. Then, the data is transferred from the input data line to
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`the output data line.
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`The data transfer control system described above makes it
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`possible to transfer data at high speed, even if the data lines,
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`in particular the output data lines, have a large capacitance
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`briefly. If new data is transferred from the input data line to
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`output data line, thereby to invert the old data and form new
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`data. In order to perform this task, the amplifier must have
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`a great drivability. Hence, if the output data line has a great
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`capacitance or a high resistance, data cannot be transferred
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`be transferred at high speed even if the differential amplifier
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`output data line prior to the data transfer.
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`Even if the data transfer control system is used, however,
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`the transfer of the new data is delayed if it takes a long time
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`new data is a bar to high-speed operation and makes a great
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`problem to a recently developed large-chip LSI, in particular
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`a DRAM comprising data lines which are thin and long and,
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`hence, have a great capacitance or a high resistance. To be
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`more specific, the operating speed of the I/O data buffer
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`incorporated in a DRAM,
`for transferring data to, and
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`receiving data from, external devices, is very important.
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`As has been described, in the great problem with the I/O
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`data buffer used in the conventional large-scale DRAM, it
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`takes a long time to equalize the data lines,
`inevitably
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`reducing the speed of data transfer.
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`SUMMARY OF THE INVENTION
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`The object of the invention is to provide a DRAM having
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`means which can transfer data at a sufficiently high speed.
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`To accomplish this object, a DRAM according to the
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`present invention comprises:
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`a memory-cell array having a plurality of parallel bit lines,
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`a plurality of parallel word lines intersecting with the
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`bit lines, and a plurality of dynamic memory cells
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`located at intersections of the bit lines and the word
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`lines;
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`a sense amplifier for supplying data to and receiving data
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`from any selected one of the memory cells;
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`an address buffer having an output terminal and designed
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`to store a row address and a column address externally
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`supplied;
`a column decoder located near the memory-cell array, for
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`selecting one of the bit lines in accordance with the
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`column address output from the address buffer;
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`a row decoder located near the memory-cell array, for
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`selecting one of the word lines in accordance with the
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`row address output from the address buffer;
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`a transfer gate selectively controlled by said column
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`decoder;
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`first data lines connected to the bit lines by the transfer
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`gate;
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`a data input/output buffer connected to the first data lines;
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`second data lines connected to the first data lines by the
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`data input/output buffer;
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`an address-transition detecting circuit connected to the
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`output
`terminal of the address buffer, for detecting
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`transition of the row and column address signals output
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`from the address buffer and for outputting a signal upon
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`detecting the transition of the row and column address
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`signals;
`an equalizing circuit connected to the second data lines,
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`for maintaining the second data lines in reset condition
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`during normal operation, and for temporarily releasing
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`the second data lines from the reset condition in
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`response to the signal output from the address-
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`transition detecting circuit; and
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`a data-latching circuit connected to the second data lines,
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`for latching data transferred to the second data lines, in
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`response to the signal output from the address-
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`transition detecting circuit.
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`the second data lines
`In the DRAM of the invention,
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`remain in the reset (equalized) condition until address tran-
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`sition occurs at
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`address transition occurs, the second data lines are released
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`from the reset condition, whereby data is transferred from
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`the first data lines to the second data lines almost at the same
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`time the address transition takes place. The data transferred
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`to the second data lines is latched by the data-latching
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`circuit. The second data lines are therefore made ready for
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`receiving the data which will be transferred from the first
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`data lines when address transition occurs. No time is there-
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`fore required to equalize either data lines, unlike in the
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`conventional data transfer control system. Hence, data can
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`be transferred at high speed in the DRAM according to the
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`present invention.
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`Additional objects and advantages of the invention will be
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`set forth in the description which follows, and in part will be
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`obvious from the description, or may be learned by practice
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`of the invention. The objects and advantages of the invention
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`may be realized and obtained by means of the instrumen-
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`talities and combinations particularly pointed out
`in the
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`appended claims.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The accompanying drawings, which are incorporated in
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`and constitute a part of the specification, illustrate presently
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`Page 11 of 15
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`6,108,254
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`4
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`to the drains of the n-channel MOS transistors Q11 and Q12,
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`respectively. The n-channel MOS transistor Q15 is con-
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`nected to the source node of the n-channel MOS transistors
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`Q11 and Q12. The second CMOS differential amplifier 412
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`is also comprised of three n-channel MOS transistors Q21,
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`Q22 and Q25 and two p-channel MOS transistors Q23 and
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`Q24 which are connected in the same way as their equiva-
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`lents of the first CMOS differential amplifier 411.
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`The differential amplifier shown in FIG. 6 is an asynchro-
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`nous one, and immediately amplifies and output the transi-
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`tion of the input data. It can be replaced by a synchronous
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`differential amplifier comprising flip-flops.
`The data latch circuit 12 when used to read out data is, for
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`example of the type illustrated in FIG. 7, which has a CMOS
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`flip-flop and which has applied thereto the outputs Vout,
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`M of FIG. 6. The data latch circuit shown in FIG. 7
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`comprises a pair of three n-channel MOS transistors Q31,
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`Q32 and Q35 and five p-channel MOS transistors Q33, Q34,
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`Q36, Q37 and Q38. The MOS transistors Q31, Q32, Q33
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`and Q34 constitute a flip-flop. The MOS transistors Q35 and
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`Q36 are used to activate the flip-flop. The MOS transistors
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`Q37 and Q38 are latch control elements. In operation, the
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`p-channel MOS transistors Q37 and Q38 are turned on when
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`the latch control signal LATCH falls to a low level, whereby
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`the input data is transferred to the nodes N1 and N2 of the
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`flip-flop. When the control signal LATCH rises to a high
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`level, the transistors Q37 and Q38 are turned off, whereby
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`the nodes N1 and N2 are disconnected from the input lines,
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`and the flip-flop is activated at the same to hold the data.
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`The equalizing circuit 11 is one selected from those
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`illustrated in FIGS. 8 to 10. The equalizing circuits shown in
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`FIG. 8 to 10 will be described, one by one.
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`The equalizing circuit shown in FIG. 8 comprises a
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`p-channel MOS transistor Q1, the gate of which is connected
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`to receive the equalizing control signal Efi. When the
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`control signal Efi falls to the low level, the MOS transistor
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`is turned on, thus connecting two signal lines Vout and E.
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`The equalizing circuit
`illustrated in FIG. 9 comprises
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`p-channel MOS transistor Q1 for connecting signal lines
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`Vout and M, and two p-channel MOS transistors Q2 and
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`Q3 for precharging the signal lines Vout and E. The gate
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`of the MOS transistor Q1 is connected to receive the control
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`signal E. When the control signal fl falls to the low
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`level, all MOS transistors Q1, Q2 and Q3 are turned on. As
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`a result of this, both signal lines Vout and E are short-
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`circuited and are precharged to a potential VDL. The pre-
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`charge potential VDL is, for example, 1/2 Vcc; it can take any
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`other suitable value.
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`The equalizing circuit of FIG. 10 comprises two equal-
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`izing circuits which are identical to the circuit of FIG. 9,
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`each comprising three p-channel MOS transistors Q1 to Q3.
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`This performs the same function as the equalizing circuit
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`shown in FIG. 9, and is superior thereto in terms of switch-
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`ing characteristic. The p-channel MOS transistors can be
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`replaced by n-channel MOS transistors.
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`The operation of the data transfer circuit shown in FIG. 1
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`will now be explained, with reference to the timing chart of
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`FIG. 2.
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`As long as the input data remains unchanged, the control
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`signal T is at the low level. Controlled by this signal, the
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`equalizing circuit 11 short-circuits the second data lines 14.
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`The second data lines 14 are thereby precharged to, for
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`example, a potential of 1/2 Vcc. In other words, the lines 14
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`are reset or equalized. On the other hand, as long as the input
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`data remains unchanged, the control signal LATCH is at the
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`high level, and the data (i.e., old data) input to the data
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`3
`preferred embodiments of the invention, and together with
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`the general description given above and the detailed descrip-
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`tion of the preferred embodiments given below, serve to
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`explain the principles of the invention.
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`FIG. 1 is a block diagram schematically showing a data
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`transfer circuit for use in a DRAM according to the present
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`invention;
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`FIG. 2 is a timing chart explaining the operation of the
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`data transfer circuit shown in FIG. 1;
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`FIG. 3 is a block diagram illustrating the DRAM accord-
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`ing to a first embodiment of the invention;
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`FIG. 4 is a diagram showing the main part of the DRAM
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`illustrated in FIG. 3;
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`FIG. 5 is a timing chart explaining the operation of the
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`DRAM shown in FIG. 3;
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`FIG. 6 is a circuit diagram showing a CMOS differential
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`amplifier circuit used in a read mode as the data transfer
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`circuit;
`FIG. 7 is a circuit diagram illustrating a CMOS latch
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`circuit used in a read mode as the data transfer circuit;
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`FIGS. 8 to 10 are circuit diagrams showing various
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`equalizing circuits for use in the DRAM according to the
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`present invention;
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`FIG. 11 is a block diagram showing a combination of a
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`multiplexer and a data transfer circuit of the invention;
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`FIG. 12 is a circuit diagram illustrating the multiplexer
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`shown in FIG. 11;
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`FIG. 13 is a block diagram illustrating the DRAM accord-
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`ing to a second embodiment of the invention; and
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`FIG. 14 is a timing chart explaining the operation of the
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`DRAM shown in FIG. 13.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`10
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`25
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`35
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`The basic structure of the data transfer circuit incorpo-
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`rated in a DRAM according to the invention will now be
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`described in detail, with reference to FIG. 1.
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`As is shown in FIG. 1, the data transfer circuit comprises
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`a differential amplifier circuit 10, an equalizing circuit 11, a
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`data latch circuit 12, a pair of first data lines 13, a pair of
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`second data lines 14, and a pair of data output lines 15. The
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`first data lines 13 are connected to the input of the differ-
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`ential amplifier 10 which is the main component of the data
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`transfer circuit. The second data lines 14 are connected at
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`one end to the output of the amplifier 10, and at the other end
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`to the input of the data latch circuit 12. The equalizing circuit
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`11 is connected to the second data lines 14. The equalizing
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`circuit 11 is controlled by a control signal W which has
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`been generated when the data on the first data lines 13
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`undergo transition. The data output lines 15 are connected to
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`the output of the data latch circuit 12. The data latch circuit
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`12 is controlled by a control signal LATCH which has been
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`generated when the data on the first
`lines 13 undergo
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`transition.
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`The differential amplifier 10 when used to read out data
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`from the memory 27 is, for example, of the type shown in
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`FIG. 6. The amplifier 10 comprises two CMOS differential
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`amplifiers 411 and 412, both being of current-mirror type.
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`The first CMOS differential amplifier 411 is comprised of
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`three n-channel MOS transistors Q11, Q12 and Q15 and two
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`p-channel MOS transistors Q13 and Q14. The sources of the
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`n-channel MOS transistors Q11 and Q12 are connected
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`together. The p-channel MOS transistors Q13 and Q14 are
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`current-supplying elements, and have their drains connected
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`40
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`60
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`65
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`Page12of15
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`Page 12 of 15
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`5
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`in the previous operation cycle is kept
`transfer circuit
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`latched in the data latch circuit 12.
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`The moment the input data on the first data lines 13
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`undergoes transition, changing from Data 1 to Data 2, the
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`signal LATCH controlling the data latch circuit 12 falls to
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`the low level, thus releasing the old data and beginning a
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`read period. Almost at
`the same time,
`the signal fl
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`controlling the equalizing circuit 11 rises to the high level,
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`releasing the second data lines 14. Hence, Data 2, is trans-
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`ferred from the first data lines 13 to the second data lines 14
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`through the differential amplifier 10. When the difference
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`between the potentials on the second data lines 14 increases
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`to a predetermined value, the control signal LATCH rises to
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`the high level, whereby Data 2 is latched in the data latch
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`circuit 12. The control signal W falls back to the low level
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`immediately thereafter. The second data lines 14 are thereby
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`reset again, thus ending the read period. As a result, the data
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`on the output lines 15 changes, from the old data (i.e., Data
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`1) to the new one (i.e., Data 2).
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`When the next data is input to the data transfer circuit, the
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`operations described in the preceding paragraph are repeated
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`in sequence,
`thereby transferring the data from the first
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`signal lines 13 to the output lines 15 through the differential
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`amplifier 10, the second data lines 14, and the latch circuit
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`12.
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`As can be understood from the above, virtually no time is
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`required to equalize the second data lines 14, unlike in the
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`conventional data transfer circuit. In other words, the data is
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`transferred, almost at the same time the input data undergoes
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`transition. Thus, even if the second data lines 14 are con-
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`siderably long, and hence have a great capacitance and a
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`high resistance, data can be transferred at high speed.
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`A DRAM according to the invention, which includes a
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`data transfer circuit, will now be described with reference to
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`FIG. 3.
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`As is evident from FIG. 3, the DRAM comprises a row
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`address buffer 21, a column address buffer 22, a T clock
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`generator 23, a X clock generator 24, a column decoder
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`25, a row decoder 26, a memory cell array 27, a sense
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`amplifier 28, first data lines 29, a data input/output buffer 30,
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`second data lines 31, and a data latch circuit 32.
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`The row address buffer 21 and the column address buffer
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`22 are connected to receive a row address and a column
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`address, respectively, which have been externally supplied.
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`The T clock generator 23 generates a clock signal for
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`controlling the row address buffer. The T clock generator
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`23 is coupled to circuits 24, 26 and 28, which operate in
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`responding to the clock generator 23 in a manner as well
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`known among those skilled in the semiconductor memory
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`art. The T clock generator 24 generates a clock signal for
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`controlling the column address buffer 22. The column
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`decoder 25 decodes the column address held in the buffer 22,
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`thereby to select some of the bit lines of the cell array 27.
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`The row decoder 26 decodes the row address held in the
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`buffer 21, thereby to select some of the word lines of the cell
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`array 27. The memory cell array 27 has memory cells
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`arranged in rows and columns at the intersections of the bit
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`lines and the word lines. Each of these memory cells consists
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`of one transistor and one capacitor. The sense amplifier 28
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`supplies data to the memory cell array 27 and receive data
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`therefrom. The first data lines 29 are connected to the bit
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`lines selected in accordance with the column address
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`decoded by the decoder 22. The data input/output buffer 30
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`is connected to the first data lines 29. The second data lines
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`31 are connected between the output of the buffer 30 and the
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`input of the data latch circuit 32. An AND gate 60 has inputs
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`Page13of15
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`6,108,254
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`6
`coupled to signals W, CAS and an output coupled to the
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`data latch circuit 32.
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`The DRAM further comprises a substrate-biasing circuit
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`(not shown) and a refresh counter (not shown, either) for
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`achieving self-refreshing of the memory cell array 27. The
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`DRAM is not different from the conventional one, as far as
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`its structure described above is concerned. If necessary, the
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`DRAM can have a serial address counter which generates a
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`serial column address for designating several bit
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`thereby to achieve a serial access to the memory cell array
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`27.
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`FIG. 4 illustrates the data transfer system incorporated in
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`the DRAM shown in FIG. 3. As this figure shows,
`the
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`memory cell array 27 has pairs of bit lines BL and E and
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`word lines WL intersecting with the bit lines BL and K. The
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`memory cells MC are arranged at the intersections of the
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`bit-line pairs and the word lines WL. The bit lines BL and
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`K of each pair are selectively connected to the first data
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`lines 29 by a transfer gate which is controlled by column
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`select signals CSL on column-select signal
`lines CSLO,
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`CSL1, .
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`25.
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`Although not shown in FIG. 3, but as shown in FIG. 4, the
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`second data lines 31 connecting the data input/output buffer
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`30 and the data latch circuit 32 each consist of two data lines
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`311 and 312. An intermediate buffer 34 is connected between
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`the data lines 311 and the data lines 312 coresponding to the
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`second data lines 31. An equalizing circuit 351 is connected
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`to the lines 311, and an equalizing circuit 352 is connected
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`to the lines 312. The use of the intermediate buffer 34 is
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`safe-guard against the case where the load capacitance of the
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`input/output buffer 30 surpasses the drivability of the buffer
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`30. Hence, the intermediate buffer 34 can be dispensed with,
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`if the buffer 30 has drivability sufficiently great for the load
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`capacitance. If the drivability of the buffer 30 is far from
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`sufficient, the second data lines 31 must be divided into three
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`or more parts, and two or more intermediate buffers must be
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`used.
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`The output of the column address buffer 22 is connected
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`to an address-transition detecting circuit 33. The circuit 33
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`generates a control signal T and a control signal LATCH
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`upon detecting a transition of the address. The signal fl
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`will control the equalizing circuit 35, and the signal LATCH
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`will control the data latch circuit 32.
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`The input/output buffer 30, which transfers data from the
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`first data lines 29 to the second data lines 31, is the CMOS
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`differential amplifier circuit of current mirror type, which is
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`illustrated in FIG. 6. The intermediate buffer 34 can be also
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`a differential amplifier circuit of current mirror type. The
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`data latch circuit 32 is the CMOS latch circuit shown in FIG.
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`7. The equalizing circuit 35 can be one of the circuits
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