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`E EE E E E E § §
`E EE E E E E § §
`E EE E E E E § §
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`‘‘‘
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`JJJ
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`FL%»=__:_.2__:_EZ:_=_=__:_E__:§%LFL%»=__:_.2__:_EZ:_=_=__:_E__:§%L
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`_HHH___________________________7___:__:_________________HHH___________________________7___:__:________________
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`........_........_
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`....................._.._r....x....................._.._r....x
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`%%%%%%%%%%%%%%%%%%%%% L?Md%%%%%%% %%%%%%%%%%%%%%%%%%%%% L?Md%%%%%%%
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`Attorney Docket No.: 20181-SUS
`Client Reference No.: PPA-5
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`PATENT APPLICATION
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`HIGH SPEED LOW POWER DATA TRANSFER SCHEME
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`Inventor(s):
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`Andrew V. Podlesny
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`38/2 Menzinsky Street, Apt. 192
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`Moscow, Russia 129281
`a citizen of Russia
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`Valery V. Lozovoy
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`108 Ac.Chelomey Street, Apt. 6
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`Moscow, Russia 117630
`a citizen of Russia
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`Alexander V. Malshin
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`50 Frunzenskaya Nabergnaya, Apt. 608
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`Moscow, Russia 119270
`a citizen of Russia
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`Assignee:
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`ELBRUS INTERNATIONAL LIMITED
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`14, Bolshoi Savvinski Per.
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`Moscow, Russia 119435
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`Small business concern
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`TOWNSEND and TOWNSEND and CREW LLP
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`Two Embarcadero Center, 8”‘ Floor
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`San Francisco, California 94111-3834
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`(415) 576-0200
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`Page 16 of 97
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`are in high impedance state and both bus lines are equalized and precharged to a potential
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`VP, (buses precharging voltage level) through the turned on transistors 24, 25 and 26.
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`During the data transfer phase, the control input PR is low. The signal
`inputs become differential: DT is high and DC is low, and vise versa. One ofthe drivers
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`is pulled up and charges the appropriate bus line from the precharged level V,,, toward a
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`more positive Vdd — V, (where V. is the threshold voltage of the pull up NMOS transistor
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`opposite bus line from the precharged level Vp, towards a more negative level V55
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`(ground). This provides a differential voltage: +dV and ~ dV from the precharging level
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`V,,, between true and complement bus lines. To provide proper operation of the bus
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`receiver (the sensing amplifier), the minimum voltage difference 2* dVm;,. (swing)
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`between the lines may be about 0.05-- O.20V. This low voltage swing is a basis to obtain
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`high frequency of data transfer through the bus.
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`Figure 2 illustrates sensing amplifier 16. Preferably, the sensing amplifier
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`is a cross—coupled latched amplifier.
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`The sense amplifier operates in two phases, a precharge phase and a data
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`transfer phase. However, the sensing amplifier operates opposite to analogous phases of
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`When the control input CLK is low and the bus driver is in the data
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`amplifier is isolated from the power buses (transistors 30 and 31 are turned off).
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`Transistors 32 and 33 are turned on and thus, the bus voltage swing passes to the internal
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`(negative binary single—rail data input phase internal point of the sensing amplifier) of the
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`latched amplifier. The output nodes of both dynamic gates are precharged to Vdd and the
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`complementary outputs QT (true phase of dual-rail data output signal) and QC
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`(complement phase of dual-rail output data signal) of the sensing amplifier become high.
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`When the control input CLK is high and the bus driver is in the precharge
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`mode, the sensing amplifier is in the data transfer mode. Transistors 32 and 33 are turned
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`of and isolate the internal nodes IT and IC of the latched amplifier from the bus lines.
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`The cross—coupled latched amplifier is connected to power buses (transistors 30 and 31
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`are turned on) and it begins to amplify the low voltage swings of the internal nodes IT
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`and IC to full logic levels. The output node of one ofthe dynamic gates is discharged to
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`ground and the appropriate output QT or QC of the sensing amplifier becomes low.
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`The use of domino output stages in accordance with the present invention
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`instead of static inverters is necessary to avoid leakage currents and output glitches,
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`which may appear because potentials of nodes IT and 1C are approximately equal to VP,
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`during the operating cycle of the bus driver. Weak PMOS transistors 34 and 35 are
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`preferably included in the sensing amplifier to help prevent output glitches.
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`The data transfer arrangement in accordance with the present invention
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`provides an increase in speed due to the differential low voltage swing bus driver in
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`combination with the use of the latched differential sense amplifier as the bus receiver.
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`A further increase in speed is attained with the data transfer arrangement
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`swings +dV/ - dV in both bus lines. This allows both bus lines to be active during the
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`data transfer phase, eliminates the necessity to use special circuits for holding the
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`precharged level and leads to a reduction in the capacitance load of the driver.
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`The buses precharging to the specific level between ground and Vd (VP, =
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`K*Vdd, where K = 1/3 for the ideal MOS model) also provides: equal charge and
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`discharge driver currents Ich = Idch, provided by the NMOS pull up follower and the
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`NMOS pull down switch, respectively, and therefore, equal differential voltage swings
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`dV in both charged and discharged bus during the data transfer phase Pdtf: + dV =
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`Ich*Dd[f/CLOAD; and -dV = Idch *T,m/CLOAD.
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`(which provides the CLQAD charging from VF, up to Vdd); Idch represents the driver pull
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`Ich represents the driver pull up output current
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`down output current (providing the CLOAD discharging from V,,, up to V55); CLQAD
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`represents the bus lines’ compacitances; +dV represents the bus voltage change up from
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`VP, during data transfer phase; -dV represents the bus voltage change down from VP,
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`during data transfer phase; and T“ represents the data transfer phase duration. The buses
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`precharging to the specific level between ground and Vdd also provides high noise
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`immunity due to active mode for both buses that equal low output resistances of the
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`drivers in pull up and pull down mode and; low total power consumed by drivers during
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`the cycle of operation (transfer plus precharge).
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`The latched sense amplifier is faster due to the bus voltage swing passing
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`directly to the high-gain nodes IT and IC ofthe cross- coupled latched amplifier, the
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`lower number of stacked transistors that are connected between the supply voltage Vdd (or
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`Page 20 of 97
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`Vcc) and nodes IT and IC, the fact that during latching of the IT and IC nodes, the nodes
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`the latched sensing amplifier is effected little by the deviation of voltage VP, and the
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`deviation of the threshold voltage of the input transistors.
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`In addition to the higher speed and low power consumption of the data
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`transfer arrangement in accordance with the present invention, the arrangement is also
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`less sensitive to circuit parameters mismatching, data bus common mode noise and power
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`buses’ noises since both drivers are active during data transfer phase. During the
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`appropriate bus precharge phase, the bus receiver is isolated from the bus lines.
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`Although the invention has been described with reference to specific
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`exemplary embodiments, it will be appreciated that it is intended to cover all
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`modifications and equivalents within the scope of the appended claims.
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`Page 21 of 97
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`6»
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`HIGH-SPEED LOW-POWER DATA TRANSFER SCHEME
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`ABSTRACT OF THE DISCLOSURE
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`A data transfer arrangement. The data transfer arrangement includes two
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`active pull up/active pull down bus drivers and a voltage precharge source. A differential
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`bus is coupled to the bus drivers and to the voltage precharge source. A latching sense
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`amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers
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`operate in a precharge phase and a data transfer phase. The bus receiver operates in an
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`analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the
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`bus receiver is in the data transfer phase and when the bus drivers are in the data transfer
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`phase, the bus receiver is in a precharge phase
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`SF 1068801 V3
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`Page 23 of 97
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`Andrew V. Podlgy et al.
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`Application No.2 O9/505,656
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`Page 2
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`.
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`PATENT
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`Applicant believes that no fee is reguired for submission of this statement, since
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`it is being submitted prior to the first Office Action. However, if a fee is required, the
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`Commissioner is authorized to deduct such fee from the undersigned’s Deposit Account No.
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`20—1430. Please deduct any additional fees from, or credit any overpayment to, the above-
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`noted Deposit Account.
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`Respectfully submi
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`Kevin T. LeMond
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`Reg. No. 35,933
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`TOWNSEND and TOWNSEND and CREW LLP
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`Two Embarcadero Center, 8"‘ Floor
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`San Francisco, California 94111-3834
`Tel: 415-5 76-0200
`I
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`Fax: 415-576-0300
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`KTL:lo
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`SF 1178827 V1
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`Page 40 of 97
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`-'Ill|IllI|ll||llllll"||"||||||||||IIv-u--'Ill|IllI|ll||llllll"||"||||||||||IIv-u--'Ill|IllI|ll||llllll"||"||||||||||IIv-u-
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`§3§3§3
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`333 §§i§§
`333 §§i§§
`333 §§i§§
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`Application/Control Number: 09/505,656
`Art Unit: 2819
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`DETAILED ACTION
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`Claim Objections
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`In claims 2 and 3 Change “A" to “The".
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`Claim Rejections - 35 USC § 103
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`2.
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`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`(a) A patent may not be obtained though the invention is not identically disclosed or
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`described as set forth in section 102 of this title, if the differences between the subject
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`matter sought to be patented and the prior art are such that the subject matter as a
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`whole would have been obvious at the time the invention was made to a person having
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`ordinary skill in the an to which said subject matter pertains. Patentability shall not be
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`negatived by the manner in which the invention was made.
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`3.
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`Claims 1-3 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lee et al.
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`(U.S. PAT. 5,598,371) in view of Hayakawa (U.S. PAT. 6,184,722 B1).
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`Lee et al. teaches all claimed features of claim 1
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`in Fig. 1, a data transfer arrangement
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`comprising: two bus drivers (114, 116; 120, 122); a differential bus (line DIO and line DIOB)
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`coupled to the bus drivers and to the voltage precharge source (PRECH); with the exception of
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`teaching a latching sense amplifier coupled to the differential bus. However, Hayakawa teaches
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`in Fig. 5A a latching sense amplifier (2) coupled to the differential bus (4, 6).
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`Therefore, it would have been obvious to one ordinary skill in the art at the time of
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`applicants’ invention to have combined the circuit of Lee et al. along with the circuit of
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`Hayakawa to provide a sense amplifier that can sense a low level differential quickly and can
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`amplifier low level differential small swing input signals.
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`Regarding claim 2, Hayakawa further teaches in Fig. 5A the data transfer arrangement
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`of claim 1, wherein the latching sense amplifier comprises a cross coupled latch amplifier (03-
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`Page 43 of 97
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`'App|ication/Contro| Number: 09/505,555
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`Art Unit: 2819
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`*
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`Page 3
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`Regarding claim 3, Lee et al. further teaches in Fig. 1, the data transfer arrangement of
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`claim 1, wherein the bus drivers consist of active pull up/pull down bus drivers (114, 114, 120,
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`122).
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`4.
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`The prior art made of record and not relied upon is considered pertinent to applicant's
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`disclosure. Proebsting teaches a differential sense amplifier circuit. Shiratake teaches a sense
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`amplifier circuit. Yamauchi teaches a signal transmitting circuit, small receiving circuit, signal
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`transmitting/receiving circuit. Yoon teaches a sense amplifiers including bipolar transistor input
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`buffers and field effect transistor latch circuits. Decuir teaches a system and method for a
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`switch data bus termination.
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`Any inquiry concerning this communication or earlier communications from the examiner
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`should be directed to Vibol Tan whose telephone number is (703) 306-5948. The examiner can
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`normally be reached on Monday—Friday (7:00 AM—4:30 PM).
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
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`supervisor, Mike J. Tokar can be reached on (703) 305-3493. The fax phone numbers forthe
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`organization where this application or proceeding is assigned are (703) 305-0142 for regular
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`communications and (703) 305-3432 for After Final communications.
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`Any inquiry of a general nature or relating to the status of this application or proceeding
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`should be directed to the receptionist whose telephone number is (703) 308-0959.
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`ZVMM
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`Vibol Tan
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`Patent Examiner, AU 2819
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`PATRICK WAM EY
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`PRIMARY EXAMINER
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`Page 44 of 97
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`‘Andrew V. Podlesny et al.
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`Application No.: 09/505,656
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`Page 3
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`a first PMOS transistor having a gate, a source terminal, and a drain, the gate
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`being coupled to a clock signal input; the source being coupled to the source of the first of the cross-
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`coupled PMOS transistors; and the drain being coupled to the drain of the first of the input
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`transistors; and
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`a second PMOS transistor having a gate, a source terminal, and a drain, the
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`gate being coupled to a clock signal input; the source being coupled to the source of a second of the
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`cross-coupled PMOS transistors; and the drain being coupled to the drain of the second of the input
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`transistors;
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`wherein the sources of the input transistors are coupled to a source of an
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`NMOS transistor having a gate coupled to a clock signal input;
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`wherein the sources of the cross~coupled PMOS transistors are coupled to a
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`voltage supply, the drains of the cross-coupled.PMOS transistors are coupled to the drains of the
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`input transistors; and
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`wherein the drains of the cross-coupled transistors provide a true and a
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`complement phase of a data output signal.
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`S
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`(NEW) The data transfer arrangement in accordance with claim 1, wherein the
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`voltage precharge source is configured to precharge the differential bus to a predetermined voltage
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`that is less than a logic high voltage and greater than a logic low voltage.
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`(NEW) The data transfer arrangement in accordance with claim 1 further
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`comprising a precharge circuit coupled between the precharge source and the differential bus.
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`Q
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`(NEW) The data transfer arrangement in accordance with claim % wherein the
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`active pull up and pull down bus drivers are NMOS transistors.
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`A
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`(NEW) A method of operation of a data transfer arrangement comprising:
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`two bus drivers;
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`a voltage precharge source;
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`a differential bus coupled to the bus drivers and to the voltage precharge
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`source; and
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`Page 48 of 97
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`‘Andrew V. Podlesny et al. .
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`Application No.: 09/5 05,656
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`Page 5
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`REMARKS
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`0
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`PATENT
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`Upon entry of this Amendment, which amends claims 1 and 3, cancels claim 2, and
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`adds claims 4-9, claims 1 and 3—9 remain pending.
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`Claims 1-3 stand rejected under 35 U.S.C. l03(a) as being unpatentable over ‘Lee et
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`al. (U.S. PAT. 5,598,371) in view ofHayakawa (U.S. PAT. 6,184,722 B1).
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`These rejections are respectfully traversed and reconsideration is respectfiilly
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`requested on the grounds that the Examiner has not shown claim 1 would have been obvious in view
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`of prior art.
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`With regard to Lee et a1., it is respectfully submitted that Lee et al. teaches a data
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`transfer arrangement comprising two bus drivers and a differential bus coupled to the bus drivers and
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`to the voltage precharge source (PRECH), where the voltage precharge source (PRECH) is coupled A
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`to a supply voltage Vcc.
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`In contrast, the present invention teaches precharging the buses to a specific level
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`between ground and Vdd (Vpr = K*Vdd, where K is precharging voltage factor), as set out in the
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`specification on page 4, lines 16-30. Precharging the buses to a specific level between ground and
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`Vdd results in equal low differential voltage swings +dV,-Vd, providing increased speed of data
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`transfer, high noise immunity due to the active mode and equal low output resistance of the driver in
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