Filed on behalf of: Samsung Electronics Co., Ltd.
`
`By: Steven L. Park (stevenpark@paulhastings.com)
`
`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,366,130
`
`____________________
`
`
`DECLARATION OF DR. R. JACOB BAKER
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 1 of 83
`
`SAMSUNG EXHIBIT 1002
`
`
`
`By: Steven L. Park (stevenpark@paulhastings.com)
`
`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,366,130
`
`____________________
`
`
`DECLARATION OF DR. R. JACOB BAKER
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 1 of 83
`
`SAMSUNG EXHIBIT 1002
`
`
`
`
`
`
`
`
`TABLE OF CONTENTS
`
`Introduction ..................................................................................................... 1
`I.
`Qualifications .................................................................................................. 1
`II.
`Summary of Opinions ..................................................................................... 5
`III.
`IV. The ’130 Patent ............................................................................................... 7
`V.
`Claim Construction ......................................................................................... 9
`A.
`Latching Sense Amplifier (Claims 1 and 3) ....................................... 10
`B.
`Stage (Claims 1, 3, and 9) .................................................................. 11
`VI. The Prior Art Discloses or Suggests Every Feature of the Challenged
`Claims of the ’130 Patent ............................................................................. 12
`A.
`Brief Description of the Prior Art ...................................................... 12
`Sukegawa and Lu, Individually or in Combination with Other
`B.
`References, Disclose or Suggest Every Feature of the
`Challenged Claims of the ’130 Patent ................................................ 14
`Sukegawa and Lu Disclose or Suggest the Features of
`1.
`Claims 1-2, 5-6, and 9 .............................................................. 14
`Sukegawa, Lu, and Watanabe Disclose or Suggest the
`Features of Claim 3 .................................................................. 40
`Sukegawa, Lu, and Hardee Disclose or Suggest the
`Features of Claim 7 .................................................................. 55
`VII. Conclusion .................................................................................................... 58
`
`2.
`
`3.
`
`
`
`
`
`-i-
`
`
`
`Page 2 of 83
`
`
`
`
`
`
`Declaration of Dr. R. Jacob Baker
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`I, R. Jacob Baker, declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
`
`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”)
`
`as an independent expert consultant in this proceeding before the United States
`
`Patent and Trademark Office. Although I am being compensated at my rate of
`
`$450 per hour for the time I spend on this matter, no part of my compensation is
`
`dependent on the outcome of this proceeding, and I have no other interest in this
`
`proceeding.
`
`2.
`
`I understand that this proceeding involves U.S. Patent No. 6,366,130
`
`(“the ’130 Patent”) (Ex. 1001), the application for which was filed on February 17,
`
`2000, as U.S. Patent Application No. 09/505,656, and issued on April 2, 2002. I
`
`also understand, as demonstrated by the face of the ’130 Patent, that the ’130
`
`Patent purports to claim priority to February 17, 1999, the filing date of U.S.
`
`Provisional Application No. 60/120,531 (“the ’531 provisional application”).
`
`3.
`
`I have been asked to consider whether certain references disclose or
`
`suggest the features recited in the claims of the ’130 Patent. My opinions are set
`
`forth below.
`
`II. QUALIFICATIONS
`I serve as a Professor of Electrical and Computer Engineering at the
`4.
`
`University of Nevada, Las Vegas (“UNLV”). I have been teaching electrical
`
`1
`
`
`Page 3 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`engineering at UNLV since 2012. Before this, I was a Professor of Electrical and
`
`Computer Engineering with Boise State University beginning in 2000. Before my
`
`position at Boise State University, I was an Associate Professor of Electrical
`
`Engineering between 1998 and 2000 and an Assistant Professor of Electrical
`
`Engineering between 1993 and 1998, both at the University of Idaho. I have been
`
`teaching electrical engineering since 1991. I received my Ph.D. in Electrical
`
`Engineering from the University of Nevada, Reno, in 1993. I also received a MS
`
`and BS in Electrical Engineering from UNLV in 1988 and 1986, respectively.
`
`5.
`
`As further described in my CV, I am a licensed Professional Engineer
`
`in the State of Idaho and have more than 25 years of experience, including
`
`extensive experience in circuit design and manufacture of Dynamic Random
`
`Access Memory (DRAM) semiconductor integrated circuit chips and CMOS
`
`Image Sensors (CISs) at Micron in Boise, Idaho. I also spent considerable time
`
`working on the development of Flash memory while at Micron. My efforts resulted
`
`in more than a dozen Flash-memory related patents. Among many other
`
`experiences, I led the development of the delay-locked loop (DLL) in the late
`
`1990s so that Micron DRAM products could transition to the DDR memory
`
`standard. I also provided technical assistance with Micron’s acquisition of Photobit
`
`during 2001 and 2002. This assistance included help transitioning the manufacture
`
`of CIS products into Micron’s DRAM process technology. I have worked as a
`
`2
`
`
`Page 4 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`consultant at other companies designing memory chips, including Sun, Oracle, and
`
`Contour Semiconductor. I have worked at other companies designing CISs,
`
`including Aerius Photonics, Lockheed-Martin, and OmniVision.
`
`6.
`
`I am the author of several books covering the area of integrated circuit
`
`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
`
`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
`
`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and/or co-
`
`authored, more than 100 papers and presentations in the areas of solid-state circuit
`
`design and packaging.
`
`7.
`
`As a professor, I have been the main advisor to five Doctoral students
`
`and over 65 Masters students.
`
`8.
`
`I am the named inventor on over 137 granted U.S. patents in
`
`integrated circuit design including flash memory, DRAM, and CMOS image
`
`sensors.
`
`9.
`
`I have received numerous awards for my work, including the
`
`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
`
`Award is bestowed annually upon an outstanding young electrical/computer
`
`engineering educator in recognition of the educator’s contributions to the
`
`profession.
`
`3
`
`
`Page 5 of 83
`
`
`
`
`
`
`10.
`
`Declaration of Dr. R. Jacob Baker
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`I have also received the IEEE Circuits and Systems Education Award
`
`(2011), the IEEE Power Electronics Best Paper Award (2000), and I am a Fellow
`
`of the IEEE for contributions to memory circuit design.
`
`11.
`
`In addition, I have received the President’s Research and Scholarship
`
`Award (2005), Honored Faculty Member recognition (2003), Outstanding
`
`Department of Electrical Engineering Faculty recognition (2001), all from Boise
`
`State University. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor Award the three years I have been at UNLV.
`
`12.
`
`I have also given over 50 invited talks at conferences and universities
`
`in the areas of integrated circuit design including: AMD, Arizona State University,
`
`Beijing Jiaotong University, Carleton University, Carnegie Mellon, Columbia
`
`University, Dublin City University (Ireland), École Polytechnique de Montréal,
`
`Georgia Tech, Gonzaga University, Hong Kong University of Science and
`
`Technology, Indian Institute of Science (Bangalore, India), Instituto de Informatica
`
`(Brazil), Instituto Tecnológico y de Estudios Superiores de Monterrey, ITESM
`
`(Mexico), Iowa State University, Laval University, Lehigh University, Princeton
`
`University, Temple University, University of Alabama, University of Arkansas,
`
`University of Buenos Aires (Argentina), University of Illinois, Urbana-Champaign,
`
`Utah State University, University of Nevada, Las Vegas, University of Houston,
`
`University of Idaho, University of Nevada, Reno, University of Macau, University
`
`4
`
`
`Page 6 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`of Toronto, University of Utah, Yonsei University (Seoul, Korea), University of
`
`Maryland, IEEE Electron Devices Conference (NVMTS), IEEE Workshop on
`
`Microelectronics and Electron Devices (WMED), the Franklin Institute, National
`
`Semiconductor, AMI semiconductor, Micron Technology, Rendition, Saintgits
`
`College (Kerala, India), Southern Methodist University, Sun Microsystems,
`
`Stanford University, ST Microelectronics (Delhi, India), Tower (Israel), Foveon,
`
`ICySSS keynote, and Xilinx.
`
`13.
`
`Details of my professional and educational background, as well as a
`
`listing of other matters on which I have provided consulting and/or provided
`
`testimony as a technical expert, are provided in my Curriculum Vitae, attached as
`
`Appendix A to this Declaration.
`
`III. SUMMARY OF OPINIONS
`All of the opinions contained in this Declaration are based on the
`14.
`
`documents I reviewed, my experience and background, and my knowledge and
`
`professional judgment. In forming the opinions expressed in this Declaration, I
`
`reviewed the ’130 Patent (Ex. 1001); the prosecution file history for the ’130
`
`Patent (Ex. 1003); the file history of the inter partes reexamination (control no.
`
`95/000,657) (“the ’657 proceeding”) for the ’130 Patent, excerpts of which I
`
`understand are being submitted as Ex. 1004; U.S. Patent No. 5,828,241 to
`
`Sukegawa (“Sukegawa”) (Ex. 1005); U.S. Patent No. 6,249,469 to Hardee
`
`5
`
`
`Page 7 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`(“Hardee”) (Ex. 1007); U.S. Patent No. 6,108,254
`to Watanabe et al.
`
`(“Watanabe”) (Ex. 1006); “Half-VDD Bit-Line Sensing Scheme in CMOS
`
`DRAM’s,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1984
`
`by Nicky Chau-Chun Lu et al. (“Lu”) (Ex. 1008); and excerpts from the Modern
`
`Dictionary of Electronics (7th ed. 1999) (Ex. 1009), while drawing on my
`
`experience and knowledge in the field.
`
`15. My opinions have also been guided by my appreciation of how a
`
`person of ordinary skill in the art would have understood the claims of the ’130
`
`Patent at the time of the alleged invention, which I have been asked to initially
`
`assume is February 17, 1999, the filing date of the ’531 provisional application
`
`from which the ’130 Patent purports to claim priority. At the time of the alleged
`
`invention, a person of ordinary skill in the art related to the technology of the ’130
`
`Patent would have had an undergraduate degree in Electrical Engineering or
`
`equivalent and at least two to three years of experience in the design and/or
`
`analysis of data transfer circuits or the equivalent. In determining the level of
`
`ordinary skill, I was asked to consider, for example, the types of problems
`
`encountered in the art, prior solutions to those problems, the rapidity with which
`
`innovations are made, the sophistication of the technology, and the educational
`
`level of active workers in the field.
`
`6
`
`
`Page 8 of 83
`
`
`
`
`
`
`16.
`
`Declaration of Dr. R. Jacob Baker
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`Based on my experience and expertise, it is my opinion that certain
`
`references disclose or suggest all the features recited in claims 1-3, 5-7, and 9 (“the
`
`challenged claims”) of the ’130 Patent.
`
`IV. THE ’130 PATENT
`The ’130 Patent is purportedly directed to a data transfer scheme that
`17.
`
`includes two bus drivers, a precharge circuit, two complementary bus lines, and a
`
`latching sense amplifier. See, e.g., Ex. 1001 2:1-8. Figure 1 of the ’130 Patent
`
`illustrates two bus drivers 11, 12 (consisting of transistors 20, 21, 22, and 23) and
`
`two complementary bus lines 14, 15 as inputs to a latching sense amplifier 16:
`
`18.
`
`The data transfer scheme operates in two phases: a precharge phase
`
`and a data transfer phase (Ex. 1001 2:12-13), with the bus drivers and
`
`
`
`7
`
`
`Page 9 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`complementary bus lines operating in opposite phases to the latching sense
`
`amplifier (Ex. 1001 2:43-44). In other words, when the complementary bus lines
`
`and the bus drivers are in the precharge phase, the sense amplifier is in data
`
`transfer phase and vice versa.
`
`19.
`
`Figure 2 of the ’130 Patent discloses a latching sense amplifier:
`
`
`
`20.
`
`I understand that the ’130 Patent includes 9 claims with claims 1 and
`
`8 being independent and claims 2-7 and 9 being dependent from claim 1. I further
`
`understand that claim 9 was added during reexamination. As I note above, I was
`
`asked to opine with respect to some of the claims of the ’130 Patent. I have
`
`reproduced claim 1 below:
`
`1. A data transfer arrangement comprising:
`
`8
`
`
`Page 10 of 83
`
`
`
`
`
`
`Declaration of Dr. R. Jacob Baker
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`two bus drivers;
`
`a voltage precharge source;
`
`a differential bus coupled to the bus drivers and to the voltage precharge
`
`source; aid [sic]
`
`a latching sense amplifier coupled to the differential bus;
`
`wherein the latching sense amplifier comprises:
`
`a first stage including a cross-coupled latch coupled to a differential data
`
`bus; and
`
`an output stage coupled to an output of said first stage;
`
`wherein the output of the first stage is coupled to an input of the output
`
`stage;
`
`wherein the differential bus and the differential data bus are precharge to a
`
`voltage Vpr between Vdd and ground, where Vpr = K*Vdd, and K is a
`
`precharging voltage factor.
`
`V. CLAIM CONSTRUCTION
`I understand that a claim subject to inter partes review receives the
`21.
`
`broadest reasonable construction in light of the specification of the patent in which
`
`it appears. I also understand that in these proceedings, any term that is not
`
`construed should be given its plain and ordinary meaning under the broadest
`
`reasonable construction. I have followed these principles in my analysis. I discuss
`
`9
`
`
`Page 11 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`a few terms below and what I understand to be Petitioner’s constructions of these
`
`terms.
`
`A. Latching Sense Amplifier (Claims 1 and 3)
`Independent claim 1 and dependent claim 3 of the ’130 Patent recite a
`22.
`
`“latching sense amplifier.” I understand Petitioner has offered that the broadest
`
`reasonable construction of the term “latching sense amplifier” that is consistent
`
`with the use of the term in the claims and specification of the ’130 Patent is “a
`
`circuit, including a latch, that detects and amplifies signals.” I have used this
`
`construction in my analysis and agree with it because the specification describes its
`
`latching sense amplifier to include a latch (see, e.g., Ex. 1001 2:39-40, 2:48-50) for
`
`detecting (see, e.g., Ex. 1001 2:33-38, 2:64-67) and amplifying received signals
`
`(see, e.g., Ex. 1001 2:64-67). Furthermore, latching sense amplifiers were well
`
`known at the time of the alleged invention of the ’130 Patent, and this construction
`
`is consistent with the understanding of one of ordinary skill in the art at the time of
`
`the alleged invention of the ’130 Patent as well as dictionary definitions for similar
`
`terms (see, e.g., Ex. 1009 at 679 (defining “sense amplifier” as “[a] circuit used to
`
`sense low-level voltages … and to amplify these signals to the logic voltage levels
`
`of the system”). In my opinion, the claims additionally specify what a “latching
`
`sense amplifier” has to include. For example, claim 1 requires that the “latching
`
`10
`
`
`Page 12 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`sense amplifier” include both a first stage with a cross-coupled latch and an output
`
`stage. See, e.g., Ex. 1001 4:8-13.
`
`B.
`23.
`
`Stage (Claims 1, 3, and 9)
`
`Independent claim 1 and dependent claims 3 and 9 recite a “stage.” I
`
`understand Petitioner has offered that the broadest reasonable construction of the
`
`term “stage” that is consistent with the use of the term in the claims of the ’130
`
`Patent is “portion of a circuit.” I have used this construction in my analysis and
`
`agree with it. In my experience and in the field, the term “stage” is sometimes used
`
`to refer to a portion of a circuit. This construction is consistent with dictionary
`
`definitions for the term. See, e.g., Ex. 1009 at 728 (defining “stage” as “[a] single
`
`section of a multisection circuit or device”). This meaning is further reinforced by
`
`the claims. Claim 1 specifies that a latching sense amplifier comprises of a “first
`
`stage” and an “output stage,” and claims 3 and 9 use the terms in the context of
`
`particular circuitry found within a “first stage” and an “output stage.” See, e.g.,
`
`Ex.1001 4:8-13, 4:21-23, Reexam Cert. 1:20-21. As the latching sense amplifier is
`
`itself a circuit, it follows accordingly that particular “stages” of the circuit reflect a
`
`portion of the circuit. My understanding is also consistent with the specification’s
`
`use of the term “stage.” Ex. 1001 3:4-5.
`
`11
`
`
`
`
`Page 13 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`VI. THE PRIOR ART DISCLOSES OR SUGGESTS EVERY FEATURE
`OF THE CHALLENGED CLAIMS OF THE ’130 PATENT
`
`24.
`
`I have reviewed several references, discussed further below, that I
`
`understand are prior art to the ’130 Patent. In my opinion, these references disclose
`
`or suggest all features of the challenged claims of the ’130 Patent.
`
`A. Brief Description of the Prior Art
`Sukegawa describes “a type of signal transmission circuit wherein the
`25.
`
`signal is amplified and transmitted by means of the positive feedback of an
`
`intermediate amplifier circuit having input/output shared terminals.” Sukegawa
`
`1:11-15. The signal transmission circuit disclosed sought to increase the signal
`
`transmission distance as well as increase the speed and lower the power
`
`consumption of a transmission. Id. 4:52-55. Sukegawa discloses that its signal
`
`transmission circuit comprises of “a driver circuit, a receiver circuit, an equalizer
`
`circuit, and an intermediate amplifier circuit.” Id. 4:62-65. The intermediate
`
`amplifier circuit relies on positive feedback to amplify the signal provided by the
`
`driver circuit and transmit the amplified signal to the receiver circuit. See, e.g., id.
`
`5:1-4.
`
`26.
`
`Lu describes a signal transmission system, and in particular, a sense
`
`amplifier utilized by DRAMs (Dynamic Random Access Memory). See, e.g., Lu
`
`Abstract. Lu introduces “a sensing scheme for CMOS DRAM’s [sic] in which the
`
`bit line is precharge to half-VDD.” Id. 451. Similar to Sukegawa, Lu discloses the
`
`12
`
`
`Page 14 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`
`need to develop signal transmission systems faster in speed and lower in power
`
`consumption. See, e.g., id. 453-54.
`
`27.
`
`Watanabe relates to the transmission of signals in electronic circuits.
`
`See, e.g., Watanabe Abstract, 1:10-13. Specifically, Watanabe introduces a “data
`
`transfer circuit incorporated in a DRAM.” Id. 3:38-39. “[T]he data transfer circuit
`
`comprises a differential amplifier circuit 10, an equalizing circuit 11, a data latch
`
`circuit 12, a pair of first data lines 13, a pair of second data lines 14, and a pair of
`
`data output lines 15.” Id. 3:41-44; see also, e.g., id. Fig. 1. Like Sukegawa and Lu,
`
`the circuit disclosed by Watanabe was motivated by a need to increase the
`
`transmission speed of signals in electronic circuits. See, e.g., id. 2:52-56 (“No time
`
`is therefore required to equalize either data lines, unlike in the conventional data
`
`transfer scheme. Hence, data can be transferred at high speed in DRAM according
`
`to the present invention.”).
`
`28.
`
`Hardee
`
`is yet another prior art reference relating
`
`to signal
`
`transmission, and in particular, “integrated circuit memories” and “sense amplifiers
`
`for use therein.” See, e.g., Hardee 1:8-10. Hardee introduces a sense amplifier
`
`highlighted by three “salient” features:
`
`(1) the connection of each sense amplifier via transistors
`
`or other switching devices to the power supply lines
`
`13
`
`
`Page 15 of 83
`
`
`
`
`
`
`Declaration of Dr. R. Jacob Baker
`
` Inter Partes Review of U.S. Patent No. 6,366,130
`without directly connecting together power supply lines
`
`for multiple sense amplifiers;
`
`(2) the use of local read amplifiers;
`
`(3) the use of local write circuitry.
`
`See i.d. 5:24-32.
`
`29.
`
`All the prior art references mentioned above relate to signal
`
`transmission and were motivated to improve the efficiency of such transmissions.
`
`As such, one of ordinary skill in the art at the time of the alleged invention of the
`
`’130 Patent would have been motivated to combine the teachings of these
`
`references.
`
`B.
`
`30.
`
`Sukegawa and Lu, Individually or in Combination with Other
`References, Disclose or Suggest Every Feature of the Challenged
`Claims of the ’130 Patent
`1.
`
`Sukegawa and Lu Disclose or Suggest the Features of
`Claims 1-2, 5-6, and 9
`In my opinion and as shown in the charts below, Sukegawa and Lu
`
`disclose or suggest each and every feature recited in claims 1-2, 5-6, and 9 of the
`
`’130 Patent.
`
`a. Claim 1
`In my opinion, Sukegawa and Lu disclose or suggest each and every
`
`31.
`
`feature recited in claim 1.
`
`14
`
`
`Page 16 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Claim Language
`
`Sukegawa and Lu
`
`1. A data transfer
`
`Sukegawa discloses a data transfer arrangement.
`
`arrangement
`
`For example, Sukegawa introduces “[a] signal transmission
`
`comprising:
`
`circuit which enables the distance of signal transmission as
`
`measured by the length of the wiring electrically connecting a
`
`driver circuit and a receiver circuit of the signal transmission
`
`circuit
`
`to be increased, while the signal delay and power
`
`consumption are reduced.” Sukegawa Abstract.
`
`Fig.
`
`1 of Sukegawa “is a circuit diagram illustrating an
`
`embodiment of the signal transmission circuit in accordance
`
`with the invention.” Sukegawa 6:37-39.
`
`two bus drivers;
`
`Sukegawa discloses two bus drivers (e.g._, transistor group 26-
`
`27 and transistor group 28-29). See, e.g., Sukegawa Fig.
`
`1
`
`Page 17 of 83
`
`15
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`(annotated below).
`
`FIG.
`
`1
`
`Sukegawa discloses that “[d]river circuit 2 comprises input
`
`terminal IN, enable EN terminal, NAND gates 22, 23, CMOS
`
`inverters 21, 24, 25, pMOS transistors 26, 28, and nMOS
`
`transistors 27, 29. The input terminal IN of driver circuit 2 is
`
`connected through CMOS inverter 21 to one input terminal of
`
`NAND gate 22, and the input terminal IN is also connected to
`
`one input terminal of NAND gate 23. Enable EN terminal is
`
`connected to the other input terminals of NAND gates 22, 23.
`
`In the driver circuit 2, in the initial precharge state, the enable
`
`EN terminal is at L level, while node N1 and node N2 on the
`
`output sides of NAND gates 22, 23 are at H level.” Sukegawa
`
`Page 18 of 83
`
`16
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Claim Language
`
`Sukegawa and Lu
`
`8:11-23; see also, e.g., id. 9: 14-21.
`
`a voltage
`
`Sukegawa discloses a Voltage precharge source (e-g., BLR).
`
`precharge source;
`
`See, e.g., Sukegawa Fig. 1 (annotated below).
`
`See also,
`
`e.g., Sukegawa 8:24-31 (“On the other hand,
`
`equalizer circuit 3 comprises BLR node with the balance
`
`signal applied to it, precharge (referred to as PC hereinafter)
`
`node and nMOS transistors 30-32. The BLR node is connected
`
`to the drain of nMOS transistor 30 and the drain of nMOS
`
`transistor 31, and the BLR node becomes the power source
`
`voltage VDD/2 in the initial precharge source.”), 7:29-37.
`
`a differential bus
`
`Sukegawa discloses a differential bus (e.g., LINE, LINE_)
`
`coupled to the bus coupled to the bus drivers (e.g., transistor group 26-27 and
`
`Page 19 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`drivers and to the
`
`transistor group 28-29) and to the voltage precharge source
`
`voltage precharge
`
`(e_g., BLR). See, e.g., Sukegawa Fig. 1 (armotated below).
`
`source; aid [sic]
`
`Voltage precharge source
`
`“As shown in FIG. 1, in this intermediate amplifier circuit 1,
`
`positive line LINE which connects connecting terminal 3a of
`
`equalizer circuit 3 and input terminal 4a of receiver circuit 4 is
`
`connected to input/output shared terminal la at node 101, and
`
`negative line N-LINE (where N- represents the negative side)
`
`which connects output terminal 3b of equalizing circuit 3 and
`
`input
`
`terminal 4b of receiver circuit 4 is connected to
`
`input/output shared terminal lb at node 102.” Sukegawa 6:54-
`
`61.
`
`18
`
`Page 20 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`One of ordinary skill in the art at the time of the alleged
`
`invention of the ’130 Patent would have recognized LINE and
`
`develop on these two bus lines. See, e.g., Sukegawa 7:38-43.
`
`LINE_ as the “differential bus” because a voltage differential
`
`(i.e., a difference in voltages between the two bus lines) can
`
`a latching sense
`
`Sukegawa discloses a latching sense amplifier (shown in
`
`amplifier coupled purple) coupled to the differential bus (e.g., LINE, LINE_)_
`
`to the differential
`
`See, e.g., Sukegawa Fig. 1 (annotated below).
`
`bus;
`
`Latching sense
`amplifier
`
`FIG.
`
`7
`
`
`
`BS7
`I
`
`
`
`—
`
`6
`
`The purple box drawn above for the latching sense amplifier is
`
`consistent with Petitioner’s proposed construction of “latching
`
`sense amplifier,” as it is a circuit, including a latch, that detects
`
`19
`
`Page 21 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`and amplifies signals. Each intermediate amplifier 1, 1A, and
`
`1B provides a latch that detects and amplifies the signal on
`
`LINE and LINE_. See, e.g., Sukegawa Fig. 2, 7: 1-8:6.
`
`Sukegawa further discloses that “[a]s shown in FIG. 1, in this
`
`intermediate amplifier circuit 1, positive line LINE which
`
`connects connecting terminal 3a of equalizer circuit 3 and
`
`input
`
`terminal 4a of receiver circuit 4 is connected to
`
`input/output shared terminal la at node 101, and negative line
`
`N—LINE (where N— represents the negative side) which
`
`connects output terminal 3b of equalizing circuit 3 and input
`
`terminal 4b of receiver circuit 4 is connected to input/output
`
`shared terminal lb at node 102.” Sukegawa 6:54-61.
`
`wherein the
`
`Sukegawa discloses a latching sense amplifier
`
`(shown in
`
`latching sense
`
`purple) wherein a first stage (e.g., IN AMP 1, shown in light
`
`amplifier
`
`blue) includes a cross-coupled latch (e.g., transistors 10, 11,
`
`comprises: a first
`
`14, 15) coupled to a differential data bus (pink lines). See, e.g.,
`
`stage including a
`
`Sukegawa Fig. 1 (annotated below).
`
`cross-coupled
`
`latch coupled to a
`
`Page 22 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`differential data
`
`bus; and
`
`Differential
`
`data bus
`
`The light blue box drawn above for the first stage is consistent
`
`with Petitioner’s proposed construction of “stage,” as it is a
`
`“portion of a circuit.” Namely, the first stage is a portion of the
`
`latching sense amplifier. In particular, intermediate amplifier 1
`
`latches and amplifies voltages received through nodes la and
`
`lb, and outputs the amplified voltages through the same nodes.
`
`See, e.g., Sukegawa 7:1-8:6.
`
`Fig. 2 of Sukegawa further discloses the first stage and its
`
`cross—coupled latch: “a circuit diagram illustrating the specific
`
`Page 23 of 83
`
`21
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`configuration of the first
`
`intermediate amplifier circuit 1.”
`
`Sukegawa 6:66-67.
`
`PMOS part of cross-coupled latch
`
`NMOS part of cross-coupled latch
`
`One of ordinary skill
`
`in the an at the time of the alleged
`
`invention of the ’l30 Patent would have recognized, based on
`
`Sukegawa’s disclosure, that the cross-coupled latch comprises
`
`of transistors 10, ll, 14, and 15 because these transistors act to
`
`regenerate full logic levels (both high and low) on LINE and
`
`LINE_. See, e.g., Sukegawa 9: 14-21.
`
`Page 24 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Moreover,
`
`these transistors are cross—coupled because the
`
`output of a first transistor (e.g., 10) is tied to the input of a
`
`second transistor (e.g., 11), and the output of the second
`
`transistor (e.g., 11) is tied to the input of the first transistor
`
`(e.g., 10).
`
`Output of transistor 10 connected
`to input of transistor 11
`
`Output of transistor 11 connected
`to input of transistor 10
`
`Likewise, the output of transistor 14 is tied to the input of
`
`transistor 15, and vice versa.
`
`23
`
`Page 25 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Output of transistor 15 connected
`to input of transistor 14
`
`Output of transistor 14 connected
`to input of transistor 15
`
`The first stage is further coupled to the differential data bus Via
`
`LINE, LINE_ and transistors 34, 35 (see e.g., Sukegawa Fig. 1
`
`(annotated below), 6:54-61):
`
`Page 26 of 83
`
`24
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Differential
`
`data bus
`
`Coupling first stage to
`
`differential data bus
`
`One of ordinary skill in the art at the time of the alleged
`
`invention of the ’130 Patent would have recognized lines
`
`associated with nodes C (shown above in pink) as the
`
`“differential data bus” because the pink highlighted lines
`
`represent an amplified voltage differential representative of the
`
`data to be read out by the latching sense amplifier. See, e.g.,
`
`Page 27 of 83
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Sukegawa 9:14-24. Indeed, one of ordinary skill in the art at
`
`the time of the alleged invention of the ’ 130 Patent would have
`
`understood the pink highlighted lines to include differential
`
`data because of the amplified voltage differential on these
`
`lines.
`
`Moreover, Fig. 5 of Sukegawa also teaches one intermediate
`
`amplifier (i.e. first stage) prior to the receiver circuit 4 (as
`
`discussed below, the receiver circuit is Sukegawa’s “output
`
`stage”), and thus the first stage and the differential data bus
`
`can be coupled without going through additional intermediate
`
`amplifiers:
`
`an output stage
`
`Sukegawa discloses a latching sense amplifier wherein an
`
`coupled to an
`
`output stage (e.g., receiver circuit 4, shown in orange) is
`
`output of said
`
`coupled to an output of the first stage (e.g., IN AMP 1, shown
`
`first stage;
`
`in light blue), and wherein the output of the first stage is
`
`wherein the
`
`coupled to an input of the output stage. See, e.g., Sukegawa
`
`Page 28 of 83
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`Claim Language
`
`Sukegawa and Lu
`
`output of the first
`
`Fig. 1 (annotated below).
`
`stage is coupled
`
`to an input of the
`
`output stage;
`
` _ ._._
`
`.
`
`‘_
`
`‘
`
`0
`
`V
`
`Output of first stage coupled
`
`to input ofoutput stage
`
`
`
`The orange box drawn above for the output stage comprises of
`
`receiver circuit 4 and is consistent with Petitioner’s proposed
`
`construction of “stage,” as it
`
`is a “portion of a circuit.”
`
`Namely, the output stage is a portion of the latching sense
`
`amplifier circuit. In particular, the identified “output stage”
`
`Page 29 of 83
`
`27
`
`
`
`Claim Language
`
`Sukegawa and Lu
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent No. 6,366,130
`
`performs the function of receiving and driving the output
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
