IPR-2015-01524
`
`Case No. IPR2015-01524
`U.S. Patent No. 6,366,130
`
`Attorney Docket No.
`ELBRUS-IPR2
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________
`
`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED
`
`Patent Owner
`
`_______________
`
`Case: IPR2015-01524
`
`U.S. Patent No. 6,366,130
`
`PATENT OWNER'S RESPONSE
`
`

`
` IPR-2015-01524
`
`IPR-2015-01524
`
`TABLE OF CONTENTS
`
`TABLE OF CONTENTS
`
`I.
`
`I.
`
`INTRODUCTION ............................................................................... 1
`
`INTRODUCTION ............................................................................. .. 1
`
`II. BACKGROUND ................................................................................. 2
`
`II. BACKGROUND ............................................................................... .. 2
`
`A. Other inter partes review.................................................................... 2
`A. Other inter partes review .................................................................. .. 2
`
`B. The `130 Patent................................................................................... 2
`
`B. The ‘130 Patent ................................................................................. .. 2
`
`C. Reexamination.................................................................................... 5
`
`C. Reexamination .................................................................................. .. 5
`
`D. Claims of the `130 Patent in trial ........................................................ 6
`
`D. Claims of the ‘ 130 Patent in trial ...................................................... .. 6
`
`III.
`
`III.
`
`INTERPRETATION OF THE `130 PATENT CLAIMS...................... 8
`
`INTERPRETATION OF THE ‘ 130 PATENT CLAIMS .................... .. 8
`
`A. Person of ordinary skill in the art........................................................ 8
`A. Person of ordinary skill in the art ...................................................... .. 8
`
`B. Claim Construction............................................................................. 9
`
`B. Claim Construction ........................................................................... .. 9
`
`C. Expert ................................................................................................12
`C. Expert .............................................................................................. ..12
`
`IV. PRIOR ART........................................................................................13
`
`IV. PRIOR ART ...................................................................................... ..13
`
`A. Sukegawa Patent No. 5,828,241 ........................................................13
`A. Sukegawa Patent No. 5,828,241 ...................................................... ..13
`
`B. Lu et al. JSSC Article ........................................................................14
`
`B. Lu et al. JSSC Article ...................................................................... ..14
`
`C. Watanabe et al. Patent No. 6,108,254 ................................................15
`C. Watanabe et al. Patent No. 6,108,254 .............................................. ..15
`
`D. Hardee Patent No. 6,249,469 .............................................................16
`D. Hardee Patent No. 6,249,469 ........................................................... ..16
`
`V. CHALLENGE 1 (OBVIOUSNESS OVER SUKEGAWA IN VIEW
`V. CHALLENGE 1 (OBVIOUSNESS OVER SUKEGAWA IN VIEW
`OF LU) FAILS TO ESTABLISH A PRIMA FACIE CASE OF
`OF LU) FAILS TO ESTABLISH A PRIMA FACIE CASE OF
`OBVIOUSNESS FOR CLAIMS 1, 2, 5, 6 AND 9......................................17
`OBVIOUSNESS FOR CLAIMS 1, 2, 5, 6 AND 9 .................................... ..17
`
`i
`
`

`
` IPR-2015-01524
`
`IPR-2015-01524
`
`A. The Combination of Sukegawa and Lu Fails to Teach a Differential
`A. The Combination of Sukegawa and Lu Fails to Teach a Differential
`
`Data Bus. .................................................................................................18
`
`Data Bus. ............................................................................................... ..18
`
`B. Sukegawa Fails to Precharge to a Voltage Between 0 and Vdd..........26
`B. Sukegawa Fails to Precharge to a Voltage Between 0 and Vdd........ ..26
`
`C. Sukegawa Teaches Away. .................................................................28
`C. Sukegawa Teaches Away. ............................................................... ..28
`
`D. Petitioner's Solution is Unworkable in Practice..................................30
`
`D. Petitioner's Solution is Unworkable in Practice ................................ ..3O
`
`E. Lu Fails to Precharge. ........................................................................34
`E. Lu Fails to Precharge. ...................................................................... ..34
`
`F. Claim 5..............................................................................................37
`
`F. Claim 5. ........................................................................................... ..37
`
`G. The Petitioner Uses Hindsight Reasoning to Prove Obviousness .......43
`G. The Petitioner Uses Hindsight Reasoning to Prove Obviousness ..... ..43
`
`H. The Petitioner Fails to Make a Prima Facie Case of Obviousness......45
`
`H. The Petitioner Fails to Make a Prima Facie Case of Obviousness. .....45
`
`VI. CHALLENGE 2 (OBVIOUSNESS OVER SUKEGAWA AND LU IN
`VI. CHALLENGE 2 (OBVIOUSNESS OVER SUKEGAWA AND LU IN
`VIEW OF WATANABE) FAILS TO ESTABLISH A PRIMA FACIE CASE
`VIEW OF WATANABE) FAILS TO ESTABLISH A PRIMA FACIE CASE
`OF OBVIOUSNESS FOR CLAIM 3..........................................................46
`OF OBVIOUSNESS FOR CLAIM 3. ....................................................... ..46
`
`VII. CHALLENGE 3 (OBVIOUSNESS OVER SUKEGAWA AND LU IN
`VII. CHALLENGE 3 (OBVIOUSNESS OVER SUKEGAWA AND LU IN
`VIEW OF HARDEE) FAILS TO ESTABLISH A PRIMA FACIE CASE OF
`VIEW OF HARDEE) FAILS TO ESTABLISH A PRIMA FACIE CASE OF
`OBVIOUSNESS FOR CLAIM 7................................................................50
`OBVIOUSNESS FOR CLAIM 7. ............................................................. ..50
`
`VIII. CONCLUSION .................................................................................56
`
`VIII. CONCLUSION ............................................................................... ..56
`
`ii
`
`

`
` IPR-2015-01524
`
`TABLE OF AUTHORITIES
`
`Cases
`
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005, en banc) .............. 9
`
`In re Royka, 490 F.2d 981 (CCPA 1974) .................................................. 18
`
`Monarch Knitting Mach. Corp. v. Sulzer Morat GmbH, 139 F.3d 877,
`U.S.P.Q.2d 1977 (Fed. Cir. 1998) ...................................................... 29, 45
`
`In re Keller, 642 F.2d 413, 425 (CCPA 1981) .......................................... 44
`
`In re Fine, 837 F.2d 1071, 1076, 5 U.S.P.Q.2d 1596, 1600
`(Fed. Cir. 1988).......................................................................................... 45
`
`Statutes
`35 U.S.C. § 103
`35 U.S.C. § 316(a)(8)
`
`Rules
`37 C.F.R. § 42.100(b)
`37 C.F.R. § 42.120
`
`Other Authorities
`
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48764
`(Aug. 14,2012)
`
`Manual of Patent Examining Procedure (M.P.E.P.)
`
`iii
`
`

`
` IPR-2015-01524
`
`LIST OF EXHIBITS RELIED UPON
`
`Exhibit 1001 - U.S. Patent No. 6,366,130 ("the `130 patent").
`
`Exhibit 1002 - Declaration of Dr. Baker.
`
`Exhibit 1005 - U.S. Patent No. 5,828,241 (Sukegawa).
`
`Exhibit 1006 - U.S. Patent No. 6,108,254 (Watanabe et al.).
`
`Exhibit 1007 - U.S. Patent No. 6,249,469 (Hardee).
`
`Exhibit 1008 - Nicky Chau-Chun Lu and Hu H. Chao, Half-VDD Bit-Line
`Sensing Scheme in CMOS DRAM's, IEEE Journal of Solid
`State Circuits, Vol. SC-19, No. 4, August 1984.
`
`Exhibit 2001 (cid:8211) (cid:8220)Action Closing Prosecution(cid:8221) - Reexamination Control No.
`95/000,657.
`
`Exhibit 2002 - Brent Keeth and R. Jacob Baker, DRAM Circuit Design - A
`Tutorial, IEEE Press Series on Microelectronic Systems,
`2001, pp. 26-29.
`
`Exhibit 2003 - Deposition of R. Jacob Baker Ph.D., Las Vegas, NV, April 1,
`2016.
`
`Exhibit 2004 - Declaration of William R. Huber D.Sc., P.E. in Support of
`Patent Owner's Response to Petition.
`
`Exhibit 2005- JEDEC Dictionary of Terms for Solid State Technology,
`JESD88E.
`
`Exhibit 2006- JEDEC Standard No. 8-1, Addendum No. 1 to JEDEC
`Standard No. 8, (cid:8220)Interface Standard for Low Voltage TTL-
`Compatible (LVTTL) VLSI Digital Circuits,(cid:8221) Electronic
`Industries Association, Washington, D.C., December 1984.
`(Ex. 2006).
`
`Exhibit 2007 (cid:8211) JEDEC Standard JESD79E (Revision of JESD79D), (cid:8220)Double
`Data Rate (DDR) SDRAM Specification,(cid:8221) JEDEC Solid State
`
`iv
`
`

`
` IPR-2015-01524
`
`Technology Association 2005, Arlington, VA, May 2005.
`(Ex. 2007).
`
`Exhibit 2008 - Semiconductor Memories, A Handbood of Design,
`Manufacture and Application, 2nd Ed., John Wiley and Sons,
`1983, 1991 - Title page, Copyright page and Index - cited by
`Huber Declaration Ex. 2004, ¶ 34.
`
`Exhibit 2009 - Wikipeda page, https://en.wikipedia.org/wiki/Node_(circuits)
`Cited by Huber Declaration Ex. 2004, ¶ 58.
`
`v
`
`

`
` IPR-2015-01524
`
` I. INTRODUCTION
`Pursuant to 35 U.S.C. § 316(a)(8) and 37 C.F.R. § 42.120, the Patent
`
`Owner provides this Response to the Petition for Inter Partes Review filed
`
`on October 24, 2014. This Response is timely filed.
`
`The issues for trial are whether the Petitioner has met its burden to
`
`show that (a) claims 1, 2, 5, 6 and 9 of the (cid:8216)130 Patent are unpatentable
`
`under 35 U.S.C. § 103 as obvious over (cid:8220)Sukegawa" in view of "Lu(cid:8221) (herein
`
`(cid:8220)Challenge 1(cid:8221)), (b) claim 3 as obvious over (cid:8220)Sukegawa(cid:8221) and "Lu" in view
`
`of (cid:8220)Watanabe(cid:8221) (herein (cid:8220)Challenge 2(cid:8221)) and (c) claim 7 over "Sukegawa" and
`
`"Lu" in view of "Hardee" (herein "Challenge 3").
`
`Sukegawa (Ex. 1005) is U.S. Patent No. 5,828,241. Watanabe et al.
`
`(Ex. 1006) is U.S. Patent No. 6,108,254. Hardee (Ex. 1007) is U.S. Patent
`
`No. 6,249,469. Lu (Ex. 1008) is the article "Half-VDD Bit-Line Sensing
`
`Scheme in CMOS DRAM's, IEEE Journal of Solid State Circuits.
`
`As explained herein and in the accompanying declaration of Dr.
`
`William Huber (Ex. 2004), the Petitioner fails to show by a preponderance
`
`of the evidence that any of the three challenges prevail.
`
`1
`
`

`
` IPR-2015-01524
`
` II. BACKGROUND
`
`A. Other inter partes review
`This trial concerns one of two inter partes review petitions directed at
`
`the '130 Patent. In addition to this trial, the same petitioner filed IPR2015-
`
`01523 directed at the same claims but with different cited art. The Board
`
`denied institution of a trial in IPR2015-01523 on January 9, 2016 and
`
`instituted trial in the instant case on the same date.
`
`The `130 Patent
`
`B.
`The (cid:8216)130 patent describes circuitry for efficiently transferring data
`
`signals at high speeds while consuming low power. The arrangement
`
`includes a sense amplifier with two separate precharged buses, a differential
`
`bus and a differential data bus. These buses operate on alternate clock
`
`phases: one bus is being precharged while the other is transferring data and
`
`vice versa.
`
`2
`
`

`
` IPR-2015-01524
`
`Fig. 2 above is the sensing amplifier shown as a box with the letters
`
`SA in it in Fig. 1. This is stated in Col. 2, lines 39-40 of the `130 Patent.
`
`The first bus, the differential bus, consists of the lines marked LT and
`
`LC in Fig. 1. The second bus, the differential data bus, consists of the two
`
`lower lines running between the left and right of the circuit in Fig. 2, the line
`
`running from N3 to N6, and the line running from N2 to N8. (See Ex. 2004,
`
`Huber Dec.¶ 47, Figure B for an annotated drawing).
`
`Several factors of the claimed invention of the (cid:8216)130 patent contribute
`
`to the higher data transfer speeds, lower power, and reduced sensitivity to
`
`component and environmental variations. According to the `130 patent,
`
`"The data transfer arrangement in accordance with the present invention
`
`provides an increase in speed due to the differential low voltage swing bus
`
`drive in combination with the use of the latched differential sense amplifier
`
`as the bus receiver." (Ex. 1001, `130 patent, 3:12-16). The differential bus
`
`and the differential data bus each precharge to a specific level between
`
`ground and Vdd, namely Vpr = K * Vdd, where 0 < K < 1 and K = 1/3 for
`
`the ideal MOS model. (See id 3:23-30). This precharging to a specific level
`
`between ground and Vdd also provides high noise immunity for both buses.
`
`(See id 3:40-45; See also e.g. Ex 2004, Declaration of Dr. William Huber, ¶
`
`30).
`
`3
`
`

`
` IPR-2015-01524
`
`(Ex. 1001,(cid:8217)130 patent, 1:42-55).
`
`As identified in the specification, the factors that lead to higher
`
`speeds, lower power and reduced sensitivity include:
`
`(Ex. 1001,(cid:8217)130 patent, 3:12-16).
`
`4
`
`

`
` IPR-2015-01524
`
`(id, 3:17-23).
`
`(id., 3:23-30).
`
`(id., 3:40-45).
`
`(id., 3:56-63).
`
`C. Reexamination
`An inter partes reexamination with Control No. 95/000,657 was
`
`instituted by a different party in 2012. A reexamination certificate was
`
`5
`
`

`
` IPR-2015-01524
`
`issued in August 2014 holding that claims 1-2 and 5-7 remained patentable
`
`over the Hardee (Ex. 1007) reference cited in this IPR and other art, that
`
`claims 3-4 and 8 were not reexamined, and adding new claim 9.
`
`In closing the reexamination, the examiner confirmed that the Hardee
`
`reference fails to disclose two buses charged as required by claim 1. (Ex.
`
`2001).
`
`D. Claims of the `130 Patent in trial
`Claims 1, 2, 3, 5, 6, 7 and 9 are challenged.
`
`Claim 1
`1.
`A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source; aid [sic]
`a differential bus coupled to the bus drivers and to the voltage
`precharge source;
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an input of the
`output stage;
`wherein the differential bus and the differential data bus are
`precharge[d] to a voltage Vpr between Vdd and ground, where
`Vpr=K*Vdd, and K is a precharging voltage factor.
`
`6
`
`

`
` IPR-2015-01524
`
`(Emphasis added).
`
`Emphasis has been added to the claim to show that there are two
`
`different buses claimed 1) the differential bus, and 2) the differential data
`
`bus; and that both of them must be precharged.
`
`Claim 2
`2.
`The data transfer arrangement in accordance with claim 1
`wherein the bus drivers comprise active pull up and active pull-down
`bus drivers.
`
`Claim 3
`3.
`The data transfer arrangement in accordance with claim 1,
`wherein the first stage of the latching sense amplifier comprises: a
`plurality of input pass transistors each having a gate, a source
`terminal, and a drain; and a plurality of NMOS and PMOS transistors
`each having a gate, a source terminal, and a drain; wherein the drains
`of the input pass transistors are coupled to the drains of the cross-
`coupled latch amplifier NMOS and PMOS transistors, each source
`terminal of the input pass transistors is coupled to an input, the
`sources of the cross-coupled latch amplifier NMOS transistors are
`coupled to the drain of the NMOS transistor coupled to a clock signal
`input, and the sources of the PMOS transistors are coupled to the
`drain of the PMOS transistor having a gate coupled to an inverted
`clock signal input.
`
`Claim 5
`
`7
`
`

`
` IPR-2015-01524
`
`The data transfer arrangement in accordance with claim 1,
`5.
`wherein the voltage precharge source is configured to precharge the
`differential bus to a predetermined voltage that is less than a logic
`high voltage and greater than a logic low voltage.
`
`Claim 6
`6.
`The data transfer arrangement in accordance with claim 1
`further comprising a precharge circuit coupled between the precharge
`source and the differential bus.
`
`Claim 7
`7.
`The data transfer arrangement in accordance with claim 2
`wherein the active pull up and pull down bus drivers are NMOS
`transistors.
`
`Claim 9
`9.
`The data transfer arrangement of claim 1 wherein the output
`stage includes cross-coupled feedback.
`
`
`
` III.
`
`INTERPRETATION OF THE `130 PATENT CLAIMS
`
`Person of ordinary skill in the art
`
`A.
`In its Decision to institute trial on January 19, 2016, the Board agreed
`
`with the Petitioner that a person of ordinary skill in the art at the time of the
`
``130 patent (February 1999) would have had an undergraduate degree in
`
`Electrical Engineering or equivalent and at least two to three years of
`
`8
`
`

`
` IPR-2015-01524
`
`experience in the design and/or analysis of data transfer circuits or the
`
`equivalent. (See Paper 9, Decision to Institute Trial, footnote p. 7).
`
`B. Claim Construction
`
`(cid:8220)During patent examination, the pending claims must be (cid:8216)given their
`
`broadest reasonable interpretation consistent with the specification(cid:8217)(cid:8221).
`
`M.P.E.P. § 2111 referring to Phillips v. AWH Corp., 415 F.3d 1303 (Fed.
`
`Cir. 2005, en banc). The statement has two parts: 1) broadest reasonable
`
`interpretation, and 2) consistent with the specification. The M.P.E.P. also
`
`requires the use of the ordinary meaning of a word to a person of ordinary
`
`skill in the art unless it is otherwise defined by the specification. See
`
`M.P.E.P. § 2111.01(III). Strange or unusual meanings are not allowed
`
`unless specifically elucidated in the specification. In an inter partes review,
`
`the Board applies the same standard. Office Practice Trial Practice Guide,
`
`77 Fed. Reg. 48,756 48, 764 (Aug. 14, 2012).
`
`The Petitioner proposes that two claim terms be construed by the
`
`Board: 1) (cid:8220)latching sense amplifier,(cid:8221) and 2) (cid:8220)stage.(cid:8221) As discussed in Patent
`
`Owner(cid:8217)s Preliminary Response (Paper 8) both of these terms were in
`
`common use in the relevant time period, and would have been clearly
`
`understood by a person of ordinary skill at that time.
`
`9
`
`

`
` IPR-2015-01524
`
`For (cid:8220)latching sense amplifier(cid:8221), the Petitioner wants the term to be
`
`construed to mean: (cid:8220)a circuit, including a latch, that detects and amplifies
`
`signals(cid:8221). The Petitioner has introduced two new words for no reason: 1)
`
`(cid:8220)circuit(cid:8221) and 2) (cid:8220)detects.(cid:8221) There is absolutely no reason to introduce new
`
`and undefined terms. The term (cid:8220)latching sense amplifier(cid:8221) is self-
`
`explanatory to the person of ordinary skill, namely it is a sense amplifier that
`
`can latch data. Sense amplifiers are well-known in the art, and have been
`
`used since at least the late nineteen-fifties to sense low level read signals
`
`from computer memories. The function and use of sense amplifiers has not
`
`changed, merely their size, and the components used to realize them, as well
`
`as the types of memory cells they are reading.
`
`In the book, (cid:8220)DRAM Circuit Design(cid:8212)A Tutorial,(cid:8221) (Ex. 2002), co-
`
`authored by Petitioner(cid:8217)s expert, R. Jacob Baker and first published in 2001,
`
`many sense amplifier designs and their operation are discussed in detail. But
`
`nowhere is there a definition of (cid:8220)sense amplifier.(cid:8221) The closest such
`
`statement seeks to define the function of sensing and appears on p. 22:
`
`(cid:8220)Sensing is essentially the amplification of the digitline signal or the
`
`differential voltage between the digitlines.(cid:8221) (See, Ex. 2004, Huber Dec., ¶
`
`34).
`
`10
`
`

`
` IPR-2015-01524
`
`The word (cid:8220)latching(cid:8221) itself was also well-known in the art. A person
`
`of ordinary skill in the art knows that electrical circuits that handle digital
`
`data can either pass data (unlatched), or hold data that was present when the
`
`circuit activated or clocked (latched). For this reason, the term (cid:8220)latching
`
`sense amplifier(cid:8221) needs no further definition and should be given its ordinary
`
`meaning. For these reason, the term (cid:8220)latching sense amplifier(cid:8221) needs no
`
`further definition and should be given its ordinary meaning.
`
`The Petitioner also states that the construction of the term latching
`
`sense amplifier should implicitly include a definition of a cross-coupled
`
`latch (Paper 1, Petition p. 10). The Board should not construe this term
`
`based on the Petitioner's statement. If the Petitioner thought that the term
`
`cross-coupled latch should be construed by the Board, it should have
`
`included an argument as to why.
`
`The Petitioner proposes construing the word (cid:8220)stage(cid:8221) as (cid:8220)a portion of a
`
`circuit.(cid:8221) This word also has been in extremely common use in circuit design
`
`for many years. However, the Petitioner(cid:8217)s proposed construction is broader
`
`than what a person of ordinary skill in the art would understand the term to
`
`mean. A portion of a circuit could be anything from a single transistor to
`
`something with thousands of components. On the other hand, the person of
`
`ordinary skill will understand that a (cid:8220)stage(cid:8221) is a portion of a circuit that has
`
`11
`
`

`
` IPR-2015-01524
`
`an input, an output and some functionality. In other words, a stage is a
`
`functional unit in a circuit and usually can be given a name such as an
`
`oscillator, a register, a latch or the like.
`
`This term is so well understood in the art that it does not need a new
`
`definition. The term (cid:8220)stage(cid:8221) should be given its ordinary meaning. (see Ex.
`
`2004, ¶ 35).
`
`In its decision to institute trial, the Board determined that no express
`
`claim construction was required for purposes of that Decision (Paper 9, p. 5).
`
`C. Expert
`The Patent Owner has retained Dr. William R. Huber D.Sc., PE, an
`
`expert in the relevant technology, to provide technical support in explaining
`
`and discussing the `130 Patent, the prior art, and the allegations of
`
`obviousness asserted by the Petitioner. Dr. Huber has twenty years(cid:8217)
`
`experience at AT&T Bell Laboratories and many years(cid:8217) experience
`
`designing memories (see Ex. 2004, Appendix A, Huber Curriculum Vitae).
`
`Dr. Huber's Declaration ("Huber Dec.") is Exhibit 2004 and will be referred
`
`to throughout this reply.
`
`12
`
`

`
` IPR-2015-01524
`
`
`
` IV. PRIOR ART
`
`Sukegawa Patent No. 5,828,241
`
`A.
`The Sukegawa reference describes a signal transmission circuit that
`
`transmits signals from point to point over a wire that allows the distance of
`
`signal transmission to be increased. The circuit uses positive feedback in an
`
`intermediate amplifier.
`
`(Ex. 1005, Sukegawa Abstract).
`
`The following figure shows the Sukegawa invention:
`
`(Ex. 1005, Sukegawa Fig. 1).
`
`Sukegawa transmits data over large distances:
`
`13
`
`

`
` IPR-2015-01524
`
`In these figures, A represents the signal transmission circuit
`used in the case when the signal transmission distance is very
`long, such as when the wiring length is over 2 cm. This signal
`transmission circuit A comprises several intermediate amplifier
`circuits 1, 1A, 1B with the same circuit configuration, a driver
`circuit 2, an equalizer circuit 3, and a receiver circuit 4.
`
`(Ex. 1005, Sukegawa 6:47-53).
`
`The input side takes a single-ended signal data input line, passes the
`
`signal through an input stage and onto the transmission line or transmission
`
`bus. This bus can be precharged with a voltage from the BLR line when the
`
`PC control line is activated. The bus passes across several parallel in-amps
`
`which are connected to an output latch at the end of the transmission line.
`
`These in-amps are distributed along the transmission line. The latch couples
`
`into an output driver that drives an output.
`
`Lu et al. JSSC Article
`
`B.
`Lu is an early (1984) IEEE paper on precharging bit lines in a dynamic
`
`random access memory.
`
`14
`
`

`
` IPR-2015-01524
`
`(Ex. 1008, p. 2, col. 2).
`
`Abstract - A sensing scheme in which the bit line is precharged
`to half Vdd is introduced for CMOS DRAM's. The study
`shows that the half-Vdd bit-line sensing scheme has several
`unique advantages, especially for high-performance high
`density CMOS DRAM's when compared to the full-Vdd bit-
`line sensing scheme used for NMOS memory arrays or the
`grounded bit-line sensing scheme for PMOS arrays in CMOS
`DRAM's.
`
`Exhibit (1008, p. 1, col. 1).
`
`C. Watanabe et al. Patent No. 6,108,254
`Watanabe teaches a DRAM memory where a data buffer is connected
`
`between first and second data lines with an equalizing circuit in between.
`
`15
`
`

`
` IPR-2015-01524
`
`(Ex. 1006, Fig. 1)
`
`Abstract - A Dynamic Random Access Memory (DRAM) in
`which a data input/output buffer is connected between first data
`lines and second data lines. An equalizing circuit and a data
`latch circuit are connected to the second data lines. The
`equalizing circuit maintains the second data lines in reset
`condition, during normal operation. It temporarily releases the
`second data lines from the reset condition, in response to an
`output from an address-transition detecting circuit, thereby to
`transfer the data from the data input/output buffer. The data
`latch circuit latches the data transferred to the second data lines,
`in response to the output from the address-transition detecting
`circuit.
`
`(Ex. 1006, Abstract).
`
`D. Hardee Patent No. 6,249,469
`
`Hardee is a sense amplifier for a CMOS memory chip.
`
`16
`
`

`
` IPR-2015-01524
`
`(Ex. 1007, Fig. 5).
`
`Abstract - A sense amplifier for a very high density integrated
`circuit memory using CMOS technology is described. Each
`sense amplifier includes first and second local sense amplifier
`drive transistors, one connecting the P channel transistors to
`VCC; the other connecting the N channel transistors to VSS...
`
`(Ex. 1007, Beginning of Abstract).
`
` V. CHALLENGE 1 (OBVIOUSNESS OVER SUKEGAWA IN
`VIEW OF LU) FAILS TO ESTABLISH A PRIMA FACIE CASE
`OF OBVIOUSNESS FOR CLAIMS 1, 2, 5, 6 AND 9.
`
`The Petitioner fails to make a prima facie case of obviousness in the
`
`combination of Sukegawa and Lu for the following reasons:
`
`1)
`
`There is no differential data bus (second bus) taught or
`
`suggested in either Sukegawa or Lu.
`
`17
`
`

`
` IPR-2015-01524
`
`2)
`
`The combination of Sukegawa and Lu fails to teach or suggest
`
`precharging two buses to Vpr = K * Vdd, where K is between 0 and 1.
`
`3)
`
`4)
`
`Sukegawa teaches away from the `130 invention;
`
`The Petitioner's solution is unworkable in practice.
`
`The law of obviousness states that a patent may not be obtained if the
`
`differences between the claimed invention and the prior art are such that the
`
`claimed invention as a whole would have been obvious to a person of
`
`ordinary skill in the art before the effective filing date of the claimed
`
`invention. (Paraphrasing 35 U.S.C. § 103). For a rejection under Section
`
`103, the Patent Office must first establish a prima facie case of obviousness.
`
`A prima facie case of obviousness of a claimed invention requires that all
`
`the claim features must be taught or suggested by the prior art. See In re
`
`Royka, 490 F.2d 981 (CCPA 1974). See also M.P.E.P. § 2142.
`
`A. The Combination of Sukegawa and Lu Fails to Teach a
`Differential Data Bus.
`
`Claim 1 of the (cid:8216)130 patent requires inter alia, (cid:8220)a differential bus
`
`coupled to the bus drivers and to the voltage precharge source(cid:8221) and (cid:8220)a first
`
`stage including a cross-coupled latch coupled to a differential data bus.(cid:8221) The
`
`Petitioner supplies the following annotated figure (Paper 1, Petition, p. 22)
`
`based on Fig. 1 of Sukegawa:
`
`18
`
`

`
` IPR-2015-01524
`
`where it is asserted that the lines annotated in green represent a differential
`
`bus, and the lines annotated in pink represent a differential data bus.
`
`The Petitioner states on p. 22 of the Petition: "One of ordinary skill in
`
`the art at the time of the alleged invention of the `130 Patent would have
`
`recognized lines associated with nodes C (shown above in pink) as the
`
`"differential data bus" because the pink highlighted lines represent an
`
`amplified voltage differential representative of the data to be read out by the
`
`latching sense amplifier. Indeed, one of ordinary skill in the art at that time
`
`of the alleged invention of the `130 Patent would have understood the pink
`
`highlighted lines to include differential data because of the amplified voltage
`
`differential on these lines."
`
`19
`
`

`
` IPR-2015-01524
`
`There are two critical flaws with the Petitioner(cid:8217)s assertion that nodes
`
`C should be recognized as the (cid:8220)differential data bus(cid:8221). First, the Petitioner
`
`improperly identifies nodes C as a bus. Second, the fact that a pair of nodes
`
`exhibits differential voltage does not make the pair of nodes a bus. Because
`
`the combination of Sukegawa and Lu lacks a differential data bus, the
`
`Petitioner fails to make a prima facie case of obviousness.
`
`1) Nodes C are simply nodes (cid:8211) not a bus
`
`In Figure 1 of Sukegawa above, the Petitioner improperly identifies
`
`nodes (cid:8220)C(cid:8221) as the (cid:8220)differential data bus(cid:8221) of the (cid:8216)130 patent (Nodes marked
`
`"C" are at the junctions of the pink lines and are also marked (cid:8220)N3(cid:8221) and
`
`(cid:8220)N4(cid:8221)). Quoting from the Patent Owner(cid:8217)s expert Dr. Huber:
`
`The nodes in this figure labeled as (cid:8220)C(cid:8221), are also labeled (cid:8220)N3(cid:8221)
`and (cid:8220)N4,(cid:8221) indicating that they are considered by the inventor of
`the (cid:8216)241 patent to be nodes. Just because the Petitioner labels a
`portion of a circuit as a bus does not make that portion a bus.
`Nodes (cid:8220)C(cid:8221) are indeed circuit nodes, but they do not constitute a
`bus. (Ex. 2004, Huber Dec, ¶ 55).
`
`In electronics, a node is defined as (cid:8220)within a circuit, a point of
`interconnection between two or more components.(cid:8221)1 For two
`
`
`1 JEDEC(cid:8212)Global Standards for the Microelectronics Industry. JEDEC is
`the body recognized for establishing standards for integrated circuits and
`
`20
`
`

`
` IPR-2015-01524
`
`nodes to be different, their voltages must be different. When
`looking at circuit schematics, ideal wires have a resistance of
`zero. Since it can be assumed that there is no change in the
`potenti