Case IPR2015-01524
`U.S. Patent 6,366,130
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`Case: IPR2015-01524
`U.S. Patent No. 6,366,130
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`DECLARATION OF WILLIAM R. HUBER, D.Sc., P.E. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`IPR2015-01524
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`Case IPR2015-01524
`U.S. Patent 6,366,130
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`Table of Contents
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`I.
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`Executive Summary
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`II.
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`Introduction
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`III. Qualifications
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`IV. Obviousness Law
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`V. Level of Skill in the Art
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`VI. The 6,366,130 Patent
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`VII. Disputed Claims of the ‘130 Patent
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`VIII. Claim Construction
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`IX. Alleged Prior Art
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`X. Patent Trial and Appeal Board Decision to Institute
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`XI. Discussion of ‘130 Claims and Alleged Prior Art
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`A.
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`Independent Claim 1
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`B.
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`C.
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`D.
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`E.
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`1. What is K?
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`2.
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`3.
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`4.
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`5.
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`The Sukegawa ‘241 Reference
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`Nodes and Buses
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`Precharging of Nodes “C”
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`The Lu JSSC Reference
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`Dependent Claims 2, 3, 5, 6, 7 and 9
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`Dependent Claim 3
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`1.
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`The Watanabe ‘254 Reference
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`Dependent Claim 5
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`Dependent Claim 7
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`1.
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`The Hardee ‘469 Reference
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`XII. Oath
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`Appendix A
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`ii
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`U.S. Patent 6,366,130
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`List of Figures
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`Figure A—Annotated FIG’s. 1 and 2 of the ‘130 Patent
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`Figure B—Annotated FIG. 2 of the ‘130 Patent
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`Figure C—Annotated FIG. 1 of the ‘241 Patent
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`Figure D—Portion of Sukegawa FIG. 1 with Dr. Baker’s Changes for
`Vdd/2 Precharging of Nodes N3 and N4
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`Figure E—Portion of Sukegawa FIG. 1 with Attempt at Vdd/2 Precharging
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`Figure F—Annotated Fig. 4 of the Lu JSSC paper
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`25
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`Figure G—Portion of Sukegawa FIG. 1 with Added Precharge Device per Lu
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`Figure H—Annotated Portion of FIG. 2 of ‘130 Patent and
`FIG. 7 of Watanabe ‘254
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`Figure I—Annotated Portion of FIG. 2 of ‘130 Patent Showing
`Sources and Drains Required by Claim 3
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`Figure J—Annotated Portion of FIG. 2 of ‘130 Patent With
`PMOS Input Pass Transistors Added
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`Figure K—Annotated Portion of FIG. 2 of ‘130 Patent
`With Only PMOS Input Pass Transistors of Watanabe ‘254
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`Figure L—Logic Low Voltage and Logic High Voltage
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`Figure M—FIG. 1 of Podlesny ‘130; Portion of FIG. 1 of Sukegawa ‘241;
`and FIG. 5 of Hardee ‘469
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`I. Executive Summary
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`Case IPR2015-01524
`U.S. Patent 6,366,130
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`1.
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`This Declaration is in support of patent owners in inter partes
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`review before the Patent Trial and Appeal Board of U.S. Patent 6,366,130 to
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`Podlesny et al.
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`2.
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`The Board has decided to institute review with respect to the
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`following grounds:
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`A. Whether independent claim 1 and dependent claims 2, 5, 6, and 9
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`are unpatentable under 35 U.S.C. § 103 as obvious over the
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`combination of U. S. Patent 5,828,241 to Sukegawa and Lu
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`JSSC;
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`B. Whether dependent claim 3 is unpatentable under 35 U.S.C. §
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`103 as obvious over the combination of Sukegawa, Lu, and U. S.
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`Patent 6,108,254 to Watanabe; and
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`C. Whether dependent claim 7 is unpatentable under 35 U.S.C. §
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`103 as obvious over the combination of Sukegawa, Lu, and U. S.
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`Patent 6,249,469 to Hardee;
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`3.
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`Evidence detailed in this Declaration demonstrates that
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`A. Regarding Issue A above:
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`1) The combination of Sukegawa and Lu fails to disclose or
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`suggest the differential data bus required by claim 1.
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`U.S. Patent 6,366,130
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`2) The combination of Sukegawa and Lu fails to disclose or
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`suggest precharging
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`the nodes
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`identified as
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`the
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`differential data bus to a voltage Vpr between Vdd and
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`ground, as required by claim 1.
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`3) Modifications to Sukegawa and Lu necessary to provide
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`precharging of the nodes identified as the differential
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`data bus to the required voltage would not have been
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`obvious to one of ordinary skill in the art at the time of
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`the invention of the ‘130 patent.
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`4) The combination of Sukegawa and Lu fails to disclose or
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`suggest the following elements required by claim 5:
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`“logic high voltage” and “logic low voltage.”
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`B. Regarding Issue B above:
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`1) The combination of Sukegawa, Lu and Watanabe fails to
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`disclose or suggest the following requirement stated in
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`claim 3: “…wherein the drains of the input pass
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`transistors are coupled to the drains of the cross-coupled
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`latch amplifier NMOS and PMOS transistors, each
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`source terminal of the input pass transistors is coupled to
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`an input…”.
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`U.S. Patent 6,366,130
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`C. Regarding Issue C above:
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`1) The combination of Sukegawa, Lu and Hardee fails to
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`disclose or suggest the following requirement stated in
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`claim 7: “…the active pull up and pull down bus drivers
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`are NMOS transistors.”
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`II. Introduction
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`4.
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`I, William R. Huber, D.Sc., P.E., a resident of West End, North
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`Carolina, declare as follows:
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`5.
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`I have been retained on behalf of Elbrus International Limited, to
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`provide declaratory evidence in inter partes review of U.S. Patent 6,366,130
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`(“‘130 patent”) to Podlesny et al.
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`6.
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`I am being compensated for my work related to this inter partes
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`review proceeding. My compensation is not dependent on and in no way affects
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`the substance of my statements in this Declaration.
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`7.
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`I have reviewed and am familiar with the specification and the
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`claims of the ‘130 patent. I will cite to the specification using the following format:
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`(Ex. 1001, ‘130 patent, 1:1-10). This example citation points to the ‘130 patent
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`specification at column 1, lines 1-10.
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`U.S. Patent 6,366,130
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`8.
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`Along with the petition for inter partes review of the ‘130 patent
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`(Paper 1; “Petition”), I have reviewed and am familiar with following references:
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` U.S. Patent 6,366,130 to Podlesny et al. (Ex. 1001; “‘130 patent” or
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`“Podlesny et al.”);
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` Prosecution File History for U.S. Patent 6,366,130 (Ex. 1003);
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` Declaration of Jacob Baker (Ex. 1002; “Baker Dec.”);
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` U.S. Patent 5,828,241 to Sukegawa (Ex. 1005; “Sukegawa ’241”);
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` Lu, N. C-C. and Hu, H. C.; “Half-VDD Bit-Line Sensing Scheme in
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`CMOS DRAM’s;” IEEE Journal of Solid-State Circuits; Vol. SC-19,
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`No. 4; August 1984; pp. 451-454 (Ex. 1008; “Lu JSSC”);
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` U.S. Patent 6,108,254 to Watanabe et al. (Ex. 1006; “Watanabe
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`‘254”);
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` U.S. Patent 6,249,469 to Hardee (Ex. 1007; “Hardee ‘469”); and
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` Patent Owner’s Preliminary Response (Paper 8).
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`9.
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`I have also reviewed and refer to the Board’s Decision to Institute
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`Inter Partes Review in this proceeding (Paper 9; “Decision”), and the transcript
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`from the deposition of Jacob Baker, Samsung’s declarant (Ex. 2003).
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`10.
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`I am familiar with the technology at issue and the state of the art at
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`the time the application leading to the ‘130 patent was filed.
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`11.
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`I have been asked to provide my technical review, analysis,
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`insights, and opinions regarding the above-noted references, as well as various
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`semiconductor industry practices.
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`III. Qualifications
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`12. My academic and professional pursuits are closely related to the
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`subject matter of the ‘130 patent.
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`13.
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`I have more than 50 years of experience in the semiconductor field.
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`I have over 30 years of experience in the hands-on product development, research,
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`and management of complex semiconductor integrated circuit products. This
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`experience includes the design of memory devices. I also have over 20 years of
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`technical consulting experience in the field of semiconductor memory devices.
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`14.
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`I earned a Bachelor of Science degree in Electrical Engineering in
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`1962 from the University of Pittsburgh in Pittsburgh, Pennsylvania. One year later,
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`I earned a Master of Science degree in Electrical Engineering from The Ohio State
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`University in Columbus Ohio. In 1969, I earned a Doctor of Science degree in
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`Electrical Engineering from the University of Pittsburgh.
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`15.
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`I am currently the President of Electronics Consulting Engineers
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`(ECE). I founded ECE in 1993. ECE has locations in Florida and West End, North
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`Carolina and provides patent-related services such as licensing evaluation, validity
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`and infringement assessment, and litigation support. I have provided litigation
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`support to various integrated circuit companies in a wide array of semiconductor
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`technologies such as DRAM, SDRAM, and Flash memory. In providing this
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`support, I rely on my technical experiences in the field of semiconductor memory:
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`(1) over 30 years of hands-on and management experience in the semiconductor
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`field, including the design of semiconductor memory devices; (2) my involvement
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`with semiconductor standards committees, including the Joint Electron Device
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`Engineering Council (JEDEC) Committee on semiconductor memory devices; and,
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`(3) authoring continuing education courses on semiconductor memory
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`technologies.
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`16. My hands-on and management experience in the semiconductor
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`field started at Bell Telephone Laboratories in 1962, where I was a Member of
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`Technical Staff and Supervisor. While at Bell, along with my group, I developed
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`and applied the concept of redundancy to semiconductor memory chips. This
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`development was quite significant in the semiconductor memory field since it
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`reduced the impact of manufacturing defects on production yield and overall
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`product cost. I co-authored and presented a paper on this memory redundancy
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`concept. The paper won the Best Paper Award at the International Solid-State
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`Circuits Conference in 1979. I also authored/co-authored three other papers
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`focusing on semiconductor memory devices during my time at Bell. I left Bell in
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`1982.
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`17. From 1982 to 1989, I was Manager of Integrated Circuit
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`Development and Manager of Reliability and Quality Assurance at General
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`Electric Company Microelectronics Center in Research Triangle Park, North
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`Carolina. I planned and directed new product and technology development and
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`characterization. One of the products we developed during this time was a 64K
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`radiation-hardened SRAM.
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`18. From 1989 to 1994, I worked at Harris Corporation in Melbourne,
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`Florida as Senior Scientist and Director of Engineering—Military and Aerospace
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`Division. I planned and directed new product development and characterization.
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`This effort included the development of radiation-hardened field-programmable
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`gate array devices and also involved the design of a 256K radiation-hardened
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`SRAM.
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`19.
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`In addition to my engineering experiences described above, I
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`played an active role in various Joint Electron Device Engineering Council
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`(JEDEC) committees. I was an active member of the JEDEC JC-42 Committee on
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`Semiconductor Memory Devices from its early days in 1972 until 1984. As a
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`member, I met regularly with specialists from companies that designed or bought
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`memories to develop physical, electrical and performance standards for a wide
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`variety of semiconductor memories. For the last two years of my tenure at JEDEC
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`JC-42, I chaired the Task Group on IC Operating Voltage Standards. We
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`developed standards for low-voltage (3.3V) operation and interface requirements
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`for memory and logic devices.
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`20.
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`In addition to my semiconductor industry experience, I am an
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`inventor on three U.S. patents that relate to semiconductor devices. Two of the
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`patents directly relate to semiconductor memory devices—in particular, DRAM
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`devices. I am also a Life Senior Member of the Institute of Electrical and
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`Electronics Engineers (IEEE) and have been a member for over 50 years. I am
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`currently registered as a Professional Engineer in Florida and North Carolina.
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`21. Additional information on my education, technical experience and
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`professional associations can be found in my curriculum vitae (attached as
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`Appendix A).
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`IV. Obviousness Law
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`22.
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`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a person of ordinary skill in the field at the time the
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`application was filed. This means that even if all of the requirements of the claim
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`cannot be found in a single prior art reference that would anticipate the claim, the
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`claim can still be invalid.
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`23.
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`To obtain a patent, the claimed invention must have, as of the
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`priority date, been nonobvious in view of the prior art in the field. I understand that
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`an invention is obvious when the differences between the subject matter sought to
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`be patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art.
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`24.
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`I understand that to prove that prior art or a combination of prior
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`art renders a patent obvious, it is necessary to: (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to
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`create the inventions claimed in the asserted claim.
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`25.
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`I understand that certain objective indicia can be important
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`evidence regarding whether a patent is obvious or nonobvious. Such indicia
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`include: commercial success of products covered by the patent claims; a long-felt
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`need for the invention; failed attempts by others to make the invention; copying of
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`the invention by others in the field; unexpected results achieved by the invention as
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`compared to the closest prior art; praise of the invention by the infringer or others
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`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art.
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`V.
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`Level of Ordinary Skill in the Art
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`26.
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`As part of this inquiry, I have been asked to consider the level of
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`ordinary skill in the field that someone would have had at the time the claimed
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`invention was made. In deciding the level of ordinary skill, I considered the
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`following:
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` the levels of education and experience of persons working in the field;
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` the types of problems encountered in the field; and
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` the sophistication of the technology.
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`27.
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`Based on the technologies disclosed in the ‘130 patent, a person
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`of ordinary skill in the art would have a Bachelor of Science degree in Electrical
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`Engineering or an equivalent field, as well as at least 2 years of experience
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`designing and analyzing data transfer or equivalent circuits.
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`VI. The 6,366,130 Patent
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`28.
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`Let us now examine the technical challenges addressed by the
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`‘130 patent. This will help define certain terms in the ‘130 patent claims in view of
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`its specification as well as what a person of ordinary skill in the art would have
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`understood during the 1999-2000 timeframe (also referred to herein as “the
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`relevant timeframe”).
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`29.
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`The ‘130 patent describes circuitry for efficiently transferring
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`data signals over long distances at high speeds while consuming low power. In
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`describing the advantages of the invention, the ‘130 patent specification states:
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` (Ex. 1001,’130 patent, 1:42-55):
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`30.
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`Several factors of the claimed invention of the ‘130 patent
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`contribute to the higher data transfer speeds, lower power, and reduced sensitivity
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`to component and environmental variations. As identified in the specification,
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`these factors include:
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`(Ex. 1001,’130 patent, 3:12-16):
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`(Ex. 1001,’130 patent, 3:17-23):
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`(Ex. 1001,’130 patent, 3:23-30):
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`(Ex. 1001,’130 patent, 3:40-45):
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`(Ex. 1001,’130 patent, 3:46-55):
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`(Ex. 1001,’130 patent, 3:56-63):
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`VII. Disputed Claims of the ‘130 Patent
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`31.
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`The following claims of the ‘130 patent are disputed before the
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`Patent Trial and Appeal Board:
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`1. A data transfer arrangement comprising: two bus drivers; a voltage
`precharge source; a differential bus coupled to the bus drivers and to the
`voltage precharge source; aid a latching sense amplifier coupled to the
`differential bus; wherein the latching sense amplifier comprises: a first
`stage including a cross-coupled latch coupled to a differential data bus;
`and an output stage coupled to an output of said first stage; wherein the
`output of the first stage is coupled to an input of the output stage; wherein
`the differential bus and the differential data bus are precharge to a voltage
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`Vpr between Vdd and ground, where Vpr=K*Vdd, and K is a
`precharging voltage factor.
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`2. The data transfer arrangement in accordance with claim 1 wherein the
`bus drivers comprise active pull up and active pull-down bus drivers.
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`3. The data transfer arrangement in accordance with claim 1, wherein the
`first stage of the latching sense amplifier comprises: a plurality of input
`pass transistors each having a gate, a source terminal, and a drain; and a
`plurality of NMOS and PMOS transistors each having a gate, a source
`terminal, and a drain; wherein the drains of the input pass transistors are
`coupled to the drains of the cross-coupled latch amplifier NMOS and
`PMOS transistors, each source terminal of the input pass transistors is
`coupled to an input, the sources of the cross-coupled latch amplifier
`NMOS transistors are coupled to the drain of the NMOS transistor
`coupled to a clock signal input, and the sources of the PMOS transistors
`are coupled to the drain of the PMOS transistor having a gate coupled to
` an inverted clock signal input.
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`5. The data transfer arrangement in accordance with claim 1, wherein the
`voltage precharge source is configured to precharge the differential bus to
`a predetermined voltage that is less than a logic high voltage and greater
`than a logic low voltage.
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`6. The data transfer arrangement in accordance with claim 1 further
`comprising a precharge circuit coupled between the precharge source and
`the differential bus.
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`7. The data transfer arrangement in accordance with claim 2 wherein the
`active pull up and pull down bus drivers are NMOS transistors.
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`9. The data transfer arrangement of claim 1 wherein the output stage
`includes cross-coupled feedback.
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`VIII. Claim Construction
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`32.
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`“During patent examination, the pending claims must be ‘given
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`their broadest reasonable interpretation consistent with the specification’.”
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`M.P.E.P. § 2111 referring to Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir.
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`2005). The statement has two parts: 1) broadest reasonable interpretation, and 2)
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`consistent with the specification. The M.P.E.P. also requires the use of the ordinary
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`meaning of a word to a person of ordinary skill in the art unless it is otherwise
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`defined by the specification. See M.P.E.P. § 2111.01(III). Strange or unusual
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`meanings are not allowed unless specifically elucidated in the specification. In an
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`inter partes review, the Board applies the same standard. Office Practice Trial
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`Practice Guide, 77 Fed. Reg. 48,756 48, 764 (Aug. 14, 2012).
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`33.
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`The Petitioner proposes that two claim terms be construed by the
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`Board: 1) “latching sense amplifier”, and 2) “stage.” As discussed in Patent
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`Owner’s Preliminary Response (POPR), both of these terms were in common use
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`in the relevant time period, and would have been clearly understood by one of
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`ordinary skill at that time.
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`34.
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`Consider first the term, “latching sense amplifier.” In the book,
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`“DRAM Circuit Design—A Tutorial,”1 co-authored by Petitioner’s expert, R.
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`Jacob Baker and first published in 2001, many sense amplifier designs and their
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`1 Keeth, B. and Baker, R.J.; IEEE Press, 2001
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`operation are discussed in detail. But nowhere is there a definition of “sense
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`amplifier.” The closest such statement seeks to define the function of sensing and
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`appears on p. 22: “Sensing is essentially the amplification of the digitline signal or
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`the differential voltage between the digitlines.” A similar lack of formal definition
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`of “latching sense amplifier” or even “sense amplifier” occurs in what has been
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`called the “bible” of semiconductor memories, “Semiconductor Memories—A
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`Handbook of Design, Manufacture, and Application.”2 Despite over 50 page
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`cites to “sense amplifier” in the index, there is no definition of the term. It is one
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`of the terms understood by those of skill in the art, but lacking a formal definition.
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`35.
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`Now consider the term “stage.” Stage is another term which
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`everyone in the field understands but which almost defies formal definition.
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`Clearly Petitioner’s proposed construction, “a portion of a circuit” is excessively
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`broad as it could include anything from a wire to thousands of components. But
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`establishing a concise definition of stage, even within the restrained context of the
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`‘130 patent, is neither productive nor necessary.
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`36.
`
`On p. 5 of their DECISION issued January 19, 2016, the Patent
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`Trial and Appeal Board states, “We determine that no express claim construction is
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`required for purposes of this Decision.”
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`2 Prince, B.; John Wiley & Sons; 1983 (First Edition) and 1991 (Second Edition)
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`37.
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`The following table summarizes the positions of the parties on
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`construing the two terms.
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`Claim Term
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`Petitioner’s
`Proposed
`Construction
`
`Patent Owner
`Position
`
`latching sense
`amplifier
`
`stage
`
`“a circuit,
`including a latch,
`that detects and
`amplifies signals”
`“a portion of a
`circuit”
`
`Ordinary meaning
`
`Ordinary meaning
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`
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`IX. Alleged Prior Art
`
`PTAB
`Decision
`
`No express
`claim
`construction
`required
`
`Patent Owner
`Proposed
`Construction if
`Required
`“circuit that
`amplifies low-
`level signals and
`stores the result”
`a portion of a
`circuit that has an
`input, an output
`and some
`functionality
`
`38.
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`The following references were cited by the Petitioner as prior art
`
`relevant to the ‘130 patent.
`
`39.
`
`Sukegawa, S.; U. S. Patent 5,828,241; “Signal Transmission
`
`Circuit Providing Amplified Output from Positive Feedback of Intermediate
`
`Amplifier Circuit;” Filed June 5, 1996; Continuation to November 19, 1992
`
`Abstract:
`A signal transmission circuit which enables the distance of signal
`transmission as measured by the length of the wiring electrically
`connecting a driver circuit and a receiver circuit of the signal
`transmission circuit to be increased, while the signal delay and
`power consumption are reduced. The signal transmission circuit
`includes the driver circuit, the receiver circuit, an equalizer circuit
`that flattens the output of the driver circuit, and an intermediate
`amplifier circuit. The intermediate amplifier circuit is connected to
`input/output shared terminals in the wiring that connects the driver
`circuit and the receiver circuit. With the aid of the positive
`feedback of the intermediate amplifier circuit, a differential signal
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`output from the driver circuit is amplified and then transmitted to
`the receiver circuit.
`
`40.
`
`Lu, N.C.C. et al.; “Half VDD Bit-Line Sensing Scheme in
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`CMOS DRAM’s;” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4,
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`August 1984; pp. 451-454
`
`Abstract:
`A sensing scheme in which the bit line is precharged to half VDD is
`introduced for CMOS DRAM’s. The study shows that the half-
`VDD bit-line sensing scheme has several unique advantages,
`especially for high-performance high-density CMOS DRAM’s,
`when compared to the full-VDD bit-line sensing scheme used for
`NMOS memory arrays or the grounded bit-line sensing scheme for
`PMOS arrays in CMOS DRAM’s.
`
`41. Watanabe, Y. et al.; U. S. Patent 6,108,254; “Dynamic Random
`
`Access Memory Having Continuous Data Line Equalization Except at
`
`Address Transition During Data Reading;” Filed November 12, 1993;
`
`Continuation to June 4, 1991
`
`Abstract:
`A Dynamic Random Access Memory (DRAM) in which a data
`input/output buffer is connected between first data lines and
`second data lines. An equalizing circuit and a data latch circuit are
`connected to the second data lines. The equalizing circuit
`maintains the second data lines in reset condition, during normal
`operation. It temporarily releases the second data lines from the
`reset condition, in response to an output from an address-transition
`detecting circuit, thereby to transfer the data from the data
`input/output buffer. The data latch circuit latches the data
`transferred to the second data lines, in response to the output from
`the address-transition detecting circuit.
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`42.
`
`Hardee, K; U. S. Patent 6,249,469; “Sense Amplifier with Local
`
`Sense Drivers and Local Read Amplifiers;” Filed July 1, 1996; Continuation to
`
`November 12, 1992
`
`Abstract:
`A sense amplifier for a very high density integrated circuit memory
`using CMOS technology is described. Each sense amplifier
`includes first and second local sense amplifier drive transistors,
`one connecting the P channel transistors to VCC; the other
`connecting the N channel transistors to VSS. A read amplifier
`circuit is provided within each sense amplifier and is operated by
`read control signals. Internal nodes of the latch of the sense
`amplifier are coupled by pass transistors that are responsive to
`column write control signals. Local data write driver transistors are
`also provided to selectively couple the pass transistors to VCC-Vt
`or VSS in response to further data write control signals. A
`relatively wider power line is coupled to the drive transistors to
`provide VCC thereto, and a narrower line is used to control those
`first sense amplifier drive transistors. Corresponding wide and
`narrow lines are used for the second local sense amplifier drive
`transistors which couple the N channel transistors to ground. Each
`sense amplifier may be shared between first and second pairs of bit
`lines through the use of isolation transistors and a corresponding
`isolation signal.
`
`Patent Trial and Appeal Board Decision to Institute
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`X.
`
`43.
`
` On January 19, 2016 the Patent Trial and Appeal Board ordered
`
`as follows:
`
`ORDER
`For the reasons given, it is hereby
`inter partes
`ORDERED that pursuant to 35 U.S.C. § 314(a), an
`review is hereby instituted as to claims 1–3, 5–7, and 9 of the ’130 patent
`with respect to the following grounds:
`1. Whether claims 1, 2, 5, 6, and 9 are unpatentable under 35 U.S.C.
`§ 103 as obvious over the combination of Sukegawa and Lu;
`2. Whether claim 3 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Watanabe; and
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`3. Whether claim 7 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Hardee;
`FURTHER ORDERED that no ground other than those specifically
`listed above is authorized for the inter partes review as to the ’130 patent;
`and
`
`to 35 U.S.C. § 314(c) and
`that pursuant
`FURTHER ORDERED
`37 C.F.R. § 42.4, notice is given of the institution of the trial.
`
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`XI. Discussion of ‘130 Claims and Alleged Prior Art
`
`44.
`
`Throughout my declaration, I will annotate various figures from
`
`the ‘130 patent, Sukegawa ‘241, Lu JSSC, Watanabe ‘254 and Hardee ‘469. These
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`annotated figures are drafted based on the ‘130 patent claims and visually highlight
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`the distinctions between the disputed claims and the applied references.
`
`45.
`
`For example, Figures A and B below show the memory system
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`disclosed in FIG’s. 1 and 2 of the ‘130 patent, with color-coding to identify some
`
`of the claim elements of Claim 1.
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` Figure A—Annotated FIG’s. 1 and 2 of the ‘130 Patent
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`A.
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`Independent Claim 1
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`Claim 1 reads as follows (Ex. 1001,’130 patent, 4:2-17):
`
`46.
`
`1. A data transfer arrangement comprising: two bus drivers;
`a voltage precharge source; a differential bus coupled to the
`bus drivers and to the voltage precharge source; aid a
`latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises: a first stage
`including a cross-coupled latch coupled to a differential data
`bus; and an output stage coupled to an output of said first
`stage; wherein the output of the first stage is coupled to an
`input of the output stage; wherein the differential bus and
`the differential data bus are precharge to a voltage Vpr
`between Vdd and ground, where Vpr=K*Vdd, and K is a
`precharging voltage factor.
`
`47.
`
`Refer to Claim 1 and Figure A on the previous page.
`
`Items 11 and 12 are the “two bus drivers,” highlighted in
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`and
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`discussed at ‘130 patent, 2:9-38.
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`Items 24, 25 and 26, along with voltage source Vpr and control signal PR
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`constitute “a voltage precharge source,” highlighted in
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`and
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`discussed at ‘130 patent, 2:14-22.
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`Items 14 and 15 are “a differential bus coupled to the bus drivers and to the voltage
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`precharge source,” highlighted
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`in and discussed at ‘130 patent,
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`2:23-38.
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`Item 16 is “a latching sense amplifier coupled to the differential bus,” highlighted
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`in and discussed at ‘130 patent, 2:39-3:11.
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`Figure B—Annotated FIG. 2 of the ‘130 Patent
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`Now refer to Claim 1 and Figure B above.
`
`The circuitry highlighted in
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`constitutes “a first stage including a
`
`cross-coupled latch coupled to a differential data bus.” and is discussed at ‘130
`
`patent, 2:39-3:3. The “differential data bus” is highlighted in
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`.
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`The circuitry highlighted in
`
`constitutes “an output stage coupled to
`
`an output of said first stage; wherein the output of the first stage is coupled to an
`
`input of the output stage,” and is discussed at ‘130 patent, 3:4-11.
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`1. What is K?
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`48.
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`Claim 1 identifies K as “a precharging voltage factor,” and
`
`requires that “the differential bus and the differential data bus are precharge(d) to a
`
`voltage Vpr between Vdd and ground, where Vpr = K*Vdd…” At ‘130 patent,
`
`3:25, the preferred embodiment is defined as K = ⅓. In stating that Vpr must be
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`between Vdd and ground, Claim 1 requires 0 < K < 1. Let us see if we can further
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`limit the value of K based upon the legal principle that claim construction must not
`
`exclude the preferred embodiment.
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`49. When the PR (precharge) signal of FIG. 1 is high, it turns on
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`NMOS transistors 24, 25 and 26. One of ordinary skill would expect the
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`maximum level of PR to be Vdd. Therefore the precharge voltage applied to the
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`differential bus lines LT and LC will be Vpr; but because of the characteristics of
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`NMOS transistors can be no greater that Vdd – VTN5 (for line LT) or
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`Vdd – VTN7 (for line LC) (where VTNX is the threshold voltage of NMOS
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`transistors N5 and N7 respectively). Therefore, to meet the claim requirement that
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`“the differential bus … (is) precharge(d) to a voltage Vpr…,” it is necessary that
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`Vpr be no greater than Vdd – VTN. Simple algebra then yields a reduced
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`accept