EXHIBIT 2002
`
`

`
`BEAM CIRCUI
`
`A Taforial
`
`Brent Keeth
`
`§>§.?.;:z*mz Tecknofagy, Ina’.
`$23555, fdafzo
`
`R. Jacob Baker
`Efiéié Stare Uniwsrsizy
`M£‘a:‘:*<;*r; Tesfmafogy, Inc.
`Mafia
`
`Scsiid-State Circuits Society, Sponsor
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`©2001 by the Institute of Electrical and Electronics Engineers, Inc.
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`Al! rights reserved. No pwi qfzfhis book may be reproduced 5:: arzyfonn,
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`Printed in the United States of Amexica.
`
`10
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`9
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`-
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`5
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`ISBN €}~7S03-6014»-1
`IEE *
`rder ,1 0. PC5863
`
`Library of Congress Catalogingdn-Publicati-on Data
`
`Keeth, Brent, 196-[)w—
`DRAM circuit design : a tutariai I Brent Keeth, R. Jacob Baker.
`p. cm.
`"IEEIZ Solid-State Circuits Socieiy, Spenser.”
`Includes bibliographical references and index.
`ISBN O-7803-fi0I4~1
`
`1. Semiconductar sturage cievices Design and wnstructéon. 1. Baker, R. Jacob, 1964——
`11. Tifie
`
`TK7895.M4 K425 2000
`621.39’ 732--dc2I
`
`O0-OSQSGE
`
`

`
`Chap 1 An Intmducticn to DRAM
`
`1.2.1
`
`ccess and Sense Operations
`
`Next, we examine the access and sense operations. We begin by assuntv
`ing chat the cells connected to D1, in Figure 1.24, have logic one levels
`(+V,g,.;i2) stored en them and that ihe cells ccnnccted to DO have logic zero
`
`levels (—VgCi2) stored on them. Next, we form a digitline pair by considcr~
`ing two digitlines fmrn adjacent arrays. The digitline pairs, labeled D0/130*
`and DE./D1*, are initially equilibrated in lfco/2 V. All wordlines are initially
`at O V, ensuring that the rnhit transistors are OFF. Prior to a wcrdline firing,
`the digérlines are electrically disconnected from the £79512 bias voltage and
`allowed to float. They remain at the vac/2 PRECHARGL" voltage due :0
`their capacitance.
`‘
`To read mbitl, wcrdline WLO changes to a voltage that is at least one
`transistor Vm above lag. This voltage level is referred to as Vggp or V9,». To
`ensure that a full logic one value can be written back min the inbit capacitor,
`lfccp must remain greater than one Vm above V55. The mbit capacitor
`begins to discharge onto the digitline at two different voltage levels depend»
`ing on the logic level stored in the cell. For a logic (me, the capacitor begins
`to discharge when the wordline voltage exceeds the digitlinc PRECHARGE
`voltage by V”. For a logic zero, the capacitor begins to discharge when the .
`wordlinc voltage exceeds Vm. Because of the finite rise time of the word»
`line voltage, this difference in tnrrron voltage translates into a significant
`delay wher reading ones, as seen in Figure 1.25.
`
`WL6 WL7
`
`WL2 WL3
`_l
`
`A fireWorclline drivers
`
`Sense amps
`D1
`I31“
`
`[30
`
`V
`
`Figure 1.34 Simple array schematic (an cpen DRAM array).
`
`

`
`Sec. 1.2 DRAM Basics
`
`Wcsrdline vollage
`
`Reading a
`log is “cne”
`
`_ Worciline voltage
`
`Reading a
`logic “zero”
`
`Digitléne
`precfiarge
`valtage
`
`Evigitilne
`precharge
`voltage
`
`‘E
`
`af{0:l D04’
`
`Wordline vi:-ltage
`
`Empgsigeffieag 1159,;
`of logic "one
`'
`an<:l“zem"
`
`Dlgitline
`precharge + Vm
`vcltage
`
`‘ii?’
`
`Figure 1,25 Cell acccss waveforms.
`
`Accessing a DRAM cell results in <:harge—sharing between the mbit
`capacitor and the digitiine capacitance. '§his chargc—sharing causes the digit-
`line voltage either to increase for a stored logic cine or tea decrease for 3 stored
`Logic zero. Ideally, cmly the cligitline connected to the accessed mbit will
`change. In reality, the other digitline voltage also changes slightly, due to par-
`asitic coupling between digiilines and between the firing wordline and the
`other cligitline. (This is especially true for the folded bitline architecmre dis-
`cussed later.) Nevertheless, a differential voltage develops between the: two
`fiigitlines. The magnitude of this voltage difference, or signal, is a function of
`the mbizf capacitance ( C,,,£,,-,.,1, digizlinc capacitance {Cd;g,,), and voltage stored
`on the cell prior to access {Vm«,). See Figure 1.26. Accordingly,
`
`V
`
`signal :
`
`Cmbzz
`V
`1:1‘ —é‘—" -
`Cdigiz‘ + Cmbir
`Ci’
`
`A V5,-g,,6,1 of 235mV is yielded from a design in which FM, = 1.65,
`Cmbjg =
`and Cdfgfy =
`
`

`
`28
`
`Chap. 1 An Introduction to DRAM
`
`After the cell has been accessed, sensing occurs. Sensing is essentially
`the amplification of the digitiine signal or the differential voltage between
`the digitlines. Sensing is necessary to properly read the cell data and refresh
`the orbit cells. (The reason for forming a digitline pair now becomes appar—
`ent.) Figure 1.2’? presents a schematic diagram for a simplified sense ampli~
`tier circuit: a erosscoupled NMOS pair and 3 Cross—coupled PMOS pair.
`The sense amplifiers also appear like a hair of cross—eoupled inverters in
`which ACT and NLA}'“* provide power and ground. The NMOS pair or
`Nsense-amp has a common node labeled NLAT* (for Nserzse-amp latch).
`Similarly, the Psenseemp has a common node labeled ACT (for Active
`pull-up). Initially, NLAT* is biased to V¢~,gf2, and ACT is biased to lrfg-3 or
`signal ground. Because the digitline pair D1 and Dlf’-‘ are both initially at
`VCC/2, the Nsensearnp transistors are both OFF. Similarly, both Psense-
`amp transistors are OFF. Again, when the melt is accessed, a signal devel-
`ops across the digitline pair. While one digitline contains charge from the
`cell access, the other digitline does not but serves as a reference for the
`Sensing operation. The sense amplifiers are generally fired sequentially: the
`Nsense—amp first, then the Psenseemp. Although designs vary at this point,
`the higher drive of NMQS transistors and better V;r;, matching offer better
`sensingwcharaoteristics by Nsense-amps and thus lower error probability
`compared to Psense-amps.
`h
`igure 3.28. The
`Waveforms for the Sensing operation are shown in
`Nsense-amp is fired by bringing NLAT* (N senseemp latch)
`toward
`ground. As the Voltage difference between NLAT““ and the digitlines (D1
`and D1* in Figure 1.27) approaches V73, the NMOS transistor whose gate
`is connected to the higher voltage digitline begins to Conduct. This conduc-
`tion occurs first in the snbthreshold and then in the saturation region as the
`gate~—to—source voltage exceeds Vgm and causes the low-voltage digitline to
`discharge toward the NLAT’«“ voltage. Ultimately, NLAT* will reach ground
`and the digitline will he hronght to ground potential. Note that the other
`NMOS transistor will not conduct: its gate voltage is derived from the low
`
`Initially. Vcz:f2
`
`MOSFET access
`
`Corgi:
`
`Capacitance
`
`-oi cligitline
`
`4-« Initially, Veer:
`
`Cmme
`
`[1vmre
`
`Figure 1.26 DRAM chargezeharing.
`
`

`
`Sec, 1.2 DRAM Basics
`
`Pse-nse—amp Nsonse~amp
`~%Q-—---------*"*P* ~4«-————-jaw
`
`Figurc 1.27 Sense amplifier schematic.
`
`voltage digitline, which is being éischarged toward ground, in reality, pare»
`sitic coupling between ciigitliues and iimited subthrcshold conéucti-on by {he
`second transistor result in voitagc. reduction on tho high digitlinc.
`Sometime after the Nsecsc—amp fires, ACT will be brought toward Va;
`to activate the Psensc—amp, which operates in a complementary foshion to
`the Nsensc—amp. With the iow-voltage digitlinc approaching ground, there is
`a strong signal to drive tho appropriate RMOS transistor into conduction“
`This conduction, again moving from subthrcshold to saturation, charges the
`lughwroltage digitlinc toward ACT, ultimately reaching VCC. Because the
`mbit transistor remains ON, the mbit capacitor is Icfrcshcd duri ig the Sons-
`ing ifipcration. The voltage, and hence charge, which the mbit capacitor held
`prior to accessing, is rcstorcé to a full level: Va; for a logic one and ground
`for a logic zero. It shouid be apparent now why the minimum wordlinc volt
`age 15 a Vm above l/CC. If Vcgp were anything less, a full l«”¢~.;- icvci con (1 not
`be \3’v‘Iitt6D back into the mbit capacitor. The mbit transisior source voltage
`Vmm, cannot be greater than VgC,,€— VT}; because this would tum OP the
`transistor;
`
`Figure 1.28 Sensing operation waveforms.
`
`

`
`CERTIFICATE OF SERVICE
`
`IPR 2015-01524
`
`The undersigned hereby certifies that the foregoing Exhibit was
`
`served on March 16, 2016 by filing this document through the Patent
`
`Review Processing System as well as delivering a copy via electronic mail
`
`upon the following attorneys of record for the Petitioner:
`
`Steven L. Park
`
`stevenpark@paulhastings.com
`
`Naveen Modi
`
`naveenmodi@paulhastings.com
`
`Dated: March 16, 2016
`
`Respectfully submitted
`
`/clifford kraft/
`
`Clifford H. Kraft
`
`Reg. No. 35,229
`
`/joseph hosteny/
`Joseph N. Hosteny
`Reg. No. 28,020