Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 9
`
` Entered: January 19, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED,
`Patent Owner.
`____________
`
`Case IPR2015-01524
`Patent 6,366,130
`____________
`
`
`
`
`
`Before JUSTIN T. ARBES, JEFFREY W. ABRAHAM, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`571-272-7822
`
`
`Paper No. 9
`
` Entered: January 19, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED,
`Patent Owner.
`____________
`
`Case IPR2015-01524
`Patent 6,366,130
`____________
`
`
`
`
`
`Before JUSTIN T. ARBES, JEFFREY W. ABRAHAM, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`Case IPR2015-01524
`Patent 6,366,130
`
`
`I.
`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner”) filed a Petition seeking
`inter partes review of claims 1–3, 5–7, and 9 of U.S. Patent No. 6,366,130
`B1 (Ex. 1001, “the ’130 patent”), as amended by Inter Partes
`Reexamination Certificate No. US 6,366,130 C1 (“Reexam. Cert.”). Paper 1
`(“Pet.”). Elbrus International Limited (“Patent Owner”) filed a Preliminary
`Response to the Petition. Paper 8 (“Prelim. Resp.”). Applying the standard
`set forth in 35 U.S.C. § 314(a), which requires demonstration of a reasonable
`likelihood that Petitioner would prevail with respect to at least one
`challenged claim, we institute an inter partes review of claims 1–3, 5–7, and
`9 as discussed below.
`Our determinations at this stage of the proceeding are based on the
`record developed thus far, prior to the Patent Owner’s Response. This is not
`a final decision as to the patentability of any challenged claim. Any final
`decision will be based on the full record developed during trial.
`II.
`BACKGROUND
`A. Related Proceedings
`The parties identify Cascades Computer Innovation, LLC. v. Samsung
`Electronics Co., Ltd., Case No. 1-14-cv-05691 (N.D. Ill.), currently pending,
`as well as pending inter partes review petition in Case IPR2015-01523, also
`pertaining to the ’130 patent. Pet. 1–2; Paper 4, 3.
`B. The ’130 Patent
`The ’130 patent, titled “High Speed Low Power Data Transfer
`Scheme,” issued on April 2, 2002, with a reexamination certificate issuing
`on August 4, 2014. The ’130 patent is directed to a “high speed and low
`power [complementary metal-oxide semiconductor (CMOS)] data transfer
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`arrangement that includes two active pull up/pull down bus drivers, a
`differential bus that precharges to a specific voltage level and a latched
`differential sense amplifier that serves as a bus receiver.” Ex. 1001, 1:24–
`28, Fig. 1. In one embodiment, the latching sense amplifier is arranged as a
`“cross coupled latched amplifier.” Id. at 1:36–38, Fig. 2. The ’130 patent
`explains that its data transfer scheme can operate at increased speeds due to,
`inter alia, precharging the buses to a specific level (Vpr) between ground and
`Vdd. Id. at 2:23–38, 3:17–55.
`C. Illustrative Claim
`Petitioner challenges claims 1–3, 5–7, and 9. Claim 1 is the only
`independent claim challenged, and is reproduced below:
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the voltage
`precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an input of the
`output stage;
`wherein the differential bus and the differential data bus are
`precharge to a voltage Vpr between Vdd and ground, where
`Vpr=K*Vdd, and K is a precharging voltage factor.
`
`Id. at 4:2–17.
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`D. References
`Petitioner relies on the following references:
`Sukegawa, U.S. Patent No. 5,828,241, issued Oct. 27, 1998
`(“Sukegawa,” Ex. 1005).
`Watanabe et al., U.S. Patent No. 6,108,254, filed Nov. 12,
`1993, issued Aug. 22, 2000 (“Watanabe,” Ex. 1006).
`Hardee, U.S. Patent No. 6,249,469 B1, filed July 1, 1996,
`issued June 19, 2001 (“Hardee,” Ex. 1007).
`Nicky Chau-Chun Lu & Hu H. Chao, Half-VDD Bit-Line
`Sensing Scheme in CMOS DRAM’s, SC-19:4 IEEE JOURNAL
`OF SOLID STATE CIRCUITS 451–454 (1984) (“Lu,” Ex. 1008).
`
`
`E. The Asserted Grounds
`Petitioner asserts the following grounds of unpatentability:
`Statutory Basis Claim(s)
`Challenged
`§103
`1, 2, 5, 6, and 9
`
`References
`
`Sukegawa and Lu
`Sukegawa, Lu, and
`Watanabe
`Sukegawa, Lu, and
`Hardee
`
`
`
`§103
`
`§103
`
`3
`
`7
`
`III. ANALYSIS
`A. Claim Construction
`Petitioner offers constructions for two terms, “latching sense
`amplifier” and “stage.” Pet. 9–11. Petitioner contends that “latching sense
`amplifier” should be construed to mean “a circuit, including a latch, that
`detects and amplifies signals.” Id. at 9. Petitioner contends that “stage”
`should be construed to mean “portion of a circuit.” Id. at 10.
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`Patent Owner argues that these terms are commonly used and well-
`known in the art, and should be given their plain and ordinary meaning.
`Prelim. Resp. 4–6.
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b); In
`re Cuozzo Speed Techs., LLC, 793 F.3d 1268, 1275–79 (Fed. Cir. 2015).
`We determine that no express claim construction is required for purposes of
`this Decision.
`
`B. References
`1. Sukegawa
`Sukegawa discloses a “signal transmission circuit which enables the
`distance of signal transmission . . . to be increased, while the signal delay
`and power consumption are reduced.” Ex. 1005, Abstract. Sukegawa
`teaches that “the signal is amplified and transmitted by means of the positive
`feedback of an intermediate amplifier circuit having input/output shared
`terminals.” Id. at 1:12–15. Sukegawa provides circuit diagrams illustrating,
`and corresponding descriptions in the specification describing, the specific
`configuration of the various components of its transmission circuit. See id.
`at 6:35–9:50, Figs. 1–7.
`
`2. Watanabe
`Watanabe discloses a “[dynamic random access memory (DRAM)]
`having means which can transfer data at a sufficiently high speed.” Ex.
`1006, 1:64–65. Watanabe’s data transfer circuit contains differential
`amplifier circuit 10, equalizing circuit 11, data latch circuit 12, pairs of first
`data lines 13 and second data lines 14, and pair of data output lines 15. Id. at
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`3:41–44, Fig. 1. In one embodiment, data latch circuit 12 comprises three n-
`channel MOS transistors and five p-channel MOS transistors, arranged as
`shown in Figure 7 of Watanabe. Id. at 4:13–19, Fig. 7. Watanabe explains
`that its transfer circuit is an improvement over conventional data transfer
`control systems because data transfer can occur without having to take the
`time to equalize its data lines. Id. at 2:52–56.
`3. Hardee
`Hardee discloses a “sense amplifier for a very high density integrated
`circuit memory using CMOS technology.” Ex. 1007, Abstract. Hardee
`further discloses a preferred sense amplifier containing, inter alia, “N
`channel devices having their source-drain paths coupled in series.” Id. at
`6:28–46 (referring to transistors 128, 130, 132, 134), Fig. 5. Hardee states
`that these transistors “provide isolation and thereby lower the stand-by
`current or normal current drain of a sense amplifier where no writing
`operation is to occur.” Id. at 12:2–4.
`4. Lu
`Lu discloses “a sensing scheme for CMOS DRAM’s in which the bit
`line is precharged to half VDD” and states that “half-VDD bit-line sensing has
`several unique advantages . . . when compared to the full-VDD bit-line
`sensing scheme used for NMOS memory arrays or the grounded bit-line
`sensing scheme used for PMOS arrays in CMOS DRAM’s.” Ex. 1008, 451.
`According to Lu, these advantages include increased speed and reduced
`power consumption. Id. at 454.
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`C. Analysis of Grounds of Unpatentability
`1. Claims 1, 2, 5, 6, and 9
`Petitioner asserts that the subject matter of claims 1, 2, 5, 6, and 9
`would have been obvious over Sukegawa in view of Lu. Pet. 14–33.1
`Independent claim 1 requires a data transfer arrangement comprising
`two bus drivers, a voltage precharge source, and a differential bus coupled to
`the bus drivers and to the voltage precharge source. Petitioner contends that
`Sukegawa’s signal transmission circuit is a data transfer arrangement, and
`that transistor pairs 26/27 and 28/29 serve as bus drivers, BLR is the voltage
`precharge source, and bus lines LINE and LINE_ constitute a differential
`bus coupled to the bus drivers and voltage precharge source. Id. at 14–17
`(citing Ex. 1005, 6:37–39, 6:54–61, 7:29–43, 8:11–23, 8:29–31, 9:14–21,
`Fig. 1).
`Claim 1 further requires a latching sense amplifier coupled to the
`differential bus, wherein the latching sense amplifier comprises a first stage
`including a cross-coupled latch coupled to a differential data bus. Petitioner
`contends that Sukegawa’s amplifier circuits 1, 1A, and 1B, and receiving
`circuit 4 comprise a latching sense amplifier. Id. at 17–18. According to
`Petitioner, amplifier circuit 1 is the first stage of the latching sense amplifier,
`and includes a cross-coupled latch, as depicted in Figure 2 of Sukegawa. Id.
`
`
`1 Based on the current record, we agree with Petitioner that a person of
`ordinary skill in the art at the time of the ’130 patent (February 1999) would
`have had “an undergraduate degree in Electrical Engineering or equivalent
`and at least two to three years of experience in the design and/or analysis of
`data transfer circuits or the equivalent.” Pet. 9 (citing the Declaration of
`R. Jacob Baker, Ph.D., Ex. 1002 ¶ 15).
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`at 19–21. Petitioner also contends that a person of ordinary skill in the art
`would have understood that the line between transistors 34 and 38/39 and
`the line between transistors 35 and 40/41 comprise a differential data bus.
`Id. at 22 (noting that these lines “include differential data because of the
`amplified voltage differential on these lines”). Petitioner asserts that the first
`stage of Sukegawa’s latching sense amplifier (i.e., amplifier circuit 1) is
`coupled to the differential data bus through LINE, LINE_, and transistors 34
`and 35. Id. at 21–22. Petitioner provides an enlarged, annotated version of
`Sukegawa Figure 1, reproduced below. Id. at 22.
`
`
`Petitioner’s annotated figure illustrates the portions of Sukegawa’s signal
`transmission circuit that Petitioner points to as corresponding to the latching
`sense amplifier, including the first stage (shown in blue), differential data
`bus (shown in pink), and lines coupling the two (shown in green).
`Claim 1 also recites that the latching sense amplifier comprises an
`output stage coupled to an output of the first stage, wherein the output of the
`first stage is coupled to an input of the output stage. Petitioner contends that
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`receiving circuit 4 corresponds to the claimed output stage of the latching
`sense amplifier, and argues that nodes 101 and 102, terminals 4a and 4b, and
`lines LINE and LINE_ disclose the required coupling of the output of the
`first stage and the input of the output stage of the latching sense amplifier.
`Id. at 23–25. Petitioner provides an annotated figure, reproduced below,
`purporting to illustrate this relationship. Id. at 24.
`
`
`Petitioner’s annotated figure illustrates the portions of Sukegawa’s signal
`transmission circuit that Petitioner points to as corresponding to the output
`stage of the latching sense amplifier (shown in orange) and illustrates how
`the first stage is coupled to the output stage. Id.
`Claim 1 additionally requires that the differential bus and differential
`data bus are precharged to a voltage Vpr between Vdd and ground. Petitioner
`contends that the differential bus in Sukegawa is precharged to an
`intermediate voltage Vdd/2 (i.e., a voltage between Vdd and ground). Id. at
`25. According to Petitioner, Sukegawa explains that when amplifier circuit
`1 is in the precharge state, “the voltage at nodes 101 and 102 becomes the
`intermediate voltage VDD/2” and that “the BLR node becomes the power
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`source voltage VDD/2 in the initial precharge state.” Id. at 25–26 (citing Ex.
`1005, 7:26–37, 8:28–31) (emphasis omitted).
`Petitioner acknowledges Sukegawa discloses that the differential data
`bus is precharged to Vdd, but contends that a person of ordinary skill in the
`art would have modified Sukegawa in view of Lu, and precharged the
`differential data bus to Vdd/2 instead of Vdd. Id. at 26. Specifically,
`Petitioner argues that
`[o]ne of ordinary skill in the art . . . would have understood that
`precharging to an intermediate voltage would have been
`desirable to speed up operation of the circuit because pulling up
`or pulling down a node precharged to an intermediate voltage to
`full logic levels would require a smaller voltage swing (and
`thus be faster) versus a full Vdd voltage swing to pull down a
`node precharged to Vdd (as disclosed in Sukegawa with respect
`to the differential data bus).
`
`Id. at 26–27 (citing Lu’s teaching that “[a]t sensing and bit-line precharge in
`half-VDD sensing, the pullup and pulldown of bitlines are balanced and have
`only half-VDD swing”). Petitioner also contends that applying the teachings
`of Lu to Sukegawa “would have amounted to nothing more than the
`use of a known technique to improve similar devices in the same way and
`would have yielded nothing more than predictable results.” Id. at 27 (citing
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
`
`Petitioner provides similar citations, arguments, and illustrations with
`regard to the unpatentability of dependent claims 2, 5, 6, and 9 under 35
`U.S.C. § 103. See Pet. 27–33.
`Patent Owner argues that Sukegawa “appears to be inoperable” and
`“makes the problem it is trying to solve dramatically worse.” Prelim. Resp.
`11–13. Patent Owner thus argues that Sukegawa’s disclosure is non-
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`enabling and teaches away from the challenged claims. Id. at 13. Patent
`Owner also contends that Sukegawa relates to a transmission system, and is
`non-analogous art to the ’130 patent, which relates to a low level signal
`amplifier. Id. at 7–8. Patent Owner likewise argues that there is no way to
`combine Sukegawa’s “large transmission system with a transmitter, a
`transmission line with distributed line amplifiers, and a data receiver,” with
`Lu’s “tiny semiconductor sense amplifiers used with semiconductor
`memories.” Id. at 13.
`With regard to the specific limitations of claim 1, Patent Owner
`argues that what Petitioner considers to be the “first stage” of the latching
`sense amplifier in Sukegawa does not have an actual output that is coupled
`to the input of the output stage as required in claim 1. Id. at 15. According
`to Patent Owner, in-line amplifier 1, “does not properly have an ‘output’ but
`rather manipulates the voltage on the bus.” Id.
`Patent Owner also argues that Sukegawa does not disclose a
`differential data bus. Id. at 15–16. First, Patent Owner contends that the
`lines (highlighted in pink in the figure above) upon which Petitioner relies
`for disclosure of this limitation are “simply a pair of wires,” and not a bus.
`Id. at 16 (noting that a bus “typically has the property of a controlled
`impedance”). Second, Patent Owner argues that the alleged data bus is not
`differential. Id.
`Patent Owner then argues that, assuming Sukegawa discloses a
`differential bus and differential data bus as required by claim 1, Petitioner
`has failed to show that Sukegawa, either alone or in combination with Lu,
`teaches or suggests precharging both the differential bus and the differential
`data bus to the same pre-charge voltage, e.g., Vdd/2. Id. at 17–21.
`
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`According to Patent Owner “[w]hat the Petitioner has not provided is some
`teaching, suggestion or motivation in either reference to turn on transistors
`34 and 35 simultaneously to bring the two buses to the same pre-charge
`voltage while that pre-charge voltage is present in the differential bus.” Id.
`at 19–20.
`As to dependent claims 2, 5, 6, and 9, Patent Owner argues that they
`are non-obvious in view of their dependency on claim 1. Id. at 26.
`Upon review, we determine that the record before us establishes a
`reasonable likelihood that Petitioner would prevail on its assertion that the
`subject matter of claims 1, 2, 5, 6, and 9 would have been obvious in view of
`Sukegawa and Lu. Petitioner’s explanation of how each claim limitation is
`taught or suggested by the combination of prior art references is supported
`by the record and persuasive at this stage. See Pet. 14–33; Ex. 1002.
`Additionally, Petitioner’s explanation (1) that a person of ordinary skill in
`the art would have understood that precharging to an intermediate voltage
`would have been desirable to speed up operation of the circuit, and (2) that
`doing so would have amounted to nothing more than the use of a known
`technique to improve similar devices in the same way and would have
`yielded nothing more than predictable results, supports, on this record,
`Petitioner’s assertion that a person of ordinary skill in the art would have had
`reason to combine the teachings of the prior art to arrive at the claimed
`subject matter. Patent Owner’s arguments to the contrary are not persuasive
`on this record.
`For example, we are not persuaded by Patent Owner’s arguments that
`Sukegawa is non-enabling. Prior art publications and patents are presumed
`to be enabled. In re Antor Media Corp., 689 F.3d 1282, 1287–88 (Fed. Cir.
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`2012). Patent Owner has not rebutted the presumption that Sukegawa is
`enabling because it has not shown sufficiently that undue experimentation
`would be needed to practice the claimed invention. Id. at 1292.
`Additionally, it is well-settled that published subject matter is prior art for all
`that it teaches in obviousness determinations—even if the reference itself is
`not enabling. See id. (citing Symbol Techs. Inc. v. Opticon Inc., 935 F.2d
`1569, 1578 (Fed. Cir. 1991) (“[A] non-enabling reference may qualify as
`prior art for the purpose of determining obviousness under § 103.”)).
`
`Nor are we persuaded, on this record, by Patent Owner’s arguments
`that Sukegawa is non-analogous art to the ’130 patent, or that there is no
`way to combine Sukegawa with Lu. As Petitioner points out, Sukegawa and
`the ’130 patent are each directed to data transfer arrangements and
`improving the efficiency of such transfers. Pet. 4–5, 14; Ex. 1005, 4:52–55
`(“The purpose of this invention is to provide a type of signal transmission
`circuit wherein the signal transmission distance can be increased, and the
`signals can be transmitted at a high speed and with low power
`consumption.”); Ex. 1001, 1:11–60 (“The present invention relates to a data
`transfer scheme, and more particularly, to a high speed and low power
`CMOS data transfer scheme.”). Patent Owner’s asserted field of endeavor
`of the ’130 patent, “semiconductor memory sense amplifier[s],” is too
`narrow. See Prelim. Resp. 8, 23–24. Additionally, “a determination of
`obviousness based on teachings from multiple references does not require an
`actual, physical substitution of elements.” In re Mouttet, 686 F.3d 1322,
`1332 (Fed. Cir. 2012) (citing In re Etter, 756 F.2d 852, 859 (Fed. Cir. 1985)
`(en banc) (noting that the criterion for obviousness is not “whether the
`references [can] be physically combined[,] but whether the claimed
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`inventions are rendered obvious by the teachings of the prior art as a
`whole”)). Petitioner, at this stage, has explained sufficiently its proposed
`combination of Sukegawa and Lu. See Pet. 26–27; Ex. 1002 ¶ 31.
`
`With regard to the argument that Sukegawa does not disclose a
`differential data bus and does not have an actual output that is coupled to the
`input of the output stage as required in claim 1, we do not agree with Patent
`Owner’s assertion that the alleged bus is “simply a pair of wires” or that it is
`not differential under any circumstances. Prelim. Resp. 16. Instead, we are
`persuaded, at this stage, by Petitioner’s explanation as to why a person of
`ordinary skill in the art would understand Sukegawa to disclose these
`limitations. Pet. 21–23. Nor do we agree with Patent Owner’s assertion that
`in-line amplifier 1 “does not properly have an ‘output’ but rather
`manipulates the voltage on the bus.” Prelim. Resp. 15. Sukegawa, for
`example, describes amplifier circuit 1 as being connected to other
`components via “input/output shared terminal 1a at node 101.” Ex. 1005,
`6:54–58.
`
`We also find Patent Owner’s argument that Sukegawa, either alone or
`in combination with Lu, fails to disclose precharging both buses to the same
`pre-charge voltage to be, on this record, unpersuasive. Patent Owner
`reasons that Petitioner has failed to demonstrate that the prior art discloses or
`suggests simultaneously bringing the two buses to the same precharge
`voltage. Prelim. Resp. 19–20. Claim 1, however, requires only precharging
`both buses to the same voltage, not that the precharging occurs
`simultaneously.
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`2. Claim 3
`Petitioner contends that the subject matter of claim 3 would have been
`obvious over Sukegawa, Lu, and Watanabe. Pet. 33–45.
`Claim 3 depends from claim 1, and further requires that the first stage
`of the latching sense amplifier comprises a plurality of input pass transistors
`and a plurality of NMOS and PMOS transistors, with each having a gate, a
`source, and a drain. Claim 3 additionally specifies how the drains, gates,
`and sources of the transistors are coupled to one another and/or to a clock
`signal:
`wherein the drains of the input pass transistors are coupled to
`the drains of the cross-coupled latch amplifier NMOS and
`PMOS transistors, each source terminal of the input pass
`transistors is coupled to an input, the sources of the cross-
`coupled latch amplifier NMOS transistors are coupled to the
`drain of the NMOS transistor coupled to a clock signal input,
`and the sources of the PMOS transistors are coupled to the
`drain of the PMOS transistor having a gate coupled to an
`inverted clock signal input.
`
`Petitioner contends that Sukegawa and Lu disclose a latching sense
`amplifier having a first stage, but acknowledges that these references do not
`expressly disclose the remaining limitations in claim 3. Id. at 33–34.
`Petitioner relies on Watanabe for these limitations. Id. at 35–45. For
`example, Petitioner contends that Watanabe’s data latch 12 is a latching
`sense amplifier having a first stage, and that transistors Q37 and Q38 are
`input pass transistors. Id. at 35–36. Petitioner also contends that the
`identification of the sources and drains for the input pass transistors is
`dependent on the voltage provided to the transistors (id. at 36 n.7), and
`argues that a person of ordinary skill in the art “would have understood that
`the gate, source, and drain of the input pass transistors are as indicated” in
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`the annotated version of Watanabe, Figure 7, reproduced below. Id. at 36–
`37.
`
`
`Petitioner’s annotated figure illustrates the portions of Watanabe, Figure 7,
`that Petitioner points to as corresponding to the gate, source, and drain of the
`input pass transistors Q37 and Q38. Petitioner provides additional annotated
`figures to illustrate and support its contentions that Watanabe’s data latch
`discloses the remaining limitations in claim 3. See generally id. at 35–45.
`Petitioner asserts that it would have been obvious to a person of
`ordinary skill in the art to modify Sukegawa and Lu in view of Watanabe
`because the first stage of Watanabe’s latching sense amplifier provides
`certain advantages, such as increased speed and a smaller circuit layout. Id.
`at 33–34. Petitioner also contends that modifying Sukegawa’s first stage
`with Watanabe’s first stage would have amounted to using a known
`technique to improve similar devices in the same way, yielding predictable
`results. Id. at 34 (citing KSR, 550 U.S. at 417).
`Patent Owner argues that the combination of Sukegawa, Lu, and
`Watanabe cannot render claim 3 obvious because Sukegawa does not
`disclose a latching sense amplifier, making it “impossible” to modify
`Sukegawa with the first stage of Watanabe. Prelim. Resp. 27, 29. Patent
`Owner also argues that sources and drains are not clearly defined in
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`Watanabe, and, therefore, Petitioner arbitrarily draws sources and drains for
`Q37 and Q38 in Watanabe Figure 7 to satisfy the limitations of claim 3. Id.
`at 27–29.
`Even in light of Patent Owner’s arguments, we determine that
`Petitioner has shown a reasonable likelihood of prevailing on its assertion
`that the subject matter of claim 3 would have been obvious. First, as noted
`above, Petitioner has demonstrated sufficiently that Sukegawa discloses a
`latching sense amplifier. Petitioner also has provided a sufficient
`explanation based on the current record as to why a person of ordinary skill
`in the art would have had reason to combine the teachings of Sukegawa, Lu,
`and Watanabe.
`With regard to Petitioner’s identification of the sources and drains in
`Watanabe, Figure 7, both parties appear to agree that the identification of
`sources and drains is dependent upon the voltage applied to the circuit. Pet.
`36–37 n.7; Prelim. Resp. 29. In view of this, we disagree with Patent
`Owner’s argument that Petitioner arbitrarily draws sources and drains for
`transistors Q37 and Q38. Absent any persuasive information to the
`contrary,2 we find that Petitioner’s argument that a person of ordinary skill
`in the art would have understood the gate, source, and drain of input pass
`transistors Q37 and Q38 are as indicated in Petitioner’s annotated figures to
`be sufficient based on the current record.
`
`
`2 We note that Patent Owner has not argued or provided a factual basis to
`support a determination that Petitioner’s identification of sources and drains
`is incorrect or not possible in an operable device.
`
`
`
`17
`
`
`
`Case IPR2015-01524
`Patent 6,366,130
`
`
`3. Claim 7
`Petitioner contends that the subject matter of claim 7 would have been
`obvious over Sukegawa, Lu, and Hardee. Pet. 45–47.
`
`Claim 7 ultimately depends from claim 1, and requires active pull up
`and active pull down bus drivers that are NMOS transistors. Petitioner
`contends that Sukegawa discloses active pull down drivers that are NMOS
`transistors, but does not expressly disclose active pull up drivers that are
`NMOS transistors. Pet. 45. Petitioner thus relies on Hardee for its
`disclosure of using NMOS transistors as pull up and pull down drivers. Id.
`Petitioner argues that a person of ordinary skill in the art would have been
`motivated to modify Sukegawa and Lu to include NMOS pull up and pull
`down drivers in view of Hardee “to reduce the layout area and avoid latch-
`up.” Id. at 46. Petitioner further argues that using solely NMOS transistors
`as bus drivers in Sukegawa and Lu would have been merely a design choice,
`and amounted to using a known technique to improve similar devices to
`yield predictable results. Id. at 46–47.
`
`In response, Patent Owner argues that claim 7 cannot be determined to
`be obvious because it depends from a non-obvious independent claim.
`Prelim. Resp. 29–30.
`
`Upon review, we determine that the record before us establishes a
`reasonable likelihood that Petitioner would prevail on its assertion that the
`subject matter of claim 7 would have been obvious in view of Sukegawa,
`Lu, and Hardee. Petitioner’s explanation of how each claim limitation is
`taught or suggested by the combination of prior art references is sufficient
`on this record, as is Petitioner’s assertion that a person of ordinary skill in
`
`
`
`18
`
`
`
`Case IPR2015-01524
`Patent 6,366,130
`
`the art would have had reason to combine the teachings of the prior art to
`arrive at the claimed subject matter.
`
`
`IV.
`CONCLUSION
`Based on the information presented, we conclude that Petitioner has
`demonstrated a reasonable likelihood of prevailing with respect to its
`challenges to claims 1–3, 5–7, and 9 of the ’130 patent.
`The Board has not made a final determination as to the patentability of
`any challenged claim.
`
`
`V. ORDER
`For the reasons given, it is hereby
`ORDERED that pursuant to 35 U.S.C. § 314(a), an inter partes
`review is hereby instituted as to claims 1–3, 5–7, and 9 of the ’130 patent
`with respect to the following grounds:
`1. Whether claims 1, 2, 5, 6, and 9 are unpatentable under 35 U.S.C.
`§ 103 as obvious over the combination of Sukegawa and Lu;
`2. Whether claim 3 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Watanabe; and
`3. Whether claim 7 is unpatentable under 35 U.S.C. § 103 as obvious
`over the combination of Sukegawa, Lu, and Hardee;
`FURTHER ORDERED that no ground other than those specifically
`listed above is authorized for the inter partes review as to the ’130 patent;
`and
`
`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
`37 C.F.R. § 42.4, notice is given of the institution of the trial.
`
`
`
`19
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`
`
`Case IPR2015-01524
`Patent 6,366,130
`
`PETITIONER:
`Steven L. Park
`Paul Hastings LLP
`stevenpark@paulhastings.com
`
`Naveen Modi
`Paul Hastings LLP
`naveenmodi@paulhastings.com
`
`PATENT OWNER:
`Clifford H. Kraft
`clifflaw@att.net
`
`Joseph N. Hosteny
`Niro, Haller & Niro
`hosteny@hosteny.com
`
`
`
`
`20
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