Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 26
`
` Entered: January 17, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD,
`Petitioner,
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED,
`Patent Owner.
`____________
`
`Case IPR2015-01524
`Patent 6,366,130
`____________
`
`
`
`
`
`Before JUSTIN T. ARBES, JEFFREY W. ABRAHAM, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a)
`
`
`
`
`
`571-272-7822
`
`
`Paper No. 26
`
` Entered: January 17, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD,
`Petitioner,
`
`v.
`
`ELBRUS INTERNATIONAL LIMITED,
`Patent Owner.
`____________
`
`Case IPR2015-01524
`Patent 6,366,130
`____________
`
`
`
`
`
`Before JUSTIN T. ARBES, JEFFREY W. ABRAHAM, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`Case IPR2015-01524
`Patent 6,366,130
`
`
`I.
`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner”) filed a Petition seeking
`inter partes review of claims 1–3, 5–7, and 9 of U.S. Patent No. 6,366,130
`B1 (Ex. 1001, “the ’130 patent”), as amended by Inter Partes
`Reexamination Certificate No. US 6,366,130 C1 (“Reexam. Cert.”). Paper 1
`(“Pet.”). Elbrus International Limited (“Patent Owner”) filed a Preliminary
`Response to the Petition. Paper 8. On January 19, 2016, we instituted an
`inter partes review of claims 1–3, 5–7, and 9. Paper 9 (“Dec. on Inst.”).
`After institution, Patent Owner filed a Patent Owner Response (Paper
`12, “PO Resp.”), and Petitioner filed a Reply (Paper 16, “Reply”). An oral
`hearing was held on October 18, 2016, and a transcript of the hearing has
`been entered into the record of the proceeding as Paper 25 (“Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 1, 2, 5–7, and 9 are unpatentable.
`II.
`BACKGROUND
`A. Related Proceedings
`The parties identify Cascades Computer Innovation, LLC. v. Samsung
`Electronics Co., Ltd., Case No. 1-14-cv-05691 (N.D. Ill). Pet. 1–2; Paper 4,
`3.
`
`B. The ’130 Patent
`The ’130 patent, titled “High Speed Low Power Data Transfer
`Scheme,” issued on April 2, 2002, with a reexamination certificate issuing
`on August 4, 2014. The ’130 patent is directed to a “high speed and low
`power [complementary metal-oxide semiconductor (CMOS)] data transfer
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`arrangement that includes two active pull up/pull down bus drivers, a
`differential bus that precharges to a specific voltage level and a latched
`differential sense amplifier that serves as a bus receiver.” Ex. 1001, 1:24–
`28, Fig. 1. In one embodiment, the latching sense amplifier is arranged as a
`“cross coupled latched amplifier.” Id. at 1:36–38, Fig. 2. The ’130 patent
`explains that its data transfer scheme can operate at increased speeds due to,
`inter alia, precharging the buses to a specific level (Vpr) between ground
`and Vdd. Id. at 2:23–38, 3:17–55.
`C. Illustrative Claim
`Petitioner challenges claims 1–3, 5–7, and 9. Claim 1 is the only
`independent claim challenged and is reproduced below.
`1. A data transfer arrangement comprising:
`two bus drivers;
`a voltage precharge source;
`a differential bus coupled to the bus drivers and to the voltage
`precharge source; aid
`a latching sense amplifier coupled to the differential bus;
`wherein the latching sense amplifier comprises:
`a first stage including a cross-coupled latch coupled to a
`differential data bus; and
`an output stage coupled to an output of said first stage;
`wherein the output of the first stage is coupled to an input of the
`output stage;
`wherein the differential bus and the differential data bus are
`precharge to a voltage Vpr between Vdd and ground, where
`Vpr=K*Vdd, and K is a precharging voltage factor.
`
`Id. at 4:2–17.
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`D. References
`Petitioner relies on the following references:
`Sukegawa, U.S. Patent No. 5,828,241, issued Oct. 27, 1998
`(“Sukegawa,” Ex. 1005).
`Watanabe et al., U.S. Patent No. 6,108,254, filed Nov. 12,
`1993, issued Aug. 22, 2000 (“Watanabe,” Ex. 1006).
`Hardee, U.S. Patent No. 6,249,469 B1, filed July 1, 1996,
`issued June 19, 2001 (“Hardee,” Ex. 1007).
`Nicky Chau-Chun Lu & Hu H. Chao, Half-VDD Bit-Line
`Sensing Scheme in CMOS DRAM’s, SC-19:4 IEEE JOURNAL
`OF SOLID STATE CIRCUITS 451–454 (1984) (“Lu,” Ex. 1008).
`
`
`§103
`
`§103
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`E. Reviewed Grounds of Unpatentability
`The Board instituted trial to review the patentability of the challenged
`claims on the following grounds (Dec. on Inst. 19):
`References
`Statutory Basis Claim(s) Challenged
`§103
`Sukegawa and Lu
`1, 2, 5, 6, and 9
`Sukegawa, Lu, and
`Watanabe
`Sukegawa, Lu, and
`Hardee
`
`
`
`F. Level of Ordinary Skill in the Art
`Petitioner’s declarant, R. Jacob Baker, Ph.D., testified that “a person
`of ordinary skill in the art related to the technology of the ’130 Patent would
`have had an undergraduate degree in Electrical Engineering or equivalent
`and at least two to three years of experience in the design and/or analysis of
`data transfer circuits or the equivalent.” Ex. 1002 ¶ 15. Patent Owner’s
`declarant, William R. Huber, D.Sc., similarly testified that a person of
`ordinary skill in the art would have had “a Bachelor of Science degree in
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`Electrical Engineering or an equivalent field, as well as at least 2 years of
`experience designing and analyzing data transfer or equivalent circuits.” Ex.
`2004 ¶ 27.
`We credit the testimony provided by the declarants for both parties
`and hold that one of ordinary skill in the art would have possessed an
`undergraduate degree in electrical engineering or equivalent field and at
`least two years of experience in the design and/or analysis of data transfer or
`equivalent circuits. This level of ordinary skill is reflected not only by the
`information presented by the parties, but also by the prior art of record.
`Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (the prior art
`itself can reflect the appropriate level of ordinary skill in the art).
`
`
`III. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b); see
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016)
`(upholding the use of the broadest reasonable interpretation standard). In
`applying a broadest reasonable construction, claim terms generally are given
`their ordinary and customary meaning, as would be understood by one of
`ordinary skill in the art in the context of the entire disclosure. See In re
`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Based on the parties’ post-issuance arguments (Reply 2–6; PO Resp.
`20–24; Tr. 33:25–34:6), we address the proper interpretation of the claim
`term “bus,” which we discuss below. No other express claim construction is
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`necessary. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795,
`803 (Fed. Cir. 1999) (“[O]nly those terms need be construed that are in
`controversy, and only to the extent necessary to resolve the controversy.”).
`“bus”
`Claim 1 requires a “differential bus” and a “differential data bus.”
`The ’130 patent does not expressly define “bus.” Petitioner contends that
`“bus” is a term of art and should be given its plain and ordinary meaning.
`Reply 2. Relying on the 1994 IEEE Standard Glossary of Computer
`Hardware Terminology, Petitioner contends that a “bus” is understood to be
`“one or more conductors that are used for the transmission of signals, data,
`or power.” Ex. 1010, 13; Reply 2. Petitioner contends that this definition is
`consistent with the use of the term in the ’130 patent and supported by Dr.
`Baker’s testimony. Reply 2–3 (citing Ex. 1001, Fig. 1, 2:1–22, 4:2–18; Ex.
`2003, 49:4–9, 49:15–17). Patent Owner, relying on the June 2013 JEDEC
`Dictionary of Terms for Solid-State Technology, argues that a “bus” is
`defined as “[a] common path along which power or signals travel from one
`or several sources to one or several destinations.” Ex. 2005, 27;1 see PO
`Resp. 21–22 & n.2.
`We agree with, and adopt, Petitioner’s interpretation of the plain and
`ordinary meaning of bus, as informed by the 1994 IEEE Standard Glossary
`of Computer Hardware Terminology. It is well settled that judges may
`consult dictionary definitions when construing claim terms so long as the
`dictionary definition does not contradict any definition found in or
`ascertained by a reading of the patent documents. Vitronics Corp. v.
`
`
`1 Page numbers for this exhibit refer to the page numbers in the top right or
`left corner of each page of the exhibit.
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`Conceptronic, Inc., 90 F.3d 1576, 1585 n.6 (Fed. Cir. 1996). Petitioner’s
`proposed construction satisfies this criteria, because, as noted above, the
`’130 patent does not include a definition of “bus,” and the ’130 patent uses
`the claimed buses as part of its data transfer arrangement, wherein the bus
`lines are charged to a particular voltage and used to transfer data. Ex. 1001,
`2:12–38.
`We do not adopt Patent Owner’s proposed interpretation because, as
`Petitioner argues and Patent Owner acknowledges, the reference upon which
`Patent Owner relies was published several years after the filing date of the
`application leading to the ’130 patent. Tr. 35:7–13; see also Reply 3
`(Petitioner arguing that Patent Owner’s interpretation of “bus” is flawed
`because it is from a document dated over 13 years after the alleged invention
`date of the ’130 patent). Additionally, Dr. Huber elaborates on Patent
`Owner’s understanding of the term “bus,” stating that a bus, unlike a node,
`has a span, and acts like a bridge between two points. Ex. 2004 ¶ 59, 62.
`Dr. Huber, however, offers no underlying facts or data to support this
`interpretation. Pursuant to 37 C.F.R. § 42.65(a), such testimony is entitled
`to little or no weight. Also, neither definition from the parties’ technical
`dictionaries includes a “span” requirement for the term. See Exs. 1010,
`2005; Tr. 35:14–17.
`We thus find the broadest reasonable interpretation of “bus” in light of
`the ’130 patent Specification is “one or more conductors that are used for the
`transmission of signals, data, or power.” Ex. 1010, 13; Reply 2.
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`B. Principles of Law
`To prevail in this inter partes review of the challenged claims,
`Petitioner must prove unpatentability by a preponderance of the evidence.
`35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness.
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`A party that petitions the Board for a determination of obviousness
`must show that “a skilled artisan would have been motivated to combine the
`teachings of the prior art references to achieve the claimed invention, and
`that the skilled artisan would have had a reasonable expectation of success in
`doing so.” Procter & Gamble Co. v. Teva Pharms. USA, Inc., 566 F.3d 989,
`994 (Fed. Cir. 2009) (quoting Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348,
`1361 (Fed. Cir. 2007)).
`
`C. References
`1. Sukegawa
`Sukegawa discloses a “signal transmission circuit which enables the
`distance of signal transmission . . . to be increased, while the signal delay
`and power consumption are reduced.” Ex. 1005, Abstract. Sukegawa
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`teaches that “the signal is amplified and transmitted by means of the positive
`feedback of an intermediate amplifier circuit having input/output shared
`terminals.” Id. at 1:12–15. Sukegawa provides circuit diagrams illustrating,
`and corresponding descriptions in the specification describing, the specific
`configuration of the various components of its transmission circuit. See id.
`at 6:35–9:50, Figs. 1–7.
`
`2. Watanabe
`Watanabe discloses a “[dynamic random access memory (DRAM)]
`having means which can transfer data at a sufficiently high speed.” Ex.
`1006, 1:64–65. Watanabe’s data transfer circuit contains differential
`amplifier circuit 10, equalizing circuit 11, data latch circuit 12, pairs of first
`data lines 13 and second data lines 14, and pair of data output lines 15. Id. at
`3:41–44, Fig. 1. In one embodiment, data latch circuit 12 comprises three n-
`channel MOS transistors and five p-channel MOS transistors, arranged as
`shown in Figure 7 of Watanabe. Id. at 4:13–19, Fig. 7. Watanabe explains
`that its transfer circuit is an improvement over conventional data transfer
`control systems because data transfer can occur without having to take the
`time to equalize its data lines. Id. at 2:52–56.
`3. Hardee
`Hardee discloses a “sense amplifier for a very high density integrated
`circuit memory using CMOS technology.” Ex. 1007, Abstract. Hardee
`further discloses a preferred sense amplifier containing, inter alia, “N
`channel devices having their source-drain paths coupled in series.” Id. at
`6:28–46 (referring to transistors 128, 130, 132, 134), Fig. 5. Hardee states
`that these transistors “provide isolation and thereby lower the stand-by
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`current or normal current drain of a sense amplifier where no writing
`operation is to occur.” Id. at 12:2–4.
`4. Lu
`Lu discloses “a sensing scheme for CMOS DRAM’s in which the bit
`line is precharged to half VDD” and states that “half-VDD bit-line sensing has
`several unique advantages . . . when compared to the full-VDD bit-line
`sensing scheme used for NMOS memory arrays or the grounded bit-line
`sensing scheme for PMOS arrays in CMOS DRAM’s.” Ex. 1008, 451.
`According to Lu, these advantages include increased speed and reduced
`power consumption. Id. at 453.
`D. Analysis of Grounds of Unpatentability
`1. Claims 1, 2, 5, 6, and 9
`Petitioner asserts that the subject matter of claims 1, 2, 5, 6, and 9
`would have been obvious over Sukegawa in view of Lu. Pet. 14–33.
`Petitioner provides detailed explanations, including claim charts and the
`declaration of Dr. Baker, to show how Sukegawa and Lu disclose or suggest
`each limitation of claims 1, 2, 5, 6, and 9. In our Decision on Institution, we
`determined that Petitioner had made a threshold showing that the prior art
`discloses or suggests all limitations of these claims sufficient for us to
`conclude that there was a reasonable likelihood that Petitioner would prevail
`in showing that the subject matter of the challenged claims would have been
`obvious in view of Sukegawa and Lu. Dec. on Inst. 7–14.
`In its Response, Patent Owner disputes that Sukegawa and Lu disclose
`two limitations of claim 1, and argues that “Sukegawa teaches away from
`the ’130 invention” and that “Petitioner’s solution is unworkable in
`practice.” PO Resp. 17–18. Patent Owner also argues that Petitioner fails to
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`show that Sukegawa and Lu disclose or suggest precharging the differential
`bus to a voltage that “is less than a logic high voltage and greater than a
`logic low voltage,” as required by dependent claim 5. Id. at 37–42. For the
`remaining dependent claims, Patent Owner argues that because the subject
`matter of claim 1 would not have been obvious, the subject matter of the
`dependent claims also would not have been obvious. Id. at 45. Finally,
`Patent Owner argues that Petitioner improperly relies on hindsight to
`establish obviousness. Id. at 43–45.
`a. The Disputed Limitations of Claim 1
`i. “differential data bus”
`Claim 1 requires a “first stage including a cross-coupled latch coupled
`to a differential data bus.”
`Petitioner argues that Sukegawa discloses a first stage coupled to a
`differential data bus, and, in support, provides an enlarged, annotated
`version of Sukegawa Figure 1, reproduced below. Pet. 22.
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`Petitioner’s annotated figure is a circuit diagram depicting portions of
`Sukegawa’s signal transmission circuit, and Petitioner identifies the
`elements of the circuit that Petitioner points to as corresponding to the first
`stage (shown in blue), differential data bus (shown in pink), and lines
`coupling the two (shown in green) as required by claim 1. Id.
`Petitioner contends that a person of ordinary skill in the art would
`have understood that the “lines associated with nodes C (shown . . . in pink)”
`comprise a differential data bus. Id. (noting that these lines “include
`differential data because of the amplified voltage differential on these
`lines”). Petitioner asserts that the first stage of Sukegawa’s latching sense
`amplifier (i.e., amplifier circuit 1) is coupled to the differential data bus
`through LINE, LINE_, and transistors 34 and 35. Id. at 21–22.
`Patent Owner argues that Petitioner “improperly identifies nodes C as
`a bus” and contends that “the fact that a pair of nodes exhibits differential
`voltage does not make the pair of nodes a bus.” PO Resp. 20.2 According to
`Patent Owner, nodes are simply electrical connections between two or more
`components, whereas a bus, unlike a node, “has a span or distance between a
`source and a destination, and transfers data from one to the other.” Id. at
`20–22 (citing Ex. 2004 ¶¶ 58, 59, 62). Patent Owner’s declarant, Dr. Huber,
`testifies that nodes N3 and N4 have neither a source nor a destination, and
`therefore do not form a bus. Ex. 2004 ¶ 59. Patent Owner points out that
`Sukegawa expressly identifies N3 and N4 as nodes. PO Resp. 24 (citing Ex.
`1005, 9:12–13).
`
`2 Patent Owner does not dispute that nodes C, N3, and N4 carry a
`differential charge. PO Resp. 20, 25. Rather, Patent Owner disputes only
`Petitioner’s assertion that the segments of the circuit of Sukegawa Petitioner
`relies upon are a bus. Tr. 7:14–19.
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`In its Reply, Petitioner notes that although Patent Owner focuses its
`arguments on nodes C, N3, and N4, Petitioner identified more than just these
`nodes as corresponding to the claimed bus in the Petition. Reply 2. Rather,
`Petitioner contends that the lines associated with the nodes Petitioner
`highlighted in pink (referred to herein as the “pink lines”) in the Petition
`comprise the differential data bus. Id. As noted above, Petitioner argues
`that the plain and ordinary meaning of “bus” is “one or more conductors that
`are used for the transmission of signals, data, or power.” Id. (quoting Ex.
`1010, 13). According to Petitioner, the pink lines in Sukegawa are
`conductors because they conduct electricity, and are used for the
`transmission of signals because they are located in Sukegawa’s receiver
`circuit, and on the path from the input to the output of Sukegawa’s “signal
`transmission” system. Id. at 3–4 (citing Pet. 19; Ex. 1005, Fig. 1, 9:4–7,
`9:14–24; Ex. 1011, 37:10–38:18, 49:12–20, 56:5–15).
` Petitioner also asserts that the pink lines constitute a bus even under
`Patent Owner’s interpretation of that term, because these lines are “a
`common path along which signals are transmitted between” at least one
`source (e.g., transistors 34 and 35) and at least one destination (e.g.,
`inverters 36 and 37 and transistors 38–41). Id. at 4–5. Thus, according to
`Petitioner, the pink lines span a distance between these devices, and act like
`a bridge between two points. Id. at 5. In support of this position, Petitioner
`directs us to Dr. Baker’s testimony that “there is a ‘wire on the input of
`[inverters] 36 and 37.’” Id. (citing Ex. 2003, 48:16–49:2). Petitioner also
`directs us to Dr. Huber’s testimony acknowledging that a different portion of
`Sukegawa’s circuit (the differential bus) has a “finite distance” even though
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`Sukegawa does not expressly disclose any physical dimensions. Id. (citing
`Ex. 1011, 39:9–23).
`Finally, Petitioner argues that the fact that the pink lines in Sukegawa
`include nodes does not preclude them from being a bus or detract from other
`evidence showing that Sukegawa discloses a differential data bus. Id. at 6.
`ii. Analysis
`For the reasons discussed below, based on the evidence developed
`during trial, we find that Sukegawa discloses a differential data bus.
` As discussed above, we determine that the broadest reasonable
`interpretation of “bus” in light of the ’130 patent Specification is “one or
`more conductors that are used for the transmission of signals, data, or
`power.” Ex. 1010, 13; Reply 2. Sukegawa discloses a “signal transmission
`circuit,” wherein a signal is transmitted to receiver circuit 4 containing
`output terminals OUT and OUT_. Ex. 1005, Fig. 1, 9:4–24. We agree with
`Petitioner that the lines between transistor 34 and inverter 36 are used to
`transmit signals from input 4a to the output labeled OUT_, and that the lines
`between transistor 35 and inverter 37 are used to transmit signals from input
`4b to the output labeled OUT. Pet. 23–25; Reply 3–5; Ex. 1005, Fig. 1, 9:4–
`7, 9:14–24; Ex. 1011, 37:10–38:18. Sukegawa explains that these lines
`carry a voltage (i.e., an electrical signal). Ex. 1005, 8:59–64, 9:4–7; Pet. 26;
`Ex. 1002 ¶ 31. Dr. Huber, Patent Owner’s declarant, agreed that “the
`connections of the various transistors” in Sukegawa Figure 1, including
`transistors 34 and 35, are conductors. Ex. 1011, 48:25–49:20. We agree
`with Petitioner that a person of ordinary skill in the art would consider these
`lines to be conductors. Reply 3. Thus, under our (and Petitioner’s)
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`construction of the term “bus,” the pink lines Petitioner identified in
`Sukegawa comprise a “bus.”
`Patent Owner does not dispute expressly that Sukegawa discloses a
`differential data bus according to Petitioner’s understanding of the plain and
`ordinary meaning of “bus,” which we adopt. Instead, Patent Owner
`proposes that Petitioner’s proposed meaning is incorrect. Tr. 34:14–17. For
`the reasons discussed above, we disagree.
`Nevertheless, we agree with Petitioner that Sukegawa discloses a bus
`even under Patent Owner’s understanding of the term. Reply 4–5. For
`example, the pink lines in Sukegawa comprise a path along which
`transmission signals travel from transistors 34 and 35 (i.e., sources) to
`inverters 36 and 37, on their way to outputs OUT_ and OUT, respectively
`(i.e., destinations). Ex. 1005, Fig. 1; 8:59–64, 9:4–7.
`Additionally, Dr. Huber provides an annotated version of Figure 2 of
`the ’130 patent, reproduced below.
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`
`Ex. 2004 ¶ 47. Figure 2 of the ’130 patent is a circuit diagram illustrating
`the parts of sensing amplifier 16. Ex. 1001, 2:40–41. According to Dr.
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`Huber, the portions highlighted in green comprise a “differential data bus.”
`Ex. 2004 ¶ 47.
`The only apparent difference between the green lines in Figure 2 of
`the ’130 patent and the pink lines in Sukegawa is the length of the lines. Tr.
`35:21–36:2. Although Patent Owner contends a bus needs to span some
`distance, neither Patent Owner nor Dr. Huber set forth a specific distance
`requirement for something to be a bus. Instead, when referring to LINE and
`LINE_ in Figure 1 of Sukegawa, which Dr. Huber admitted comprise a bus,
`Dr. Huber testified that “I think it’s clear from the drawing that it is a -- a
`finite distance. It’s not a zero distance or it’s not a distance that you can
`minimize. It looks to be transmitting from one portion of the circuit to
`another portion, which are physically separate.” Ex. 1011, 39:13–23.
`Figure 1 of Sukegawa likewise shows a finite, non-zero distance
`between transistors 34 and 35 and inverters 36 and 37, respectively, and
`discloses transmitting from one portion of the circuit to another portion.
`Although Dr. Baker testified that a person of ordinary skill in the art would
`seek to minimize the distance between node and inverter, he maintained that
`there would be a wire there. Ex. 2003, 47:19–49:2. We agree.
`In contesting that Sukegawa discloses a differential data bus under its
`interpretation, Patent Owner focuses on nodes C, N3, and N4, arguing that
`these components do not constitute a bus. Petitioner, however, relies on
`more than just nodes C, N3, and N4 as corresponding to the bus.
`Additionally, Dr. Baker testified that “a bus may have multiple wires with
`multiple nodes.” Ex. 2003, 57:5–6. This appears to be consistent not only
`with what the green lines of the ’130 patent depict, which Dr. Huber testified
`comprise a bus, but also with what the pink lines in Sukegawa depict. Patent
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`Owner’s argument, therefore, is unavailing, as it fails to address directly and
`adequately Petitioner’s assertion that the pink lines associated with nodes C,
`N3, and N4, and not just the nodes themselves, comprise the differential data
`bus.
`
` Based on the foregoing, we find that Petitioner has established by a
`preponderance of the evidence that the pink lines in Sukegawa constitute a
`differential data bus under either party’s meaning of the term.
`iii. “precharge to a voltage Vpr between Vdd and ground”
`Claim 1 additionally requires that the differential bus and differential
`data bus are precharged “to a voltage Vpr between Vdd and ground.”
`Petitioner contends that the differential bus in Sukegawa is precharged to an
`intermediate voltage Vdd/2 (i.e., a voltage between Vdd and ground). Pet.
`25. Petitioner acknowledges Sukegawa discloses that the differential data
`bus is precharged to Vdd, but notes that Sukegawa “provides no criticism of
`precharging the ‘differential data bus’ to a value under Vdd, such as Vdd/2.”
`Reply 8. Petitioner contends that given the advantages of precharging to an
`intermediate voltage, for example, as taught by Lu, a person of ordinary skill
`in the art would have had reason to modify Sukegawa in view of Lu, and
`precharge the differential data bus to Vdd/2 instead of Vdd. Pet. 26–27;
`Reply 7–8. Specifically, Petitioner argues that
`[o]ne of ordinary skill in the art . . . would have understood that
`precharging to an intermediate voltage would have been
`desirable to speed up operation of the circuit because pulling up
`or pulling down a node precharged to an intermediate voltage to
`full logic levels would require a smaller voltage swing (and
`thus be faster) versus a full Vdd voltage swing to pull down a
`node precharged to Vdd (as disclosed in Sukegawa with respect
`to the differential data bus).
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`Pet. 26–27 (citing Lu’s teaching that “[a]t sensing and bit-line precharge in
`half-VDD sensing, the pullup and pulldown of bitlines are balanced and have
`only half-VDD swing”); Reply 7; Ex. 1002 ¶ 31. Petitioner contends that the
`advantages of intermediate voltage precharging were well-known in the art,
`as acknowledged by Dr. Huber and as set forth explicitly in Lu. Pet. 26–27;
`Reply 7, 11; Ex. 1008, Abstract, 453 (listing advantages (1)–(4) of
`intermediate voltage precharging); Ex. 1011, 58:15–59:18; Ex. 1002 ¶ 31.
`Petitioner also contends that applying the teachings of Lu to
`Sukegawa “would have amounted to nothing more than the use of a known
`technique to improve similar devices in the same way and would have
`yielded nothing more than predictable results.” Pet. 27 (citing KSR, 550
`U.S. at 417); Reply 11–12. In support of its position, Petitioner directs us to
`Dr. Baker’s testimony explaining that a person of ordinary skill in the art
`would have been able to make the necessary adjustments to Sukegawa so
`that it would work. Reply 12–14 (citing Ex. 1002 ¶ 31; Ex. 2003, 63:20–
`64:1, 64:7–12, 75:9–16, 79:15–81:23, 109:23–110:8).
`
`Patent Owner argues that Sukegawa teaches away from precharging
`the differential data bus to Vdd/2 because it explicitly teaches precharging
`that bus to Vdd. PO Resp. 28–30. According to Patent Owner,
`[s]ince Sukegawa knew and practiced Vdd/2 in the same
`invention and specifically chose not to bring nodes N3 and N4
`to Vdd/2, but rather to Vdd, this leads the person of ordinary
`skill in the art in a divergent direction by teaching that it would
`be undesirable to bring nodes N3 and N4 to some intermediate
`value, but rather that they should be brought completely to Vdd.
`Id. at 29–30; Ex. 2004 ¶¶ 65–66.
`
`Patent Owner also argues that Petitioner’s proposed modification to
`precharge nodes N3 and N4 to Vdd/2 would result in “an unacceptable and
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`practically unworkable circuit with undesirable leakage currents.” PO Resp.
`33–34. In support of its position, Patent Owner directs us to testimony from
`Dr. Huber who concludes that modifying Sukegawa in view of Lu, as
`suggested by Dr. Baker, would result in unacceptable “power-wasting
`current paths.” Ex. 2004 ¶¶ 67–71; PO Resp. 30–34.
`Patent Owner additionally argues that Lu fails to disclose or suggest
`precharging to Vdd/2. PO Resp. 34. Patent Owner asserts that Lu does not
`define any definite precharging value, but instead teaches precharging two
`bit-line halves at “nearly half VDD,” which means that the bit-line halves are
`floating, and their voltages can change over time. Id. at 35–36 (citing Ex.
`1008, 452; Ex. 2004 ¶ 74; Ex. 2003, 26:18–27:4, 28:10–17). According to
`Patent Owner, claim 1 requires a precharge voltage that does not float. Id. at
`37.
`
`iv. Analysis
`For the reasons discussed below, based on the evidence developed
`during trial, we find that the combined teachings of Sukegawa and Lu
`disclose precharging the differential data bus to a voltage between Vdd and
`ground, and that a person of ordinary skill in the art would have been
`motivated to combine the references’ teachings.
`Sukegawa and Lu each disclose precharging certain portions of a
`circuit to Vdd/2. Ex. 1005, 7:29–31 (“In this case, the voltage at nodes 101
`and 102 becomes the intermediate voltage VDD/2 . . . .”); Ex. 1008, Abstract
`(“A sensing scheme in which the bit line is precharged to half VDD is
`introduced from CMOS DRAM’s.”). Contrary to Patent Owner’s argument
`that Lu fails to disclose a precharging source, Lu expressly states that “[t]he
`bit lines are precharged to a reference voltage approximately equal to VDD/2,
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`which can be obtained from a voltage regulator.” Ex. 1008, 451. Lu
`describes this as one of two possible mechanisms for precharging to Vdd/2,
`the other mechanism involving shorting two bit-line halves. Id. In arguing
`that Lu fails to disclose any definite precharging value, Patent Owner
`focuses on Lu’s disclosure of the operation involving shorting two bit-line
`halves, and does not address the alternative mechanism. PO Resp. 34–35.
`Thus, even if we were to agree with Patent Owner’s argument with regard to
`the shorting mechanism, this would not detract from Lu’s disclosure of the
`alternative mechanism for precharging to Vdd/2 using a voltage regulator.
`See In re Fritch, 972 F.2d 1260, 1264 (Fed. Cir. 1992) (“It is well settled
`that a prior art reference is relevant for all that it teaches to those of ordinary
`skill in the art.”).
`We recognize that Sukegawa teaches pre-charging the differential data
`bus to Vdd, not Vdd/2. Lu, however, expressly discloses several advantages
`of pre-charging to Vdd/2, including increasing chip reliability, providing
`better speed, and reducing power for charging and discharging the bit lines.
`Ex. 1008, 453. Dr. Huber likewise testified that there are “many
`advantages” to intermediate voltage precharging. Ex. 1011, 58:15–59:15.
`Petitioner has thus provided evidence demon
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