Page 1 of 22
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`SAMSUNG EXHIBIT 1005
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`SAMSUNG EXHIBIT 1005
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`Page 2 of 22
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`Page 3 of 22
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`Page 4 of 22
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`Page 5 of 22
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`U.S. Patent
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`00028:1r..PA
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`Sheet 5 of 12
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`6,052,328
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`‘-\l
`Q'%
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`§
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`\EE.§
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`Page 6 of 22
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`Page 7 of 22
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`Page 8 of 22
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`U.S. Patent
`
`00028:1r..PA
`
`Sheet 8 of 12
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`6,052,328
`
`SEQQ
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`_.
`
`anwk.....--"E.,§,§
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`_“___" "---‘I
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`Page 9 of 22
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`Page 10 of 22
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`U.S. Patent
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`Apr. 18, 2000
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`21f0014|.66hS
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`6,052,328
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`:5:E:3
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`.§:§§
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`;:3.3aIE339
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`>5:Sufi
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`.33.N..~..S
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`Roi39$
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`5:959
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`,£,s:§.m,:§_
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`K33%
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`anE525
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`23.539%
`
`Enmzza
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`Page 11 of 22
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`Page 12 of 22
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`Page 13 of 22
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`Page 19 of 22
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`Page 20 of 22
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`6,052,328
`
`15
`as to allow the read or write operation to be rolled into the
`beginning of the next cycle. As illustrated in FIG. 12 for the
`timing diagram DL (for the data lines DL1 and DL2), for
`each of the timing periods READAO, WRITEAI, READA2
`and READA3, the data remains on the data lines into the
`next period until the restore clock signal DLEQ goes high.
`This enables the overall cycle times to be reduced by
`maximizing the active read/write time and minimizing latcl1-
`ing and pipeline stage transfer time. This is in contrast to a
`system where, for example, the read/write signal was latched
`at the end of the cycle, which would require the cycle times
`to be extended to produce the same available data times
`shown for timing diagram DL in FIG. 12.
`Another advantage of this invention as described above is
`that it uses the read data path as a read/write data path. As
`described above with reference to FIGS. 1, 4 and 5, the clock
`signals DCLK and IOEQ control the equalization circuits
`between the data latch lines DLL1 and DLL2, and the
`input/output lines 101 and 102, respectively. As illustrate
`with respect to FIGS. 7 and 8, clock signals IOEQ anc
`DCLK are disabled during a write operation so as to allow
`the lines 101, I02, DLL1, and DLL2 to be over-driven with
`the write data. As illustrated in FIG. 9, and in timing perioc
`W'RITEAl of FIG. 12, the over driving of the lines IO1, IO2,
`DLL1, and DLL2 allows the write data to be quickly
`transitioned up the lines so that it is available to the data line
`sense amp 32. As described above, the data is then latchec
`by the data line restore clock signal DLEQ going high, an
`is applied immediately after the signal DLEQ goes low.
`Using this process, the lines DL1, DL2, DLL1, DLL2, I01
`and I02 are used for both read and write operations. This
`technique thus avoids the need for additional
`lines tha
`would otherwise be required for write operations and which
`would consequently require more wiring, more contro
`logic, and greater surface area.
`In summary, the key aspects of the invention are that the
`circuit accomplishes a high performance random read/write
`SDRAM design by synchronizing the read and write opera-
`tions at the data line sense amplifier. This enables the design
`to perform random read and write operations without vary-
`ing cycle time issues or unbalanced margin issues. The
`invention also uses the data lines as bi-directional lines to
`accomplish high performance reads and writes with minimal
`additional wiring overhead to the logic and wiring already
`used for the read case. This design enables a single clock '
`timing flow for both reads and writes which is the basis for
`the balanced margins for reads and writes.
`While the preferred embodiment of the invention has been
`illustrated and described, it will be appreciated that various
`changes can be made therein without departing from the ‘
`spirit and scope of the invention.
`The embodiments of the invention in which an exclusive
`property or privilege is claimed are defined as follows:
`1. A semiconductor memory device for storing data, the
`semiconductor memory device comprising:
`a memory where data signals are stored;
`an input/output port for writing and reading data signals
`to and from the semiconductor memory device;
`pairs of data lines in series for passing data signals from
`the memory to the input/output port, the same pairs of
`data lines that are used during a read operation to pass
`data signals from the memory to the input/output port
`also being used during a write operation to pass data
`signals from the input/output port to the memory;
`a timing logic circuit, the timing logic circuit controlling
`the timing cycles of when data signals are passed to and
`
`16
`from each of the pairs of data lines during the read
`operation,
`the timing logic circuit during the write
`operation disabling all of the timing cycles for all of the
`pairs ofdata lines except the pair closest to the memory
`so that write data may be overdriven onto the pairs of
`data lines without concern for the normal timing cycles
`for those data lines, the write data being transferred
`during the write operation to the pair of data lines
`close st to the memory for which the timing cycle is still
`active at approximately the same point during the
`timing cycle that the read data is transferred during the
`read operation.
`2. The semiconductor memory device of claim 1, further
`comprising:
`read circuitry coupled between the consecutive pairs of
`data lines, the read circuitry being used during the read
`operation to perform amplifying, isolating, latching, or
`driving functions with regard to the data signals; and
`pairs of bypass lines coupled between the consecutive
`pairs of data lines for bypassing the read circuitry
`during the write operation.
`3. The semiconductor memory device of claim 2, wherein
`the read circuitry includes read drivers for driving data
`signals onto a first pair of data lines during the read
`operation.
`4. The semiconductor memory device of claim 3 further
`comprising write drivers for driving data signals to a second
`pair of data lines during the write operation, wherein at least
`one pair of bypass lines is coupled to a write driver.
`5. The semiconductor memory device of claim 2, wherein
`the read circuitry includes a latch for latching the data
`signals during the read operation.
`6. The semiconductor memory device of claim 5, wherein
`the read circuitry includes an isolation circuit for isolating
`the latch from one of the pairs of data lines.
`7. The semiconductor memory device of claim 1, further
`comprising equalization circuits being controlled by equal-
`ization signals to reset the voltage on the data lines during
`each of the timing cycles for the data lines.
`8. The memory device of claim 7, wherein the equaliza-
`tion circuits are coupled between each of the data lines in
`each pair of data lines.
`9. The memory device of claim 7, wherein the equaliza-
`tion circuits bring each of the data lines in the respective
`pairs of data lines to a common mid—level Voltage.
`10. The semiconductor memory device of claim 7, further
`comprising read and write data latches coupled to a first pair
`of data lines for latching data signals on the data lines, the
`timing for the data latch being controlled such that data is
`latched by the equalization signal so that the read or write
`operation is rolled into the beginning of the next timing
`cycle for the first pair of data lines, so that
`the active
`read/write time is increased and the latching time is reduced.
`11. The semiconductor memory device of claim 4,
`wherein the bypass lines coupled to the pair of data lines that
`is second closest to the memory include a write data latch for
`latching write data during the write operation.
`12. The semiconductor memory device of claim 11,
`wherein the bypass lines coupled to the pair of data lines that
`is second closest to the memory include an isolation circuit
`that couples the write data latch to the pair of data lines that
`is second closest to the memory.
`13. The semiconductor memory device of claim 4,
`wherein the bypass lines that are coupled to the pair of data
`lines that is closest to the memory include an isolation circuit
`for isolating the pair of data lines that is closest to the
`memory from the write drivers of the bypass lines.
`
`Page 21 of 22
`
`
`
`6,052,328
`
`17
`14. Asemiconductor memory device for storing data, the
`semiconductor memory device comprising:
`a memory where data signals are stored;
`an input/output port for writing and reading data signals
`to and from the semiconductor memory device;
`pairs of data lines in series for passing data signals from
`the memory to the input/output port, the same pairs of
`data lines that are used during a read operation to pass
`data signals from the memory to the input/output port
`also being used during a write operation to pass data
`signals from the input/output port to the memory;
`read circuitry coupled between at
`least
`two pairs of
`consecutive data lines for performing amplifying,
`isolating, latching, or driving functions with respect to
`the data signals;
`pairs of bypass lines coupled between pairs of consecutive
`data lines for selectively bypassing the read circuitry
`during the write operation; and
`a write data latch being coupled to at least one ofthe pairs
`of bypass lines for latching write data during he write
`operation.
`15. The semiconductor memory device of c aim 14,
`wherein the read circuitry includes read drivers for driving
`data signals onto a pair of data lines during the read
`operation.
`16. The semiconductor memory device of c aim 14,
`further comprising write drivers for driving data signals to a
`pair of data lines during the write operation, wherein at least
`one of the pair of bypass lines is coupled to a wri e driver.
`17. Asemiconductor memory device of claim 14, wherein
`the read circuitry includes a latch for latching the data
`signals during the read operation.
`18. The semiconductor memory device of c aim 17,
`wherein the read circuitry includes an isolation circuit for
`isolating the latch from one of the pairs of data lines.
`19. The semiconductor memory device of c aim 14,
`further comprising equalization circuits being controlled by
`equalization signals to reset the voltage on the data lines
`during each of the timing cycles for the data lines.
`20. The semiconductor memory device of c aim 19,
`wherein the equalization circuits are coupled between each
`of the data lines in each pair of data lines.
`21. A semiconductor memory device for storing data;
`the semiconductor memory device comprising:
`a memory for storing data signals;
`an input/output port for inputting and outputting data
`signals to and from the semiconductor memory
`
`18
`device, the data signals being output from the semi-
`conductor memory device during a read operation
`and being input
`into the semiconductor memory
`device during a write operation;
`clock circuitry for generating clock signals for control-
`ling the timing of the read and write operations;
`pairs of data lines in series for carrying complementary
`data signals between the memory and the inp11t/
`output port of the semiconductor memory device;
`a
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