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`PTOi‘SEi’SB (DE-09]
`Approved for use through 03252013 OMB 0651-0064
`U 3 Patent and Trademark Office: US. DEPARTMENT OF COMMERCE
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`rted to as FORM PTO—1 I165]
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` REQUEST FOR INTER PARTES REEXAMINATION TRANSMITTAL FORM
`
`
`ADD [255 102
`
`
`
`
`
`
`
`
`Mail Stop inter Fortes Reexarn
`commissioner for Patents
`
`Po. Box 1450
`Alexandria. VA 22313-1450
`
`Attorney Docket No; 19958-0006RX1
`
`Date: January 19. 2012
`
`[JIM
`
`UT”-
`
`l'.J-'.‘,’.'.I
`
`6.366.130
`This is a request for iriterpartes reexamination pursuant to 3? CFR 1.913 of patent number
`issued Apr” 2' 2002
`. The request is made by a third party requester. identified herein below.
`
`1.
`
`2'.
`
`
`
`
`a. The name and address of the person requesting reexamination is:
`W. Karl Renner
`
`
`Fish & Richardson RC.
`
`
`
`1425 K St, NW #1100, Washington, DC 20005
` b. The real party in interest {37 cm 1.91502in .5: Hynix Semiconductor Inc.
`
`
`
`
`3. D a.
`A check In the amount of 5
`is enclosed to cover the reexamination fee. 37 CFR 120(c)(2).
`
`
` D c.
`
`credit to Deposit Account No. 064050
`IE Any refund should be made by D check or
` 4.
`
`
`37 CFR 1.26m). If payment is made by credit card. relund musl be to credit card account.
` 5.
`
`
` 6. E] CD-ROM or CD-R in duplicate, Computer Program (Appendix) or large table
`
`
`|:| Lands-ape Table on CD
`
`o.
`
`The Director is hereby authorized to charge the fee as set forth in 37 CFR 120(c)(2)
`lo Deposit Account No. 05‘1 050
`'. or
`
`Payment by credit card. Form PTO-2033 is attached.
`
`A copy ofthe patent to be reexamined having a double column format on one side of a separate paper is
`enclosed. 37 CFR 1.915(b)(5)
`
`7.
`
`
`
`|:] Nucleotide andfor Amino Acid Sequence Submission
`if applicable, items a. - c. are required.
`
`
`
`
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`
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`a. C] Computer Readable Form (CRF)
`b. Specification Sequence Listing on:
`i.
`[3 CD-ROM (2 copies) or CD-R {2 copies}; or
`ii. El paper
`
`
`
`
`0. D Statements verifying identity of above copies
`
`
`
` a. D A copy of any disclaimer. Del'liflcaIE‘. of correction or reexamination certificate issued in the patent is included.
`Reexamination ofclaim(s] 1‘3 and 5'7
`is requested.
` 9.
`
` 1t‘.l.
`
`
`A copy of every patent or printed publication relied upon is submitted herewith including a listing thereof on
`Form PTOISBIOB. PTO-1449, or equivalent.
` 11. D An English language translation of all necessary and pertinent non-Engiish language patents andlor printed
`publications is included.
`[Pa e 1 of 2]
`This collection at information is requlred by 37 CFR 1.9!5. The Inlonnalion is lgflulfefl to obtain or retain a benefit by the public which is to file (and by the USPTD to
`process] an application. Confidentiality is governed by 35 use. in and 3? CFR 1.11 and L14. This collection is estimated to latte 13 minutes to complete,
`including
`gathering. preparing. and submitting the completed application loan to the USPTO. Tlrno wilt vary depending upon the individual case. Any comments on the amount
`at time you require to complete this form ahdi'ur suggestions for reducing this burden. should be sent to the Chiel Information Officer. US. Patent and trademark
`Olllcel US. Department at Commerce. P.D. Bolt 1450. Alexandria. VA 22313-1450 DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND
`TO: Mail Stop inter Fortes Reoxarni Commissioner for Patents, P.O. Box 1450. Alexandria, VA 22313-1450.
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`approved for use through 0212311013. OMB 0651-0054
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`Under the Paperwork Reduction Act at 1995. no persons are required to respond to a collection at information unless it displays a valid OMB control number.
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`12.
`
`The attached detailed request includes at least the lollowing items:
`
`a. A statement identifying each substantial new question of patentability based on prior patents and printed
`publications. 37 CFR 1.915ib)[3)
`b. An identification of every claim for which reexamination is requested. and a detailed explanation of the pertinency
`and manner of applying the cited art to every claim for which reexamination is requested. 3? CFR 1.915(b}(1} a (3).
`
`It is certified that the estoppei provisions of 37 CFR 1.90? do not prohibit this reexamination 37 CFR 1.915(b)(7)
`
`a.
`
`it is certified that a copy of this request has been served in its entirely on the patent owner as provided in
`3? CFR 1733(c)7
`The name and address of the party served and the date of service are:
`KILPATRICK TOWNSEND & STOCKTON LLF'
`
`13.
`
`14.
`
`TWO EMBARCADERO CENTER. 8TH FLOOR
`
`SAN FRANCISCO. CA 94111
`
`Date of Service:
`
`'. or
`January 19, 2012
`
`D b. A duplicate copy is enclosed because service on patent owner was not possible. An explanation of the efforts
`made to serve patent owner is attached. See MPEP 2620.
`
`15. Third Party Requester Correspondence Address: Direct all communications about the reexamination to:
`
`The address associated with Customer Number:
`
`25171
`
`OR
`
`E]
`
`Firm or
`Individual Name
`
`
`
`
`
`Telephone
`
`
`
`15. [:1 The patent is currently the subject ofthe following concurrent prooeedingts):
`a. Copending reissue Application No.
`
`b. Copending reexamination Control No.
`
`c. Cope-riding Interference No.
`d . Copending litigation styled:
`Cascades Computer Innovation. LLC v. Hynix Semiconductor
`inc. in US Dist Court Northern Dist of IL Case-ll 1:11-cv—04356
`
`
`
`WARNING: Information on this term may become public- Credit card information should not be
`inctud d on this form. Provide credit card information and authorization on PTO-2038.
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`W 011192012
`
`Authorized Signature
`W. Karl Renner
`
`Date
`41265
`
`Typedi'Printed Name
`
`Registration No., if applicable
`
`[Page 2 of 2]
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`Page 2 of 144
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`Page 2 of 144
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`

`

`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Reexamination Request for
`U.S. Patent No. 6,366,130
`
`In re Patent to Podlesny, et al.
`
`US. Patent No; 6,366,130
`Issued: April 2, 2002
`
`Serial No.: 09/505,656
`Filed: February 17, 2000
`
`For: HIGH SPEED LOW POWER DATA
`TRANSFER SCHEME
`
`Mail Stop Inter Panes Reexam
`Commissioner for Patents
`PD. Box 1450
`
`Alexandria, VA 22313-1450
`
`UVUM—JVNJVUUV
`
`REQUEST FOR INTER PARTES REEXAMINATION UNDER 35 U.S.C. §§ 302 and
`31] AND 3"! C.F.R. § 1.902 et seq.
`
`***REEXAMINATION REQUEST FOR PATENT ASSERTED IN LITIGATION***
`
`Page 3 of 144
`
`Page 3 of 144
`
`

`

`Reexamination Request for
`US. Patent No. 6,366,130
`
`TABLE OF CONTENTS
`
`OVERVIEW OF APPENDICES ........................................................ . .........................................3
`
`I.
`
`II.
`
`INTRODUCTION .............................................................................................................. 4
`
`IDENTIFICATION OF PATENT AND CLAIMS, AND REAL PARTY IN
`INTEREST OIIUI'IIIIIOIIIOOQIDIIIIIlllflillllliIIICIOI‘...'..'I.I'"-."'l..|.'IC'I'IIl"..l|'|"lllllIIll-IIIIIIIIOIIIIOIIOQIIOIUIIG
`
`III.
`
`LITIGATION INVOLVING THE ’130 PATENT .........................................................6
`
`IV.
`
`CLAIMS FOR WHICH REEXAMINATION IS REQUESTED AND PRIOR ART
`REFERENCES APPLIED ................................................................................................6
`
`V.
`
`OVERVIEW OF THE GROUNDS OF UNPATENTABILITY‘7
`
`VI.
`
`THERE IS A REASONABLE LIKELIHOOD THAT THE REQUESTER WILL
`PREVAIL WITH RESPECT TO THE CLAIMS CHALLENGED ........................... 11
`
`A.
`
`B.
`
`C.
`
`HARDEE ...................................................................................... I
`
`l
`
`FUJII ............................................................................................. 13
`
`KOYANAGI ................................................................................. 15
`
`VII. MANNER OF APPLYING CITED PRIOR ART TO EVERY CLAIM FOR
`
`WHICH REEXAMINATION IS REQUESTED .......................................................... 17
`
`A.
`
`B.
`
`C.
`
`HARDEE ...................................................................................... 18
`
`FUJII ............................................................................................. 31
`
`KOYANAGI ................................................................................. 44
`
`VIII. SUMMARY OF GROUNDS FOR UNPATENTABILITY ......................................... 55
`
`2
`
`Page 4 of 144
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`Page 4 of 144
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`

`

`OVERVIEW OF APPENDICES
`
`Reexamination Request for
`US. Patent No. 6,366,| 30
`
`Appendix A;
`
`[1.5. Patent No. 6,366,130 to Podlesny (hereinafter “Podlcsny")
`
`Appendix Bl: Complaints from Pending Litigations involving US. Patent No. 6,366,} 30
`
`Appendix B2: Select Excerpts from Prosecution History of US. Patent No. 6,366,l30
`
`Appendix C: European Patent No 0 597 231 to Hardee (hereinafter “Hardee")
`
`Appendix D: US. Patent No‘ 5,274,598 to F ujii (hereinafter “Fujii")
`
`Appendix E: U.S. Patent No. 5,659,512 to Koyanagi (hereinafter “Koyanagi")
`
`Appendix F:
`
`IDS Form PTO/SB/OS
`
`Page 5 of 144
`
`Page 5 of 144
`
`

`

`Reexamination Request for
`U.S. Patent No. 6,366,130
`
`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. §§ 302 and 311 and 37 C.F.R. § 1.902 et seq, interpartes
`
`reexamination is requested for U.S. Patent No. 6,366,130 (“the ‘ 130 patent"). A copy ofthe ‘ 130
`
`patent is attached in Appendix A.
`
`Requestor is aware ofone presently-pending proceeding in the United States District
`
`Court fer the Northern District of Illinois, in which the ’ I 30 patent has been asserted. Section ll]
`
`of this request provides further detail on the pending litigation involving the ’130 patent.
`
`In view
`
`of the current litigation, special dispatch pursuant to 35 U.S.C. §§ 314 is respectfully requested
`
`to expedite the handling of this request and for any subsequent reexamination proceedings.
`
`Requester is not aware of any reexamination certificates that have issued for the '130
`
`patent. The ’ I30 patent is not subject to a terminal disclaimer.
`
`In accordance with 37 C.F.R. § 1.915, as modified by The Leahy—Smith America lnvents
`
`Act {HR 1249, pp.l6—20; Federal Register, Vol. 76, No. lSS, pp.59055-58), this Request includes
`
`the following;
`
`1.
`
`an identification of the patent by patent number and every claim for which
`
`reexamination is requested (Section ll);
`
`2.
`
`a citation of the patents and printed publications which are presented to provide a
`
`showing that there is a reasonable likelihood that the requester will prevail with
`
`reSpect to at least one of the claims challenged in the request (Section IV);
`
`3.
`
`a statement pointing out, based on the cited patents and printed publications, each
`
`showing of a reasonable likelihood that the requester will prevail with respect to at
`
`least one of the claims challenged in the request, and a detailed explanation of the
`
`pertinence and manner of applying the patents and printed publications to every claim
`
`for which reexamination is requested (Sections VI and VII);
`
`4.
`
`a copy of every patent or printed publication relied upon or referred to in paragraphs
`
`(1) through (3) above, accompanied by an English language translation ofall the
`
`Page 6 of 144
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`Page 6 of 144
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`

`

`Reexamination Request for
`US. Patent No. 6,366,130
`
`necessary and pertinent parts of any non—English language document (Appendices C-
`
`E);
`
`a copy of the entire patent including the front face, drawings, and specification/claims
`
`(in double column format) for which reexamination is requested, and a copy of any
`
`disclaimer, certificate of correction, or reexamination certificate issued in the patent
`
`(Appendix A);
`
`a certification by the third party requester that a copy of the request has been served
`
`in its entirety on the patent owner at the address provided for in § l.33(c)
`
`(Certification Following Signature Page);
`
`a certification by the third party requester that the estoppel provisions of§ l.907 do
`
`not prohibit the inter partes reexamination [Section Ii); and
`
`a statement identifying the real party in interest to the extent necessary for a
`
`subsequent person filing an inter partes reexamination request to determine whether
`
`that person is a privy (Section 1!).
`
`The Director is hereby authorized to charge payment in the amount of $8,800 for the inter
`
`partes reexamination fee specified by 37 C.F.R. § 120(c)(2) to Deposit Account 06-1050.
`
`Page 7 of 144
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`Page 7 of 144
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`

`

`
`
`Reexamination Request for
`US. Patent No. 6,366,130
`
`II.
`
`IDENTIFICATION OF PATENT AND CLAIMS, AND REAL PARTY IN
`INTEREST
`
`In accordance with 37 CPR. § 1.915(1))“ ), (b)(7'), and (b)(8), requester Hynix
`
`Semiconductor Inc. (“Hynix" or “‘Requester“) requests interpartes reexamination of claims l-3
`
`and 5—7 ofthe ’130 patent, assigned to Elbrus International Limited, Cayman Islands {“Elbrus”)l.
`
`Requester certifies that the estoppel provisions of 37 C.F.R. § 1.90? do not prohibit this inter
`
`panes reexamination.
`
`As explained below, claims I-3 and 5-7 are unpatentable over the prior art patents and
`
`publications identified and applied in this Request. The patents and printed publications relied
`
`upon in this request, and the manner in which they are applied to the claims, present substantial
`
`new questions of patentability and show a reasonable likelihood that the Requester will prevail
`
`with respect to the claims challenged in the Request.
`
`III.
`
`LITIGATION INVOLVING THE ‘130 PATENT
`
`The ‘130 patent is the subject of pending litigation.
`
`In particular, Cascades Computer
`
`Innovation, LLC (“Cascades") has asserted the ‘ 130 patent against Hynix Semiconductor Inc. in
`
`the United States District Court for the Northern District of Illinois, Case No. 1:] Lev-04356.
`
`No other parties were named as co-defendants. Hynix has waived service of the complaint and
`
`its answer is due on January 19, 2012. A copy of the complaint is included in Appendix BI.
`
`IV.
`
`CLAIMS FOR WHICH REEXAMINATION IS REQUESTED AND PRIOR
`ART REFERENCES APPLIED
`
`Reexamination is requested for claims 1-3 and 5-7 ofthe “130 patent in view ofthe
`
`following art:
`
`1. European Patent Publication No. 0 S97 23] to Hardee (coPy provided in Appendix C)
`(hereinafter “Hardee”);
`
`' Assignee listed on the US 6,366,l30 patent: Elbrus International Limited, George Town Grand Cayman (KY).
`Appendix A at page It Assignee listed on the USPTO Assignment Database: Elhrus International Limited. PO.
`BOX 265. George Town Grand Cayman, Cayman Island.
`In the Complaint for Patent Infringement, the plaintiff,
`Cascades Computer Innovation LLC stated that “Cascades owns the exclusive license and right to sue for past.
`present and future infringement oflhe '130 patent." Appendix BI at page 2.
`
`Page 8 of 144
`
`Page 8 of 144
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`

`

`Reexamination Request for
`U.S. Patent No. 6,366,130
`
`2. U.S. Patent No. 5,274,598 to Fujii (copy provided in Appendix D) (hereinafter
`“Fujii”); and
`
`3. U.S. Patent No. 5,659,512 to Koyanagi (copy provided in Appendix E) (hereinafter
`“Koyanagi”).
`
`Each of the above references is listed on IDS Form PTOISB/OS provided in Appendix F.
`
`These references independently qualify as prior an under 35 U.S.C. § 102. Specifically,
`
`Hardee qualifies as prior art under 35 U.S.C. § 102(b) because Hardee issued was published on
`
`May 18, 1994, which is more than one year prior to the earliest possible effective February 17.
`
`I999 filing date ofthe ‘130 patent.
`
`Fujii qualifies as prior an under 35 U.S.C. § 102(b) because Fujii issued as a patent on
`
`December 28, 1993, which is more than one year prior to the earliest possible effective February
`
`17, W99 filing date ofthe ’130 patent.
`
`Koyanagi qualifies as prior an under 35 U.S.C. § 102(b) because Koyanagi issued as a
`
`patent on August 19, 1997, which is more than one year prior to the earliest possible effective
`
`February 17, 1999 filing date ofthc ’130 patent.
`
`None of the references were considered during prosecution of the ‘130 patent.
`
`V.
`
`OVERVIEW OF THE GROUNDS OF UNPATENTABILITY
`
`The ’ 130 patent is directed to an electronic circuit configured to enable data transfer with
`
`relatively high speed and low power consumption.
`
`‘130 patent at 2:34-38. The ‘130 patent
`
`attributes its improved speed and power characteristics to pro-charging of a differential bus and a
`
`differential data bus. Specifically, data buses are pre-charged to voltage levels prior to data
`
`transfer operations. Then, when data transfer is desired, the pre-charged voltage levels on
`
`opposing differential buses are each changed in the opposite manner, yielding a differential
`
`voltage level that represents data to be transferred.
`
`[n this process, relatively modest voltage
`
`level changes are quickly and efficiently imparted on each data bus, with the resulting opposite
`
`but marginal changes reflecting a difl'erential of sufficient magnitude to yield perceptible and
`
`transferable data.
`
`Against this backdrop, the basic concept of pre—charging bus lines was itself recited by
`
`claims of the ’130 patent- This feature was highlighted by applicants during original prosecution
`
`when seeking to distinguish prior art, and indeed, it was relied upon by that original Examiner as
`
`Page 9 of 144
`
`Page 9 of 144
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`

`

`Reexamination Request for
`U.S. Patent No. 6,366,130
`
`the sole basis for allowing the claims of the ”130 patent. Appendix 132 at page 24, Notice of
`
`Allowance mailed in Application No. 09/505,656 on February 22, 2001.
`
`Below, additional details are provided regarding structure and function disclosed by the
`
`‘ 130 patent, with reference to its specification and figures, despite the fact that claims of the
`
`patent were allowed based on pre-charging of the data buses alone.
`
`Structurally, the ’130 patent usesjust two figures to illustrate an electronic circuit
`
`responsible for the pre—charging and claimed functionality. FIG. 1 provides an overview of the
`
`complete electronic circuit, and FIG. 2 shows details relating to a particular aspect of FIG. l,
`
`namer its sensing amplifier element 16. Below, FIG.
`
`1 is reproduced for convenient visual
`
`reference.
`
`
`
`Busdrivers Prccharge Bus lines Bus recicver
`circuit
`
`FIGJ.
`
`As indicated by labels applied on the bottom of the drawing itself, FIG.
`
`1 shows bus
`
`drivers, a precharge circuitfsource= and bus lines (i.e., a differential bus) coupled to the bus
`
`drivers and to the voltage precharge circuit/source. Also coupled to the bus lines is a latching
`
`Page 10 of 144
`
`Page 10 of 144
`
`

`

`sense amplifier 16, the contemplated details of which are illustrated by FIG. 2, reproduced
`
`below.
`
`Reexamination Request for
`US. Patent No. 6,366,130
`
`
`
`V53
`
`no.2.
`
`16
`
`in particular, in FIG. 2, latching sense amplifier 16 is shown to include a cross-coupled
`
`latch having internal nodes IT and IC coupled to differential data buses, and complementary
`
`outputs QT and QC.
`
`Functionally, two phases of operation are describe for the bus driver circuit of FIG. I, and
`
`two analogous but opposite phases ofoperation for the sense amplifier shown by FIG. 2. With
`
`respect to each, the two phases is identified as (l) a bus precharge phase and (2) a data transfer
`
`phase, but as indicated, they are oppositefoffset to promote data propagation through the circuit,
`
`Below, the phases are described, first with respect to components ofthe bus driver circuit shown
`
`in FIG.
`
`1 and then with respect to components ofthe sense amplifier shown by FIG. 2.
`
`During the precharge phase of the bus driver circuit shown by FIG. 1:
`
`[tjhe true phase driver on transistors 20 and 2] and the complement phase driver
`on transistors 22 and 23 are in high impedance state and both bus lines are
`equalized and precharged to a potential Vpr (buses precharging voltage level)
`through the turned on transistors 24, 25 and 26.
`’ 130 patent at 2: 1 8-22.
`
`Thereafter, during the data transfer phase of the bus driver circuit shown by FIG. 1:
`
`[o]ne of the drivers is pulled up and charges the appropriate bus line from the
`precharged level Vpr toward a more positive Vdd - Vt (where Vt is the threshold
`voltage ofthe pull up NMOS transistor ofthe driver). At the same time, the other
`driver is pulled down and discharges the opposite bus line from the precharged
`
`Page 11 of 144
`
`Page 11 of 144
`
`

`

`Reexamination Request for
`U.S. Patent No. 6,366,130
`
`level Vpr towards a more negative level Vss (ground). This provides a differential
`voltage: +dV and -dV from the precharging level Vpr between true and
`complement bus lines. 1d. at 2:25-33.
`
`During the precharge phase of the sense amplifier circuit shown by FIG. 2 (which occurs
`
`when the bus driver circuit is operating in its data transfer phase), the control input CLK is low,
`
`such that the differential voltage on bus lines 14 and 15:
`
`passes to the internal nodes IT (positive binary single-rail internal point of the
`sensing amplifier) and [C (negative binary single-rail data input phase internal 55
`point of the sensing amplifier) of the latched amplifier. The output nodes of both
`dynamic gates are precharged to Vdd and the complementary outputs QT (true
`phase of dual-rail data output signal) and QC (complement phase of dual-rail
`output data signal) ofthe sensing amplifier become high. Id. at 2:52-59.
`
`And, during the data transfer phase of the sense amplifier circuit shown by FIG. 2 (which
`
`occurs when the bus driver circuit is operating in its precharge phase), the control input CLK is
`
`high, such that the differential voltage passed to the internal nodes IT and 1C is received and
`
`passed by the cross-coupled amplifier
`
`to power buses (transistors 30 and 31 are turned on) and [the cross-coupled
`amplifier] begins to amplify the low voltage swings of the internal nodes IT and
`1C to full logic levels. The output node of one of the dynamic gates is discharged
`to ground and the appropriate output QT or QC of the sensing amplifier becomes
`low. Id. at 2:64-33.
`
`During original prosecution, the handling Examiner rejected the original claims based on
`
`U.S. Patent No. 5,598,371 (“Lee”) in view of U.S. Patent No. 6,184,722 (“Hayakawa”).
`
`Indeed,
`
`allowance was not secured until applicants amended the claims to recite pre—charging of bus
`
`lines, nor until they presented arguments suggesting that this general concept was missing from
`
`within the prior art. The Examiner‘s reasons for allowance, reproduced below, make clear that
`
`allowance was secured on this basis alone:
`
`applicants‘ arguments have been fully considered and deemed to be persuasive.
`The present invention teaches precharging the buses to a specific level between
`ground and Vdd, which results in equal, low differential Voltage swings,
`providing increased speed of data transfer. The prior art of Lee et al. does not
`teach such precharging buses as described above. Appendix BE at page 24. Notice
`of Allowance mailed in Application No. 092501656 on February 22, 2001.
`
`Despite the Examiner's determination that these features are absent from the prior art, a
`
`close inspection reveals that these features relate to very basic differential voltage amplification
`
`techniques that have been well-known among engineers designing sensing amplifier circuits for
`
`memory systems.
`
`10
`
`Page 12 of 144
`
`Page 12 of 144
`
`

`

`Reexamination Request for
`US. Patent No. 6,366,130
`
`Because these features were well-known prior to the ‘ 130 patent, as demonstrated by the
`
`references applied in this Request, which Show the features ofclaims l-3 and 5-7 ofthe ’ 130
`
`patent, Requester requests reexamination of the ’130 patent and cancellation of the challenged
`
`claims.
`
`V1.
`
`THERE IS A REASONABLE LIKELIHOOD THAT THE REQUESTER WILL
`PREVAIL WITH RESPECT TO THE CLAIMS CHALLENGED
`
`The legal standard for ordering inter partes reexamination was recently modified by The
`
`Leahy—Smith America Invents Act. See HR 1249, pp.16-20; Federal Register, Vol. 76, No. 185,
`
`pp.59055-58). An inter partes reexamination should be granted when there is a showing that
`
`there is a reasonable likelihood that the requester will prevail with respect to at least one of the
`
`claims challenged in the request (the “reasonable likelihood” standard). This standard replaced
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`the previously applicable “substantial new question of patentability" standard. Regardless of
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`how this new controlling standard is interpreted and applied in the courts and the Office, the
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`instant Request is sufficient to justify reexamination.
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`Indeed, the grounds of rejection proposed
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`by this Request are based on patents and printed publications and they raise substantial new
`questions ofpatentability that are reasonably likely to be upheld against the claims being
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`challenged.
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`Below, Requester sets forth proposed grounds for rejection of claims l-3 and 5—7 of the
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`‘130 patent, demonstrating why the prior art applied in the proposed grounds are reasonably
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`likely to be adopted and sustained against these claims. Because none of the references applied
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`in this request were considered during prosecution ofthe ’130 patent. they also raise substantial
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`new questions of patentability with respect to claims 1-3 and 5-7 ofthe ’130 patent.
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`A.
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`HARDEE
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`Hardee describes a memory circuit that amplifies a voltage difference between two
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`precharged data buses during a write operation.
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`In this manner, Hardee contemplates the concept
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`of precharging differential buses that was deemed sufficient to justify allowance of the ‘130
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`patent claims.
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`Structurally, the Hardee memory circuit as shown in FIG. 8 represents one of many
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`columns in a memory system, where the YW signal selects the column of memory circuit to be
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`written. The true and complement data input signals are DW and DWB, respectively, and the
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`l |
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`Page 13 of 144
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`Reexamination Request for
`US. Patent No. 6,366,130
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`true and complement data output signals are BIT L and BIT BL, respectively, which lead to a
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`memory cell. As shown in representative FIG. 8 reproduced below, the Hardee memory circuit
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`includes a precharge source BLREF, a precharge circuit as enclosed in the dashedvdotted box,
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`two bus drivers as enclosed in the dashed boxes, :1 cross-latched sense amplifier, and isolation
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`transistors 232 and 234.
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`
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`L~(V55J
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`III-IIIIIiII-I'
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`Functionally, prior to writing the memory cell on a column, both DW and DWB are
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`disabled. The YW signal is enabled, resulting in the DW Local and DWB Local bit lines being
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`coupled to the data lines 158 and 160, respectively. Upon activating precharge circuit and the
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`isolation transistors 232 and 234, the DW Local and DWB Local bit lines and the data lines 153
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`and 160 are precharged to a voltage BLREF, which is illustratively a constant voltage of V: VCC.
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`Hardee at 13:17-19. The precharged lines are then isolated by turning offthe isolation
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`transistors.
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`To write the memory cell on the column, DW or DWB is enabled while YW remains
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`high, and a pair oftransistor gates 128/134 or 130/132 turn on. The DW Local and the DWB
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`Local bit lines experience a change in voltage, one bit line going high while the other bit line
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`goes low. The differential voltage then enables the cross-latched sense amplifier and drives one
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`ofthe data lines 158 or 160 to VCC and the other line to ground. Hardee at 13:43-53. The
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`isolation transistors 232 and 234 are compled to the output of the data lines 158 and 160, and
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`12
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`Reexamination Request for
`US. Patent No. 6,366,130
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`controlled to pass the voltage on the data lines 158 and 160 to the BIT L and BIT BL outputs
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`after the voltages have reached a steady state.
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`As described, Hardee discloses a scheme for precharging differential data line pairs to a
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`voltage of V: VCC, and amplifying a differential voltage across a differential data line pair when
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`writing data to a memory cell.
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`In doing so, Hardee discloses the features identified by the
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`Examiner asjustifying allowance of independent claim I. This and other teachings of Harder:
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`establish a substantial (and new) question of patentability, and they also establish a reasonable
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`likelihood that the requester will prevail with respect to at least independent claim 1.
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`B.
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`FUJll
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`Fujii describes a circuit configured to enable access to a memory circuit/cell. In doing so,
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`F ujii describes applying a charge to main and sub-bit data bus lines (i.e., precharging those bus
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`lines) before using those bus lines to read data from the memory circuitfcell.
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`in this manner,
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`Fujii also contemplates the concept of precharging differential buses, which was deemed
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`sufficient to justify allowance of the ”130 patent claims.
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`Structurally, with reference to FIG. 3 of Fujii, reproduced below, there exist several
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`selectable memory circuits (MCs) in a memory array. Each memory circuit (MC) includes a true
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`and complement sub-bit line (SB and E) used to read data from within the memory cell (MC).
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`When selected, the sub—bit lines SBil-SE for a particular memory circuit (i) may be used to
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`communicate data from within that memory cell to main data lines (MB and W), which yield
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`memory contents through their connection at output buses U0 and 36.1mportantly, a precharge
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`source HVC and a precharge circuit 5 are configured to work together to precharge main data
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`line pair MB and fig and sub-bit lines SENS—ii. Also bus drivers (enclosed in the dashed-dotted
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`boxes), a main cross—latched sense amplifier 1, and isolation transistors Qv and Q1 are
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`configured to facilitate flow of precharge voltage and data toffrom sub-bit data lines (SB and
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`ea).
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`13
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`Reexamination Request for
`US. Patent No. 6,366,|30
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`SSEPi
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`SSENi
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`SSEP]
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`SSElli
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`
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`no WE wet on tron:
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`FIG. 3mm Al"
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`Functionally, the sub—bit line selection signal 531 is enabled when access is desired to
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`data within a corresponding a memory cell MC. Responsively, the main data line pair MB and
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`W are coupled to the sub-bit line pair SBi and E, where the index “i" corre5ponds to one of
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`the several sub—bit line pairs able to be connected to the main data line pair, namely, the sub-bit
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`line pair canesponding to the sub-bit line selection signal SSi.
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`To enable ready access to data from within the memory cell MC, the sub-bit lines (SBi
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`and E) and the data lines (MB and We?) are each prechargedz, by disabling the word select
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`signal WL while enabling the precharge control signal PDL and the sub-bit line selection signal
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`SSi. The precharged main and sub-hit lines are thereafter isolated from the precharge source by
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`disabling the precharge control signal PDL, and they are isolated from each other by disabling
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`the sub-bit line selection signal SSi. Fujii at 2:53-56.
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`The precharged sub-bit line SBi then accesses the data from the memory cell MC by
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`enabling the word select signal WL, enabling the precharged sub-bit line SBi to experience a
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`change in voltage reflective of the memory cell MC data contents/charge. Moreover, this change
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`in voltage is experienced in the opposite direction on the complement sub-bit line 'S_B'_1 by
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`controlling the driver control signals SSEPi and SSENi. Fujii at 2:56-64.
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`Ultimately, the sub—bit line selection signal SSi is again enabled to connect the main data
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`line pair MB and W to the sub-bit line pair SBi and S—B'i, and using the main sense amplifier
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`2 Fujii discloses "[t]he main bit lines and the sub—bit lines are set at the V: Vcc level of the pre-eharge level." Fujii at
`2:4849.
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`14
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`Reexaminatiou Request for
`1.1.3. Patent No. 6,366,130
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`activation signals MSEP and MSEN, the differential voltage at the sub-bit line pair SBi and E
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`is passed to the main data line pair MB and W. Fujii 2:60-35.
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`The two isolation transistors, both identified as Qv_ are coupled to the output of the main
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`data lines MB or m, and used to control passage of the voltages on the main'data lines MB and
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`m to the output buses [/0 and E after those voltages have reached a steady state.
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`As described, Fujii discloses a sensing amplifier circuit that precharges the main and sub-
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`bit (differential) data lines to a voltage of V; VCC.
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`In doing so, Fujii discloses the features
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`identified by the Examiner as justifying allowance of independent claim I, establishing a
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`substantial (and new) question of patentability, and also establishing a reasonable likelihood that
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`the requester will prevail with respect to at least independent claim I.
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`C.
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`KOYANAGI
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`Koyanagi describes a circuit configured to enable data to be read from a memory
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`circuitl’cell. Koyanagi, like other prior art described above, discloses precharging of differential
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`buses used to communicate the data from the memory cell to an output.
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`In particular, in the
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`following paragraphs, data line pairs DQI‘ DO and D/*D are each precharged.
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`In this manner,
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`Koyanagi contemplates the concept of prechargirtg differential buses that was deemed sufficient
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`tojustify allowance of the ’130 patent claims.
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`Structurally, and in accord with the FIG.
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`1 illustration of two memory circuits/cells in a
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`memory system/array, reproduced below, Koyanagi describes a da