Attomey Docket No.
`, Customer No. 20350
`Client Ref No.
`TOWNSEND and TOWNSEND and CREW LLP
`Two Embarcadero Center, 8 Floor
`r;
`-
`7
`7‘
`San Francisco, California 94111-3834
`(1'1 a? - - 1,. 9
`(415) 576-0200
`
`20181-5US
`PPA-S
`
`ASSISTANT COMMISSIONER FOR PATENTS
`BOX PATENT APPLICATION
`V '
`'
`.
`.
`‘ ashmgton, D C 202:"
`'5"
`0— 3
`fifio
`Hfi c
`QE‘.
`C:E 3”
`Des"— ,u
`Er“
`‘. 0
`Transmitted herewith for filing is the
`[ X ] patent application of
`
`lnventor(s).-'Applicant Identifier: Andrew V. Podlesny et a1.
`
`“Express Mail” Label No.
`EL394877883US
`
`Februa I 17 2000
`Date of Deposit:
`.
`.
`.
`.
`.
`.
`.
`l hereby certify that this is being deposrted With the United States
`Postal Service “Express Mail Post Office to Addressee” service
`under 37 CFR 1.10 on the dat
`' dicated above, addressedcto:
`
`.
`.
`.
`s §
`Asststant Comnnsstoner for
`nts
`“1‘0 E
`Washington, DC. 20231
`. §
`
`$8
`
`b
`3R§S
`Wm §w
`_u
`3‘9
`’7 §
`
`BY:
`
`This application claims priority from each of the following Application Nostfiling dates:
`60/120,53 l/Filed 2/ 17/99
`the disclosure(s) of which is (are) incorporated by reference.
`
`
`
`or: HIGH SPEED LOW POWER DATA TRANSFER SCHEME
`
`
`
`
`
`
`sheet(s) of [ ] formal [X] informal drawingts).
`1
`A[ ]signed [X] unsigned Declaration.
`A verified statement to establish small entity status under 37 CFR 1.9 and 37 CFR 127 [ X ] is enclosed [
`prior application and small entity status is still proper and desired.
`
`] was filed in the
`
`
`
`In view of the Unsigned Declaration as filed with this application and pursuant to 37 CFR §1.53(d),
`Applicant requests deferral of the filing fee until submission of the Missing Parts of Application.
`
`DO NQT CHARGE THE FILING FEE AT THIS THVIE.
`
`% 2: ”WM
`
`Kevin T. LeMond
`
`Telephone:
`(415) 576-0200
`
`Facsirnile:
`(415) 576—0300
`
`Reg No.1 35,933
`Attorneys for Applicant
`
`$F10'36480vl
`
`Page 1 of 97
`
`SAMSUNG EXHIBIT 1003
`
`

`

`VimiFIED STATEMENT (DECLARATION) CLAIMING SMALL ENTITY STATUS
`(37 CFR mm at l.27(c)) — SMALL BUSINESS CONCERN
`
`
`
`Attorney Docket 020181-000500US (PPA-S)
`
`nghfinmg Lay-[mtg Dag; [mfg]; 55mm];
`
`Applicant or Patentec:
`Application or Patent No.:
`Filed or Issued:
`Title:
`
`I hereby declare that I am:
`
`]
`[
`[It]
`
`the owner of the small business concern identified below
`an offictal of the small bustness concern empowered to act on behalf of the concern identified below
`
`Name of Small Business Concern:
`Address of Small Busmess Concern:
`
`Elbrus International Limited
`2.9. 139x 2§§
`Gegge Town Grand Cavmaril Camn Islands
`
`I hereby declare that the above—Identified small business concern qualifies as a small business concern as defined in 13 CFR 121.12, and reproduced in 37 CFR l.9(d),
`for purposes of paying reduced fees to the United States Patent and Trademark Office, In that the number of employees of the concern, including those of Its afl'tliates,
`does not exceed 500 persons. For purposes of this statement. (1) the number of employees of the busmess concern Is the average over the previous fiscal year of the
`concern ot the persons employed on a full-time, part-time or temporary basis during each of the pay periods of the fiscal year, and (2) concerns are affhates of each
`
`”other when either, directly or indirectly, one concem controls or has the power to control the other, or a third party or parties controls or has the power to control both
`£33
`fIIheI-eby declare that rights under contract or law have been conveyed to and remain with the small business concern identifed above with regard to the Invention,
`'Sehtitlcd High-Speed Low-Power Data Transfer Scheme by Inventor(s) Andrew V nglgny, Alexander V. Malshin and Alexander Y Solomatnikov described In:
`[X]
`the specification filed herewith;
`
`[ 1
`Application No.
`
`[
`]
`Patent No.
`
`
`
`filed
`issued
`
`;
`.
`
`'If the rights held by the above-identified small business concem are not exclusive, each Individual, concern or organization having rightsIn the invention is listed
`=below’ and no rights to the invention are held by any person, other than the inventor. who would not qualify as an independent inventor under 37 CFR 1.9(c) If that
`fpprson made the invention, or by any concern that would not qualify as a small business concern under 37 CFR 1 .9(d), or a nonprofit organization Imder 37 CFR l ..9(e)
`II;
`E. :
`‘2' 1
`
`*NOTE' Separate verified statements are required from each named person, mncem or organization havtng rights to the Invention avemng to their status as
`small entities. (37 CFR l.27)
`
`gfiame:ddress
`
`Name:
`Address:
`
`[
`
`] Individual
`
`[
`
`] Small Business Concern
`
`[
`
`] Nonprofit Organization
`
`[
`
`] Individual
`
`[ ] Small Business Concern
`
`[ ] Nonprofit Organization
`
`I acknowledge the duty to file, in this application or patent, notification of any change in status resulting in loss of entitlement to small entity status prior to paying, or at
`the time of paying, the earliest of the issue fee or any maintenance fee due alter the date on which status as a small entity is no longer appropriate. (37 CFR 1.28(b))
`
`I hereby declare that all statements made herein of my own knowledge are true and that all smtements made on information and belief are believed to be true; and
`further 11ml thm statements were made with the knowledge that wrllful false statements and the like so made are punishable by fine or Imprisonment, or both, under
`Section 1001 of Title 18 of the United States Code. and that such willful false statements may jeopardize the validity of the application, any patent Issuing thereon. or
`any patent to which this verified statement 15 directed.
`
`Name of Person Signing: w—_—_
`Title of Person If Other than Owner: WWW—“m
`Address of Person Signing: WWW—.—
`Moscow I 19435 Russia
`
`
`
`SF 1058186 V1
`
`
` Signaturc
`
`Date
`
`Page I of l
`
`Page 2 of 97
`
`

`

`
`
`
`
`Attorney Docket No.: 20181-5US
`Client Reference No.: PPA-S
`
`PATENT APPLICATION
`
`HIGH SPEED LOW POWER DATA TRANSFER SCHEME
`
`Inventor(s):
`
`Andrew V. Podlesny
`38/2 Menzinsky Street, Apt. 192
`Moscow, Russia 129281
`a citizen of Russia
`
`Valery V. Lozovoy
`108 Ac.Chelomey Street, Apt, 6
`Moscow, Russia 1 17630
`a citizen of Russia
`
`Alexander V. Malshin
`
`50 Frunzenskaya Nabergnaya, Apt. 608
`Moscow, Russia 119270
`a citizen of Russia
`
`Assignee:
`
`ELBRUS INTERNATIONAL LIMITED
`14, Bolshoi Savvinski Per.
`Moscow, Russia 119435
`
`Entity:
`
`Small business concem
`
`TOWNSEND and TOWNSEND and CREW LLP
`Two Embarcadero Center, 8‘h Floor
`San Francisco, California 9411 1-3834
`(415) 576—0200
`
`Page 3 of 97
`
`

`

`PATENT
`
`Attorney Docket No.: 20181-5US
`
`Client Reference No.: PPA-S
`
`HIGH SPEED LOW POWER DATA TRANSFER SCHEME
`
`5
`
`This application claims priority from US. Provisional Patent Application
`
`No. 60/120,531, filed February 17, 1999, the disclosure of which is incorporated herein
`
`by reference in its entirety.
`
`10
`
`1.
`
`Field Of The Invention
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a data transfer scheme, and more
`
`particularly, to a high speed and low power CMOS data transfer scheme.
`
`2.
`
`Description Of The Prior Art
`
`15
`
`Today’s requirements for electronic circuits require high speed.
`
`Additionally, the circuits should be as small and simple as possible due to the ever
`
`increasing number of circuits that are crowding today’s chip devices. Furthermore,
`
`circuits for data transfer should not be sensitive to circuit parameter mismatches, noise,
`
`and deviations in various applied voltages.
`
`20
`
`SUMMARY OF THE INVENTION
`
`The present invention provides a high speed and low power CMOS data
`
`transfer arrangement that includes two active pull up/pull down bus drivers, a differential
`
`bus that precharges to a specific voltage level and a latched differential sense amplifier
`
`25
`
`that serves as a bus receiver.
`
`In accordance with one embodiment of the present invention, a data
`
`transfer arrangement includes two bus drivers, a voltage precharge source, a differential
`
`bus coupled to the bus drivers and to the voltage precharge source, and a latching sense
`
`amplifier coupled to the differential bus.
`
`30
`
`In accordance with another embodiment of the present invention, the
`
`latching sense amplifier is arranged as a cross coupled latched amplifier.
`
`
`
`Page 4 of 97
`
`

`

`
`
`:--;
`
`
`
`
`
`2
`
`In accordance with a further embodiment of the present invention, the two
`
`bus drivers consist of active pull up/pull down bus drivers.
`
`Thus, the present invention provides a data transfer arrangement that
`
`operates at a high speed and uses low power. The data transfer arrangement is faster
`
`5
`
`because the bus voltage swing passes directly to high gain nodes of the cross-coupled
`
`latched amplifier. Additionally, the data transfer arrangement uses a lower number of
`
`stacked transistors coupled between the supply voltage and the high gain nodes when
`
`compared to the prior art. Additionally, the arrangement according to the present
`
`invention is less sensitive to deviations in voltage sources and the deviation of threshold
`
`10
`
`voltage concerns of the input transistors. Additionally, the arrangement is less sensitive
`
`to circuit parameter mismatches, data bus common mode noise and power bus noises.
`
`Other features and advantages of the present invention will be understood
`
`upon reading and understanding the detailed description of the preferred embodiments
`
`below, in conjunction with reference to the drawings, in which like numerals represent
`
`15
`
`like elements.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Figure 1 is a schematic of a differential data transfer arrangement in
`
`accordance with the present invention; and
`
`Figure 2 is a schematic of a circuit for a sense amplifying latch for use in
`
`20
`
`the data transfer arrangement illustrated in Figure I.
`
`DETAILED DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENTS
`
`Figure 1 illustrates a data transfer arrangement circuit 10 that includes two
`
`bus drivers ll, 12, a precharge circuit 13, and two complementary bus lines 14, 15. The
`
`25
`
`bus lines are inputs to a bus receiver 16 that is arranged as a latching sense amplifier.
`
`The two bus drivers are complementary and consist, preferably, of two
`
`active pull up/active pull down bus drivers.
`
`Operation of the data transfer arrangement consists of two phases: A bus
`
`precharge phase and a data transfer phase.
`
`30
`
`During the bus precharge phase, the control input PR (control signal for
`
`bus precharge circuit 13) is high and signal inputs DT (true phase of dual-rail data
`
`function) and DC (complement phase of dual-rail data function) are low. The true phase
`
`driver on transistors 20 and 21 and the complement phase driver on transistors 22 and 23
`
`Page 5 of 97
`
`

`

`3
`
`are in high impedance state and both bus lines are equalized and precharged to a potential
`
`Vpr (buses precharging voltage level) through the turned on transistors 24, 25 and 26.
`
`During the data transfer phase, the control input PR is low. The signal
`
`inputs become differential: DT is high and DC is low, and vise versa. One of the drivers
`
`is pulled up and charges the appropriate bus line from the precharged level Vpr toward a
`
`more positive Vdd — V1 (where V . is the threshold voltage of the pull up NMOS transistor
`
`of the driver). At the same time, the other driver is pulled down and discharges the
`
`opposite bus line from the precharged level Vpr towards a more negative level VSS
`
`(ground). This provides a differential voltage: +dV and — dV from the precharging level
`
`Vpr between true and complement bus lines. To provide proper operation of the bus
`
`receiver (the sensing amplifier), the minimum voltage difference 2* dem (swing)
`
`between the lines may be about 0.05-- 0.20V. This low voltage swing is a basis to obtain
`
`high frequency of data transfer through the bus.
`
`Figure 2 illustrates sensing amplifier 16. Preferably, the sensing amplifier
`
`is a cross-coupled latched amplifier.
`
`The sense amplifier operates in two phases, a precharge phase and a data
`
`transfer phase. However, the sensing amplifier operates opposite to analogous phases of
`
`the bus driver.
`
`When the control input CLK is low and the bus driver is in the data
`
`transfer mode, the sensing amplifier is in the precharge mode. The cross-coupled latched
`
`amplifier is isolated from the power buses (transistors 30 and 31 are turned oft).
`
`Transistors 32 and 33 are turned on and thus, the bus voltage swing passes to the internal
`
`nodes IT (positive binary single-rail internal point of the sensing amplifier) and IC
`
`(negative binary single-rail data input phase internal point of the sensing amplifier) of the
`
`latched amplifier. The output nodes of both dynamic gates are precharged to Vdd and the
`
`complementary outputs QT (true phase of dual-rail data output signal) and QC
`
`(complement phase of dual-rail output data signal) of the sensing amplifier become high.
`
`When the control input CLK is high and the bus driver is in the precharge
`
`mode, the sensing amplifier is in the data transfer mode. Transistors 32 and 33 are turned
`
`of and isolate the internal nodes IT and IC of the latched amplifier from the bus lines.
`
`The cross-coupled latched amplifier is connected to power buses (transistors 30 and 31
`
`are turned on) and it begins to amplify the low voltage swings of the internal nodes IT
`
`10
`
`3O
`
`Page 6 of 97
`
`

`

`
`
`4
`
`and IC to full logic levels. The output node of one of the dynamic gates is discharged to
`
`ground and the appropriate output QT or QC of the sensing amplifier becomes low.
`
`The use of domino output stages in accordance with the present invention
`
`instead of static inverters is necessary to avoid leakage currents and output glitches,
`
`5
`
`which may appear because potentials of nodes IT and [C are approximately equal to Vpr
`
`during the operating cycle of the bus driver. Weak PMOS transistors 34 and 35 are
`
`preferably included in the sensing amplifier to help prevent output glitches.
`
`The data transfer arrangement in accordance with the present invention
`
`provides an increase in speed due to the differential low voltage swing bus driver in
`
`10
`
`combination with the use of the latched differential sense amplifier as the bus receiver.
`
`A further increase in speed is attained with the data transfer arrangement
`
`due to the pull up/pull down bus drivers, which provide equal low differential voltage
`
`swings +dV/ - dV in both bus lines. This allows both bus lines to be active during the
`
`data transfer phase, eliminates the necessity to use special circuits for holding the
`
`15
`
`precharged level and leads to a reduction in the capacitance load of the driver.
`
`The buses precharging to the specific level between ground and Vd (Vpr =
`
`K*Vdd, where K = 1/3 for the ideal MOS model) also provides: equal charge and
`
`discharge driver currents lch = ldch, provided by the NMOS pull up follower and the
`
`NMOS pull down switch, respectively, and therefore, equal differential voltage swings
`
`20
`
`dV in both charged and discharged bus during the data transfer phase Pdtf: + dV =
`
`Ich*Ddlf7/CL0,\D; and -dV = Ida, *Tdm’CLOAD.
`
`Id, represents the driver pull up output current
`
`(which provides the CLOAD charging from Vpr up to Vdd); Idch represents the driver pull
`
`down output current (providing the CLOAD discharging from Vp, up to V55); CLOAD
`
`represents the bus lines’ compacitances; +dV represents the bus voltage change up from
`
`25
`
`Vpr during data transfer phase; -dV represents the bus voltage change down from Vpr
`
`during data transfer phase; and Tm represents the data transfer phase duration. The buses
`
`preeharging to the specific level between ground and Vdd also provides high noise
`
`immunity due to active mode for both buses that equal low output resistances of the
`
`drivers in pull up and pull down mode and; low total power consumed by drivers during
`
`30
`
`the cycle of operation (transfer plus precharge).
`
`The latched sense amplifier is faster due to the bus voltage swing passing
`
`directly to the high-gain nodes IT and IC of the cross- coupled latched amplifier, the
`
`lower number of stacked transistors that are connected between the supply voltage Vdd (or
`
`Page 7 of 97
`
`

`

`5
`
`Vcc) and nodes IT and IC, the fact that during latching of the IT and IC nodes, the nodes
`
`are charged by K*Vdd and (1-K)*Vdd instead of simply Vdd. Additionally, the speed of
`
`the latched sensing amplifier is effected little by the deviation of voltage Vpr and the
`
`deviation of the threshold voltage of the input transistors.
`
`5
`
`In addition to the higher speed and low power consumption of the data
`
`transfer arrangement in accordance with the present invention, the arrangement is also
`
`less sensitive to circuit parameters mismatching, data bus common mode noise and power
`
`buses’ noises since both drivers are active during data transfer phase. During the
`
`appropriate bus precharge phase, the bus receiver is isolated from the bus lines.
`
`10
`
`Although the invention has been described with reference to specific
`
`exemplary embodiments, it will be appreciated that it is intended to cover all
`
`modifications and equivalents within the scope of the appended claims.
`
`
`
`Page 8 of 97
`
`

`

`WHAT IS CLAIMED is:
`
`1.
`
`A data transfer arrangement comprising:
`
`two bus drivers;
`
`a voltage precharge source;
`
`a differential bus coupled to the bus drivers and to the voltage precharge
`
`source; and
`
`a latching sense amplifier coupled to the differential bus.
`
`2.
`
`A data transfer arrangement in accordance with claim 1 wherein
`
`the latching sense amplifier comprises a cross coupled latched amplifier.
`
`3.
`
`A data transfer arrangement in accordance with claim 1 wherein
`
`the bus drivers consist of active pull tip/pull down bus drivers.
`
`l
`
`2
`
`{4.)
`
`4
`
`5
`
`6
`
`1
`
`Z
`
`1
`
`Z
`
`
`
`
`
`Page 9 of 97
`
`

`

`HIGH-SPEED LOW-POWER DATA TRANSFER SCHEME
`
`l
`
`ABSTRACT OF THE DISCLOSURE
`
`A data transfer arrangement. The data transfer arrangement includes two
`
`active pull tip/active pull down bus drivers and a voltage precharge source. A differential
`
`UI
`
`bus is coupled to the bus drivers and to the voltage precharge source. A latching sense
`
`amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers
`
`SF 1065331 vl
`
`operate in a precharge phase and a data transfer phase. The bus receiver operates in an
`
`analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the
`
`bus receiver is in the data transfer phase and when the bus drivers are in the data transfer
`
`10
`
`phase, the bus receiver is in a prechai'ge phase
`
`Page 10 of 97
`
`

`

`
`
`
`
`Bus drivers Precharge
`cu‘cuxt
`
`Bus lines Bus reciever
`
`Fig.1.
`
`Page 11 of 97
`
`

`

`Attorncy Docket 020181-000500US (PPA-S)
`
`As a below-named inventor, I declare that:
`
`DECLARATION AND POWER OF ATTORNEY
`
`My residence, post office address and citizenship are as stated below next to my name; I believe I am the original, first and sole
`inventor (if only one name is listed below) or an original, first and joint inventor (if plural inventors are named below) of the subject
`matter which is claimed and for which a patent is sought on the invention entitled: HIGH-SPEED LOW-POWER DATA
`TRANSFER SCHEME, the specification of which __2{__ is attached hereto or _ was filed on
`as Application No.
`and was amended on
`(if applicable).
`
`including the claims, as amended by any
`I have reviewed and understand the contents of the above-identified specification,
`amendment referred to above. I acknowledge the duty to disclose information which is material to patentability as defined in Title 37,
`Code of Federal Regulations, Section 1.56.
`I claim foreign priority benefits under Title 35, United States Code, Section 119 of any
`foreign application(s) for patent or inventor’s certificate listed below and have also identified below any foreign application for patent
`or inventor’s certificate having a filing date before that of the application on which priority is claimed
`
`Prior Foreign Application(s)
`
`Priority Claimed Under
`
`35 USC 119
`
`Coun-
`
`A . -lieation No.
`
`Date of Filin
`
`zjahereby claim the benefit under Title 35, United States Code § 119(e) of any United States provisional application(s) listed below:
`
` 60/120 531
`
`17, 1999
`
`Febru
`
`:1, claim the benefit under Title 35, United States Code, Section 120 of any United States application(s) listed below and, insofar as the
`:gubject matter of each of the claims of this application is not disclosed in the prior United States application in the manner provided by
`§the first paragraph of Title 35, United States Code, Section 112, I acknowledge the duty to disclose material information as defined in
`'é’lfitle 37, Code of Federal Regulations, Section 1.56 which occurred between the filing date of the prior application and the national or
`QCT international filing date of this application:
`
`
`
`POWER OF ATTORNEY: As a named inventor, I hereby appoint the following attomcy(s) and/or agent(s) to prosecute this
`application and transact all business in the Patent and Trademark Office connected therewith.
`
`
`
`
`I. Georg Seka, Reg. No. 24,491
`Robert J. Bennett, Reg. No. 27,533
`Charles E. Krueger, Reg. No. 30,077
`Charles J. Kulas, Reg. No. 35,809
`Kevin T. LeMond, Reg. No. 35,933
`George B.F. Yee, Reg. No. 37,478
`
`
`Direct Telephone Calls to:
`(Name, Reg. No, Telephone No.)
`Name:
`KcViD T- LeMond
`
`ch- No.2
`35933
`
`
`Telephone: 415-576-0200
`
`
`
`Chad S. Hilyard, Reg. No. 40,647
`Gerald T. Gray, Reg. No. 41,797
`Daniel D. Tagliaferri, Reg. No. 43,178
`Thomas D. Franklin, Reg. No. 43,616
`Patrick M. Boucher, Reg. No. 44,037
`
`
`
`Send Correspondence to:
`
`Kevin T. LeMond
`TOWNSEND and TOWNSEND and CREW LLP
`Two Embarcadero Center, 8'” Floor
`
`San Francisco California 94111-3834
`
`lon
`
`Page 12 of 97
`
`

`

`Attorney Docket 020181-000500US (PPA-S)
`
`F1111 Name Of
`
`
`
`Citizenshi - :
`
`Last Name:
`
`Moscow
`
`State/Foreign Country:
`Russia
`
`
`
`Middle Name or Initial:
`
`Country of Citizenship:
`Russia
`
`Address:
`
`A - t. 192 38/2 Menzins. St.
`
`Moscow
`
`Russia
`
`129281
`
`
`
`
`
`
`
`
`Inventor 23
`
`
`
`
`Ci ' enshi :
`
`Post Office
`
`F11" Name Of
`
`
`
`
`
`Citizenshi . :
`
`Post Office
`Address:
`
`Malshin
`
`Moscow
`
`Alexander
`State/Foreign Country:
`Russia
`
`Post Ofiice Address:
`Apt. 608,
`50 Frunzenska a Naberna a
`Last Name:
`
`City:
`Moscow
`
`First Name:
`
`City:
`Moscow
`
`State/Foreign Country:
`Russia
`
`
`
`Country of Citizenship:
`Russia
`
`Post Office Address:
`14 Bolshoi Savvinski Per.
`
`City:
`Moscow
`
`State/Country:
`Russia
`
`Postal Code:
`119435
`
`V.
`Country of Citizenship:
`Russia
`
`State/Country:
`Russia
`
`Postal Code:
`I 19270
`
`Middle Name or Initial:
`
`
`
`
`
`
`
`
`
`
`
`
`”I! further declare that all statements made herein of my own knowledge are true and that all statements made on information and belief
`are believed to be true; and further that these statements were made with the knowledge that willful false statements and the like so
`’j-rqiiade are punishable by fine or imprisonment, or both, under Section 1001 of Title 18 of the United States Code, and that such willful
`é:itialsc statements may jeopardize the validity of the application or any patent issuing thereon.
`
`
`
`M‘Tn--rlu-n--
`
`Signature of Inventor 2
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`Signature of Inventor 3
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`Date
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`_ Monastery. Sotomamikov_.
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`3:33am
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`TOWNSEND and TOWNSEND and CREW LLP
`Two Embarcadero Ofinter, 8‘h Floor
`San Francisco, California 94111-3834
`(415) 576-0200
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`ASSISTANT COMMISSIONER FOR PATENTS
`BOX PATENT APPLICATION
`Washington, D.C. 20231
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`'
`
`Sir:
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`o“
`20181-5US
`Attorney Docket’No.
`PP -5
`Client Ref No.
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`'
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`“Express Mail" Label No.
`EL394§27§§3US
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`a
`17 2
`Date of Deposit:
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`Assistant Commissioner for
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`I hereby certify that this is being deposited with the United States
`Postal Service “Express Mail Post Office to Addressee" service
`under 37 CFR 1.10 on the dat
`' dicated above, addressed to:
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`Washington, DC. 20231
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`\
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`‘0 ‘° §
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`By:
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`Transmitted herewith for filing is the
`[ X ] patent application of
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`-
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`rs o‘ \
`8% $01
`'1‘
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`Inventor(s)/Applicant Identifier: Andrew V. Podlesny et a1.
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`For: HIGH SPEED LOW POWER DATA TRANSFER SCHEME
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`[ X ]
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`This application clairns priority from each of the following Application Nosjfiling dates:
`0/ 2
`l/File 2/17/ 9
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`the disclosure(s) of which is (are) incorporated by reference.
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`Enclosed are:
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`[ X ]
`[ X ]
`[ X ]
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`[ X ] informal drawing(s).
`] formal
`sheet(s) of [
`l
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`] signed [ X ] unsigned Declaration.
`‘
`A [
`A verified statement to establish small entity status under 37 CFR 1.9 and 37 CFR 127 [ X ] is enclosed [
`prior application and small entity Status is still proper and desired.
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`] was filed in the
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`In view of the Unsigned Declaration as filed with this application and pursuant to 37 CFR §1.53(d),
`Applicant requests deferral ot’ the filing fee until submission of the Missing Parts of Application.
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`DO NOT CHARGE THE FILING FEE AT THIS TIME.
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`Reg No.: 35.933
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`SF mouse"
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`Page 14 of 97
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`Bus drivers Precharge
`c1rcu 1t
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`Bus lines Bus reciever
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`Fig.1.
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`Attorney Docket No.: 20181-5US
`Client Reference No.: PPA-5
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`PATENT APPLICATION
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`HIGH SPEED LOW POWER DATA TRANSFER SCHEME
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`Inventor(s):
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`Andrew V. Podlesny
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`38/2 Menzinsky Street, Apt. 192
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`Moscow, Russia 129281
`a citizen of Russia
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`Valery V. Lozovoy
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`108 Ac.Chelomey Street, Apt. 6
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`Moscow, Russia 117630
`a citizen of Russia
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`Alexander V. Malshin
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`50 Frunzenskaya Nabergnaya, Apt. 608
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`Moscow, Russia 119270
`a citizen of Russia
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`Assignee:
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`ELBRUS INTERNATIONAL LIMITED
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`14, Bolshoi Savvinski Per.
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`Moscow, Russia 119435
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`Entity:
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`Small business concern
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`TOWNSEND and TOWNSEND and CREW LLP
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`
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`Two Embarcadero Center, 8‘h Floor
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`San Francisco, California 94111-3834
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`(415) 576-0200
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`Jl
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`PATEN
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`Attorney Docket No.: 20181-5US
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`Client Reference No.: PPA-S
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`HIGH SPEED LOW POWER DATA TRANSFER SCHEME
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`This application claims priority from US. Provisional Patent Application
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`No. 60/ 120,53l , filed February 17, 1999, the disclosure of which is incorporated herein
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`by reference in its entirety.
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`10
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`1.
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`Field OfThe Invention
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`BACKGROUND OF THE INVENTION
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`The present invention relates to a data transfer scheme, and more
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`particularly, to a high speed and low power CMOS data transfer scheme.
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`2.
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`Description OfThe Prior Art
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`Today’s requirements for electronic circuits require high speed.
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`Additionally, the circuits should be as small and simple as possible due to the ever
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`increasing number of circuits that are crowding today’s chip devices. Furthermore,
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`circuits for data transfer should not be sensitive to circuit parameter mismatches, noise,
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`and deviations in various applied voltages.
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`SUMMARY OF THE INVENTION
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`The present invention provides a high speed and low power CMOS data
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`transfer arrangement that includes two active pull up/pull down bus drivers, a differential
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`bus that precharges to a specific voltage level and a latched differential sense amplifier
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`that serves as a bus receiver.
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`In accordance with one embodiment of the present invention, a data
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`transfer arrangement includes two bus drivers, a voltage precharge source, a differential
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`bus coupled to the bus drivers and to the voltage precharge source, and a latching sense
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`amplifier coupled to the differential bus.
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`In accordance with another embodiment of the present invention, the
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`latching sense amplifier is arranged as a cross coupled latched amplifier.
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`In accordance with a further embodiment of the present invention, the two
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`bus drivers consist of active pull up/pull down bus drivers.
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`Thus, the present invention provides a data transfer arrangement that
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`operates at a high speed and uses low power. The data transfer arrangement is faster
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`because the bus voltage swing passes directly to high gain nodes of the cross-coupled
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`latched amplifier. Additionally, the data transfer arrangement uses a lower number of
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`stacked transistors coupled between the supply voltage and the high gain nodes when
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`compared to the prior an. Additionally, the arrangement according to the present
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`invention is less sensitive to deviations in voltage sources and the deviation of threshold
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`voltage concerns of the input transistors. Additionally, the arrangement is less sensitive
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`to circuit parameter mismatches, data bus common mode noise and power bus noises.
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`Other features and advantages of the present invention will be understood
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`upon reading and understanding the detailed description of the preferred embodiments
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`below, in conjunction with reference to the drawings, in which like numerals represent
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`like elements.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`Figure 1 is a schematic of a differential data transfer arrangement in
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`accordance with the present invention; and
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`Figure 2 is a schematic ofa circuit for a sense amplifying latch for use in
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`the data transfer arrangement illustrated in Figure 1.
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`DETAILED. DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENTS
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`Figure 1 illustrates a data transfer arrangement circuit 10 that includes two
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`bus drivers 11, 12,,a precharge circuit 13, and two complementary bus lines 14, 15. The
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`bus lines are inputs to a bus receiver 16 that is arranged as a latching sense amplifier.
`The two bus drivers are complementary and consist, preferably, of two
`active pull up/active pull down bus drivers.
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`Operation of the data transfer arrangement consists of two phases: A bus
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`precharge phase and a data transfer phase.
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`During the bus precharge phase, the control input PR (control signal for
`bus precharge circuit 13) is high and signal inputs DT (true phase of dual-rail data
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`function) and DC (complement phase of dual-rail data function) are low. The' true phase
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`driver on transistors 20 and 21 and the complement phase driver on transistors 22 and 23
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`are in high impedance state and both bus lines are equalized and precharged to a potential
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`VPr (buses precharging voltage level) through the turned on transistors 24, 25 and 26.
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`During the data transfer phase, the control input PR is low. The signal
`inputs become differential: DT is high and DC is low, and vise versa. One ofthe drivers
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`is pulled up and charges the appropriate bus line from the precharged level Vpr toward a
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`more positive Vdd — Vt (where V. is the threshold voltage of the pull up NMOS transistor
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`opposite bus line from the precharged level Vpr towards a more negative level VSS
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`(ground). This provides a differential voltage: +dV and ~ dV from the precharging level
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`Vpr between true and complement bus lines. To provide proper operation of the bus
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`receiver (the sensing amplifier), the minimum voltage difference 2* dein (swing)
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`between the lines may be about 0.05" 0.20V. This low voltage swing is a basis to obtain
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`high frequency of data transfer through the bus.
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`Figure 2 illustrates sensing amplifier 16. Preferably, the sensing amplifier
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`is a cross-coupled latched ainplifier.
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`The sense amplifier operates in two phases, a precharge phase and a data
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`transfer phase. However, the sensing amplifier operates opposite to analogous phases of
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`When the control input CLK is low and the bus driver is in the data
`transfer mode, the sensing amplifier is in the precharge mode. The cross-coupled latched
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`amplifier is isolated from the power buses (transistors 30 and 31 are turned off).
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`Transistors 32 and 33 are turned on and thus, the bus voltage swing passes to the internal
`nodes IT (positive binary single-rail internal point of the sensing amplifier) and IC
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`(negative binary single-rail data input phase internal point of the sensing amplifier) of the
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`latched amplifier. The output nodes of both dynamic gates are precharged to Vdd and the
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`complementary outputs QT (true phase of dual-rail data output Vsignal) and QC
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