Filed on behalf of: Samsung Electronics Co., Ltd.
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`By: Steven L. Park (stevenpark@paulhastings.com)
`
`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`____________________
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`U.S. Patent No. 6,366,130
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`____________________
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`DECLARATION OF DR. R. JACOB BAKER
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`Page 1 of 92
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`SAMSUNG EXHIBIT 1002
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`By: Steven L. Park (stevenpark@paulhastings.com)
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`Naveen Modi (naveenmodi@paulhastings.com)
`Paul Hastings LLP
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
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`v.
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`ELBRUS INTERNATIONAL LIMITED
`Patent Owner
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`____________________
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`U.S. Patent No. 6,366,130
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`____________________
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`DECLARATION OF DR. R. JACOB BAKER
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`Page 1 of 92
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`SAMSUNG EXHIBIT 1002
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`TABLE OF CONTENTS
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`Introduction ..................................................................................................... 1
`I.
`Qualifications .................................................................................................. 1
`II.
`Summary of Opinions ..................................................................................... 5
`III.
`IV. The ’130 Patent ............................................................................................... 7
`V.
`Claim Construction ......................................................................................... 9
`A.
`Latching Sense Amplifier (Claims 1 and 3) ....................................... 10
`B.
`Stage (Claims 1, 3, and 9) .................................................................. 11
`VI. The Prior Art Discloses or Suggests Every Feature of the Challenged
`Claims of the ’130 Patent ............................................................................. 12
`A.
`Brief Description of the Prior Art ...................................................... 12
`Ternullo, Either Individually or in Combination with Other
`B.
`References, Discloses or Suggests Every Feature of the
`Challenged Claims of the ’130 Patent ................................................ 14
`Ternullo Discloses the Features of Claims 1-3 and 5-6 ........... 14
`1.
`Ternullo and Hardee Disclose or Suggest the Features of
`2.
`Claim 7 ..................................................................................... 61
`Ternullo and Sukegawa Disclose or Suggest the Features
`of Claim 9 ................................................................................. 64
`VII. Conclusion .................................................................................................... 68
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`3.
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`-i-
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`I, R. Jacob Baker, declare as follows:
`
`I.
`
`INTRODUCTION
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`1.
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`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”)
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`as an independent expert consultant in this proceeding before the United States
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`Patent and Trademark Office. Although I am being compensated at my rate of
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`$450 per hour for the time I spend on this matter, no part of my compensation is
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`dependent on the outcome of this proceeding, and I have no other interest in this
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`proceeding.
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`2.
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`I understand that this proceeding involves U.S. Patent No. 6,366,130
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`(“the ’130 Patent”) (Ex. 1001), the application for which was filed on February 17,
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`2000, as U.S. Patent Application No. 09/505,656, and issued on April 2, 2002. I
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`also understand, as demonstrated by the face of the ’130 Patent, that the ’130
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`Patent purports to claim priority to February 17, 1999, the filing date of U.S.
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`Provisional Application No. 60/120,531 (“the ’531 provisional application”).
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`3.
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`I have been asked to consider whether certain references disclose or
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`suggest the features recited in the claims of the ’130 Patent. My opinions are set
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`forth below.
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`II. QUALIFICATIONS
`I serve as a Professor of Electrical and Computer Engineering at the
`4.
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`University of Nevada, Las Vegas (“UNLV”). I have been teaching electrical
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`1
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`engineering at UNLV since 2012. Before this, I was a Professor of Electrical and
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`Computer Engineering with Boise State University beginning in 2000. Before my
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`position at Boise State University, I was an Associate Professor of Electrical
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`Engineering between 1998 and 2000 and an Assistant Professor of Electrical
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`Engineering between 1993 and 1998, both at the University of Idaho. I have been
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`teaching electrical engineering since 1991. I received my Ph.D. in Electrical
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`Engineering from the University of Nevada, Reno, in 1993. I also received a MS
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`and BS in Electrical Engineering from UNLV in 1988 and 1986, respectively.
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`5.
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`As further described in my CV, I am a licensed Professional Engineer
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`in the State of Idaho and have more than 25 years of experience, including
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`extensive experience in circuit design and manufacture of Dynamic Random
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`Access Memory (DRAM) semiconductor integrated circuit chips and CMOS
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`Image Sensors (CISs) at Micron in Boise, Idaho. I also spent considerable time
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`working on the development of Flash memory while at Micron. My efforts resulted
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`in more than a dozen Flash-memory related patents. Among many other
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`experiences, I led the development of the delay-locked loop (DLL) in the late
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`1990s so that Micron DRAM products could transition to the DDR memory
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`standard. I also provided technical assistance with Micron’s acquisition of Photobit
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`during 2001 and 2002. This assistance included help transition the manufacture of
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`CIS products into Micron’s DRAM process technology. I have worked as a
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`Inter Partes Review of U.S. Patent 6,366,130
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`consultant at other companies designing memory chips, including Sun, Oracle, and
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`Contour Semiconductor. I have worked at other companies designing CISs,
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`including Aerius Photonics, Lockheed-Martin, and OmniVision.
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`6.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
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`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
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`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and/or co-
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`authored, more than 100 papers and presentations in the areas of solid-state circuit
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`design and packaging.
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`7.
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`As a professor, I have been the main advisor to five Doctoral students
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`and over 65 Masters students.
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`8.
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`I am the named inventor on over 137 granted U.S. patents in
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`integrated circuit design including flash memory, DRAM, and CMOS image
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`sensors.
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`9.
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`I have received numerous awards for my work, including the
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`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
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`Award is bestowed annually upon an outstanding young electrical/computer
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`engineering educator in recognition of the educator’s contributions to the
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`profession.
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`3
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`Inter Partes Review of U.S. Patent 6,366,130
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`I have also received the IEEE Circuits and Systems Education Award
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`10.
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`(2011), the IEEE Power Electronics Best Paper Award (2000), and I am a Fellow
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`of the IEEE for contributions to memory circuit design.
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`11.
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`In addition, I have received the President’s Research and Scholarship
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`Award (2005), Honored Faculty Member recognition (2003), Outstanding
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`Department of Electrical Engineering Faculty recognition (2001), all from Boise
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`State University. I have also received the Tau Beta Pi Outstanding Electrical and
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`Computer Engineering Professor Award the three years I have been at UNLV.
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`12.
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`I have also given over 50 invited talks at conferences and universities
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`in the areas of integrated circuit design including: AMD, Arizona State University,
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`Beijing Jiaotong University, Carleton University, Carnegie Mellon, Columbia
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`University, Dublin City University (Ireland), École Polytechnique de Montréal,
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`Georgia Tech, Gonzaga University, Hong Kong University of Science and
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`Technology, Indian Institute of Science (Bangalore, India), Instituto de Informatica
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`(Brazil), Instituto Tecnológico y de Estudios Superiores de Monterrey, ITESM
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`(Mexico), Iowa State University, Laval University, Lehigh University, Princeton
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`University, Temple University, University of Alabama, University of Arkansas,
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`University of Buenos Aires (Argentina), University of Illinois, Urbana-Champaign,
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`Utah State University, University of Nevada, Las Vegas, University of Houston,
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`University of Idaho, University of Nevada, Reno, University of Macau, University
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`of Toronto, University of Utah, Yonsei University (Seoul, Korea), University of
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`Maryland, IEEE Electron Devices Conference (NVMTS), IEEE Workshop on
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`Microelectronics and Electron Devices (WMED), the Franklin Institute, National
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`Semiconductor, AMI semiconductor, Micron Technology, Rendition, Saintgits
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`College (Kerala, India), Southern Methodist University, Sun Microsystems,
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`Stanford University, ST Microelectronics (Delhi, India), Tower (Israel), Foveon,
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`ICySSS keynote, and Xilinx.
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`13.
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`Details of my professional and educational background, as well as a
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`listing of other matters on which I have provided consulting and/or provided
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`testimony as a technical expert, are provided in my Curriculum Vitae, attached as
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`Appendix A to this Declaration.
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`III. SUMMARY OF OPINIONS
`All of the opinions contained in this Declaration are based on the
`14.
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`documents I reviewed, my experience and background, and my knowledge and
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`professional judgment. In forming the opinions expressed in this Declaration, I
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`reviewed the ’130 Patent (Ex. 1001); the prosecution file history for the ’130
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`Patent (Ex. 1003); the file history of the inter partes reexamination (control no.
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`95/000,657) (“the ’657 proceeding”) for the ’130 Patent, excerpts of which I
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`understand are being submitted as Ex. 1004; U.S. Patent No. 6,052,328 to Ternullo
`
`et al. (“Ternullo”) (Ex. 1005); U.S. Patent No. 5,828,241 to Sukegawa
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`5
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`Inter Partes Review of U.S. Patent 6,366,130
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`(“Sukegawa”) (Ex. 1006); U.S. Patent No. 6,249,469 to Hardee (“Hardee”) (Ex.
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`1007); and excerpts from the Modern Dictionary of Electronics (7th ed. 1999) (Ex.
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`1008), while drawing on my experience and knowledge in the field.
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`15. My opinions have also been guided by my appreciation of how a
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`person of ordinary skill in the art would have understood the claims of the ’130
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`Patent at the time of the alleged invention, which I have been asked to initially
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`assume is February 17, 1999, the filing date of the ’531 provisional application
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`from which the ’130 Patent purports to claim priority. At the time of the alleged
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`invention, a person of ordinary skill in the art related to the technology of the ’130
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`Patent would have had an undergraduate degree in Electrical Engineering or
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`equivalent and at least two to three years of experience in the design and/or
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`analysis of data transfer circuits or the equivalent. In determining the level of
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`ordinary skill, I was asked to consider, for example, the types of problems
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`encountered in the art, prior solutions to those problems, the rapidity with which
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`innovations are made, the sophistication of the technology, and the educational
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`level of active workers in the field.
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`16.
`
`Based on my experience and expertise, it is my opinion that certain
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`references disclose or suggest all the features recited in claims 1-3, 5-7, and 9 (“the
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`challenged claims”) of the ’130 Patent.
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`6
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`IV. THE ’130 PATENT
`The ’130 Patent is purportedly directed to a data transfer scheme that
`17.
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`includes two bus drivers, a precharge circuit, two complementary bus lines, and a
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`latching sense amplifier. See, e.g., Ex. 1001 2:1-8. Figure 1 of the ’130 Patent
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`illustrates two bus drivers 11, 12 (consisting of transistors 20, 21, 22, and 23) and
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`two complementary bus lines 14, 15 as inputs to a latching sense amplifier 16:
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`
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`18.
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`The data transfer scheme operates in two phases: a precharge phase
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`and a data transfer phase (Ex. 1001 2:12-13), with the bus drivers and
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`complementary bus lines operating in opposite phases to the latching sense
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`amplifier (Ex. 1001 2:43-44). In other words, when the complementary bus lines
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`Inter Partes Review of U.S. Patent 6,366,130
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`and the bus drivers are in the precharge phase, the sense amplifier is in data
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`transfer phase and vice versa.
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`19.
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`Figure 2 of the ’130 Patent discloses a latching sense amplifier:
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`
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`20.
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`I understand that the ’130 Patent includes 9 claims with claims 1 and
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`8 being independent and claims 2-7 and 9 being dependent from claim 1. I further
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`understand that claim 9 was added during reexamination. As I note above, I was
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`asked to opine with respect to some of the claims of the ’130 Patent. I have
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`reproduced claim 1 below:
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`1. A data transfer arrangement comprising:
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`two bus drivers;
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`a voltage precharge source;
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`8
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`Inter Partes Review of U.S. Patent 6,366,130
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`a differential bus coupled to the bus drivers and to the voltage precharge
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`source; aid [sic]
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`a latching sense amplifier coupled to the differential bus;
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`wherein the latching sense amplifier comprises:
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`a first stage including a cross-coupled latch coupled to a differential data
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`bus; and
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`an output stage coupled to an output of said first stage;
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`wherein the output of the first stage is coupled to an input of the output
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`stage;
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`wherein the differential bus and the differential data bus are precharge to a
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`voltage Vpr between Vdd and ground, where Vpr = K*Vdd, and K is a
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`precharging voltage factor.
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`V. CLAIM CONSTRUCTION
`I understand that a claim subject to inter partes review receives the
`21.
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`broadest reasonable construction in light of the specification of the patent in which
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`it appears. I also understand that in these proceedings, any term that is not
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`construed should be given its plain and ordinary meaning under the broadest
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`reasonable construction. I have followed these principles in my analysis. I discuss
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`a few terms below and what I understand to be Petitioner’s constructions of these
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`terms.
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`A. Latching Sense Amplifier (Claims 1 and 3)
`Independent claim 1 and dependent claim 3 of the ’130 Patent recite a
`22.
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`“latching sense amplifier.” I understand Petitioner has offered that the broadest
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`reasonable construction of the term “latching sense amplifier” that is consistent
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`with the use of the term in the claims and specification of the ’130 Patent is “a
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`circuit, including a latch, that detects and amplifies signals.” I have used this
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`construction in my analysis and agree with it because the specification describes its
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`latching sense amplifier to include a latch (see, e.g., Ex. 1001 2:39-40, 2:48-50) for
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`detecting (see, e.g., Ex. 1001 2:33-38, 2:64-67) and amplifying received signals
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`(see, e.g., Ex. 1001 2:64-67). Furthermore, latching sense amplifiers were well
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`known at the time of the alleged invention of the ’130 Patent, and this construction
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`is consistent with the understanding of one of ordinary skill in the art at the time of
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`the alleged invention of the ’130 Patent as well as dictionary definitions for similar
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`terms (see, e.g., Ex. 1008 at 679 (defining “sense amplifier” as “[a] circuit used to
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`sense low-level voltages … and to amplify these signals to the logic voltage levels
`
`of the system”). In my opinion, the claims additionally specify what a “latching
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`sense amplifier” has to include. For example, claim 1 requires that the “latching
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`sense amplifier” include both a first stage with a cross-coupled latch and an output
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`stage. See, e.g., Ex. 1001 4:8-13.
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`10
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`Stage (Claims 1, 3, and 9)
`
`Independent claim 1 and dependent claims 3 and 9 recite a “stage.” I
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`B.
`23.
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`understand Petitioner has offered that the broadest reasonable construction of the
`
`term “stage” that is consistent with the use of the term in the claims of the ’130
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`Patent is “portion of a circuit.” I have used this construction in my analysis and
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`agree with it. In my experience and in the field, the term “stage” is sometimes used
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`to refer to a portion of a circuit. This construction is consistent with dictionary
`
`definitions for the term. See, e.g., Ex. 1008 at 728 (defining “stage” as “[a] single
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`section of a multisection circuit or device”). This meaning is further reinforced by
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`the claims. Claim 1 specifies that a latching sense amplifier comprises of a “first
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`stage” and an “output stage,” and claims 3 and 9 use the terms in the context of
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`particular circuitry found within a “first stage” and an “output stage.” See, e.g.,
`
`Ex.1001 4:8-13, 4:21-23, Reexam Cert. 1:20-21. As the latching sense amplifier is
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`itself a circuit, it follows accordingly that particular “stages” of the circuit reflect a
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`portion of the circuit. My understanding is also consistent with the specification’s
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`use of the term “stage.” Ex. 1001 3:4-5.
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` Declaration of Dr. R. Jacob Baker
`Inter Partes Review of U.S. Patent 6,366,130
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`
`VI. THE PRIOR ART DISCLOSES OR SUGGESTS EVERY FEATURE
`OF THE CHALLENGED CLAIMS OF THE ’130 PATENT
`
`24.
`
`I have reviewed several references, discussed further below, that I
`
`understand are prior art to the ’130 Patent. In my opinion, these references disclose
`
`or suggest all features of the challenged claims of the ’130 Patent.
`
`A. Brief Description of the Prior Art
`Ternullo describes “a method and apparatus that accomplishes a high
`25.
`
`performance, random read/write SDRAM design by synchronizing the read and
`
`write operation at the data line sense amplifier.” Ternullo Abstract. As such,
`
`Ternullo generally relates to the transmission of signals in an electronic circuit.
`
`Ternullo sought to overcome the challenges of using the same set of lines for
`
`efficient read and write operations (see, e.g., id. 2:9-35), and in doing so, teaches,
`
`among other things, a “high performance write process without impacting the
`
`critical read path” (id. 1:9-10).
`
`26.
`
`Sukegawa describes “a type of signal transmission circuit wherein the
`
`signal is amplified and transmitted by means of the positive feedback of an
`
`intermediate amplifier circuit having input/output shared terminals.” Sukegawa
`
`1:11-15. The signal transmission circuit disclosed sought to increase the signal
`
`transmission distance as well as increase the speed and lower the power
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`consumption of a transmission. Id. 4:52-55. Sukegawa discloses that its signal
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`Inter Partes Review of U.S. Patent 6,366,130
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`transmission circuit comprises of “a driver circuit, a receiver circuit, an equalizer
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`circuit, and an intermediate amplifier circuit.” Id. 4:62-65. The intermediate
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`amplifier circuit relies on positive feedback to amplify the signal provided by the
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`driver circuit and transmit the amplified signal to the receiver circuit. See, e.g., id.
`
`5:1-4.
`
`27.
`
`Hardee
`
`is yet another prior art reference relating
`
`to signal
`
`transmission, and in particular, “integrated circuit memories” and “sense amplifiers
`
`for use therein.” See, e.g., Hardee 1:8-10. Hardee introduces a sense amplifier
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`highlighted by three “salient” features:
`
`(1) the connection of each sense amplifier via transistors
`
`or other switching devices to the power supply lines
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`without directly connecting together power supply lines
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`for multiple sense amplifiers;
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`(2) the use of local read amplifiers;
`
`(3) the use of local write circuitry.
`
`See i.d. 5:24-32.
`
`28.
`
`All the prior art references mentioned above relate to signal
`
`transmission and were motivated to improve the efficiency of such transmissions.
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`As such, one of ordinary skill in the art at the time of the alleged invention of the
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`
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`13
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`Declaration of Dr. R. Jacob Baker
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`Inter Partes Review of US. Patent 6,366,130
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`’130 Patent would have been motivated to combine the teachings of these
`
`references.
`
`B.
`
`Ternullo, Either Individually or in Combination with Other
`References, Discloses or Suggests Every Feature of the Challenged
`Claims of the ’130 Patent
`
`29-
`
`In my opinion, Ternullo, either individually or in combination with
`
`other references, such as Hardee and Sukegawa, discloses or suggests the features
`
`recited in the challenged claims of the ’ 130 Patent.
`
`1.
`
`Ternullo Discloses the Features of Claims 1-3 and 5-6
`
`30.
`
`In my opinion and as shown in the charts below, Ternullo discloses
`
`each and every feature recited in claims 1-3 and 5-6 of the ’ 130 Patent.
`
`a.
`
`Claim 1
`
`31.
`
`Ternullo discloses each and every feature of claim 1.
`
`1. A data transfer
`
`Temullo discloses a data transfer arrangement.
`
`arrangement
`
`For example, Ternullo states
`
`that
`
`its “present
`
`invention
`
`comprising:
`
`provides a method and apparatus that accomplishes a high
`
`Ternullo further discloses that “[d]uring a read operation, read
`
`performance,
`
`random read/write
`
`SDRAM design
`
`by
`
`synchronizing the read and write operations at the data line
`
`sense amplifier.” Ternullo Abstract.
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`Declaration of Dr. R. Jacob Baker
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`Inter Partes Review of US. Patent 6,366,130
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`data is transferred from the memory cells of the device across
`
`a series of consecutive pairs of data lines to an input/output
`
`port of the memory device.” Ternullo Abstract (emphasis
`
`added).
`
`operation.” Ternullo 4:63—67.
`
`Fig. 2 of Ternullo “shows a schematic diagram of the read
`
`circuitry 32A that is formed in accordance with the present
`
`invention as it may be implemented as part of the data sense
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`line sense amplifier and supporting circuitry 32 (FIG. 1). The
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`read circuitry 32A is
`
`required for performing a
`
`read
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`15
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`Declaration of Dr. R. Jacob Baker
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`Inter Partes Review of US. Patent 6,366,130
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`CIRCUIT
`
`ISOLATION
`CIRCLIY
`
`‘
`
`,
`L,
`,
`Isowlolv
`m;
`mm
`1.0616
`
`lmv-u
`05;"
`
`.
`
`—
`
`)
`
`‘
`
`mun"
`
`mm:
`
`4
`
`_/
`
`(annotated below).
`
`See also, e.g., Temullo Flg. 1.
`
`two bus drivers;
`
`Temullo discloses two bus drivers (e.g., transistor group 91-94
`
`and transistor group 95-98). See,
`
`e.g., Termlllo Fig.
`
`3
`
`Page 18 of 92
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`16
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`
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`
`
`READBM is also low at that time, a high signal will be passed
`
`and DLL2. See, e.g., Temullo 7:31-37 (“The read driver
`
`Two bus drivers
`
`Temullo discloses that “read driver coupled to latch line LAT2
`
`includes PFET transistors 91 and 92 and NFET transistors 93
`
`and 94. The read driver coupled to latch line LAT] includes
`
`PFET transistors 95 and 96 and NFET transistors 97 and 98.”
`
`Ternullo 7:15-18.
`
`The two bus drivers drive the outputs of Fig. 3 on lines DLLl
`
`operates such that when the signal on the latch line LAT2 is
`
`low, PFET transistor 91 is biased on, and if the signal
`
`Page 19 of 92
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`
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`to the line DLLl. If the latch line LAT2 is high, then the
`
`NFET transistor 94 will be biased on, and if the signal
`
`READM is high, then a low signal will be passed to the line
`
`DLLl.”); 7:18-22 (“While the connections and operation of
`
`the read driver connected to latch line LAT2 will be described
`
`below, it is understood that the read driver connected to latch
`
`line LAT] is constructed and operates similarly”).
`
`a voltage
`
`Temullo discloses a voltage precharge source (e.g., VBLR).
`
`precharge source;
`
`See, e.g., Temullo Fig. 5 (annotated below).
`
`
`
`
`
`VBLR represents a voltage precharge source because prior to
`
`Page 20 of 92
`
`18
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`receiving data on lines DLLl and DLL2,
`
`these lines are
`
`precharged to the midlevel voltage VBLR: “when control
`
`signal DCLKD is high and signal DCLKN is low, NFET
`
`transistor 161 and PFET transistor 162 couple line DLLl to
`
`line DLL2, while NFET transistors 163 and 164 and PFET
`
`transistors 165 and 166 couple the lines DLLl and DLL2 to
`
`the midlevel voltage source VBLR.” Ternullo 8:28-32; see
`
`also, e.g., id. 10:35-40.
`
`source; aid [sic]
`
`a differential bus
`
`Temullo discloses a differential bus (e.g., DLLl and DLL2)
`
`coupled to the bus coupled to the bus drivers (e.g., transistor group 91-94 and
`
`drivers and to the
`
`transistor group 95-98) and to the voltage precharge source
`
`voltage precharge
`
`(e.g., VBLR). See, e.g., Ternullo Figs. 3, 5 (annotated below).
`
`Page 21 of 92
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`19
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
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`Bus drivers
`
`
`
`Page 22 of 92
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`20
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
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`Voltage precharge
`source
`
`
`
`Differential
`
`bus
`
`jfouzi“
`
`Temullo discloses that the DLLl and DLL2 outputs driven by
`
`the bus drivers in Fig. 3 correspond to DLLl and DLL2 (i.e.
`
`the “differential bus”) and serve as inputs to Fig- 5: “latch lines
`
`LAT] and LAT2 are coupled through read drivers 90 to data
`
`latch lines DLL2 and DLLl, respectively. The read driver
`
`coupled to latch line LAT2 includes PFET transistors 91 and
`
`92 and NFET transistors 93 and 94. The read driver coupled to
`
`includes PFET transistors 95 and 96 and
`latch line LAT]
`
`
`Page 23 of 92
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`21
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`NFET transistors 97 and 98.” Temullo 7:13-18 (emphasis
`
`added); see also id. Figs- 1-5. Thus, the bus drivers are coupled
`
`to the differential bus.
`
`Temullo further discloses that “when control signal DCLKD is
`
`high and signal DCLKN is low, NFET transistor 161 and
`
`PFET transistor 162 couple line DLLl to line DLL2, while
`
`NFET transistors 163 and 164 and PFET transistors 165 and
`
`166 couple the lines DLLl and DLL2 to the midlevel voltage
`
`source VBLR.” Ternullo 8:28-32 (emphasis added); see also,
`
`e.g., id. 10:35-40.
`
`One of ordinary skill in the art at the time of the alleged
`
`invention of the ’ 130 Patent would have recognized DLLl and
`
`DLL2 as the “differential bus” because a voltage differential
`
`(i.e., a difference in voltages between the two bus lines) can
`
`develop on these two bus lines. See, e.g., Ternullo 10:35—43. In
`
`addition, DLLl and DLL2 precede isolation circuit170 within
`
`Temullo’s latching sense amplifier (discussed further below),
`
`and is consistent with the Patent Owner’s own mapping of
`
`“differential bus” in the ’657 proceeding:
`
`
`Page 24 of 92
`
`22
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
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`bus;
`
`Busdrivcnx Prwhargc Buslims Bus recicvct
`circuit
`
`Ex. 1004, p. 68 (declaration of Dr. Philip Koopman submitted
`
`by Patent Owner; labeled differential bus LT and LC precedes
`
`sense amplifier 16).
`
`a latching sense
`
`Temullo discloses a latching sense amplifier (shown in purple)
`
`amplifier coupled
`
`coupled to the differential bus DLLl and DLL2. See, e.g.,
`
`to the differential
`
`Temullo Fig. 5 (annotated below).
`
`Page 25 of 92
`
`23
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`Differential
`
`bus
`
`
`
`Latching sense
`amplifier
`
`7:58-83, 8:51—55, 10:46—49.
`
`The purple box drawn above for the latching sense amplifier is
`
`consistent with Petitioner’s proposed construction of “latching
`
`sense amplifier,” as it is a circuit, including a latch, that detects
`
`and amplifies signals. This circuit includes an input/output
`
`latch 180. The circuit detects and amplifies the signal on DLLl
`
`and DLL2 received through isolation circuit 170. Temullo
`
`Page 26 of 92
`
`
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`Ternullo discloses that “[w]hen NFET transistor 186 is biased
`
`on by a high on control signal IOEQN and when PFET
`
`transistor 181 is biased on by a low on control signal IOEQ,
`
`the input/output latch 180 is turned on. Once the input/output
`
`latch 180 is turned on, when a high or low signal appears on
`
`either of the lines IOLATI or IOLAT2, the other line IOLATI
`
`or IOLAT2 is correspondingly driven to the opposite state by
`
`the function of the latch.” Ternullo 8:48-55.
`
`wherein the
`
`Ternullo discloses a latching sense amplifier (shown in purple)
`
`latching sense
`
`wherein a first stage (shown in light blue) includes a cross-
`
`amplifier
`
`coupled latch (e.g.,
`
`input/output
`
`latch 180) coupled to a
`
`comprises: a first
`
`differential data bus (e.g., IOLATl and IOLAT2). See, e.g.,
`
`stage including a
`
`Ternullo Fig- 5 (annotated below).
`
`
`
`cross—coupled
`
`latch coupled to a
`
`differential data
`
`bus; and
`
`Page 27 of 92
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`25
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of U.S. Patent 6,366,130
`
`Differential data bus
`
`
`
`
`
`
`L, ___________ mm . mm
`
`
`
`First stage
`
`Latching sense
`ampllfier
`
`The light blue box drawn above for the first stage is consistent
`
`with Petitioner’s proposed construction of “stage,” as it is a
`
`“portion of a circuit.” Namely, the first stage is a portion of the
`
`latching sense amplifier. In particular,
`
`isolation circuit 170
`
`passes the differential voltage to input/output latch 180, which
`
`eventually latches and amplifies the differential voltage. See,
`
`Page 28 of 92
`
`26
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`e.g., Ternullo 7:58—83, 8:48-55, 10:35—43.
`
`Ternullo discloses that “[w]hen NFET transistor 186 is biased
`
`on by a high on control signal IOEQN and when PFET
`
`transistor 181 is biased on by a low on control signal IOEQ,
`
`the input/output latch 180 is turned on. Once the input/output
`
`latch 180 is turned on, when a high or low signal appears on
`
`either of the lines IOLATl or IOLAT2, the other line IOLATI
`
`transistor, and Vice versa:
`
`or IOLAT2 is correspondingly driven to the opposite state by
`
`the function of the latch.” Termlllo 8:48-55.
`
`Fig. 5 of Ternullo (annotated below) further teaches that the
`
`latch in Ternullo’s first stage is cross coupled because the
`
`output of a first transistor is tied to the input of a second
`
`Page 29 of 92
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`27
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`Claim Language
`
`covered by the green lines should be removed):
`
`One of ordinary skill
`
`in the art at the time of the alleged
`
`invention of the ’130 Patent would have understood that
`
`input/output
`
`latch 180 in Fig.
`
`5
`
`is mistakenly drawn
`
`incorrectly. The gates of the transistors are improperly
`
`connected to each other (the section of annotated Fig. 5 below
`
`Page 30 of 92
`
`28
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`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`Claim Language
`
`
`
`Indeed, Temullo teaches that “input/output
`
`latch operate[s]
`
`correctly without the transistor gates connected to each other:
`
`similarly to
`
`data line latch 80 in FIG. 2” (Ternullo 7:63-65),
`
`and data line latch 80, as further detailed in Fig. 3, is drawn
`
`Page 31 of 92
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`29
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`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`: transistor 82
`I not connected
`
`to gate of
`transistor 83
`
`
`
`Additionally, one of ordinary skill in the art at the time of the
`
`alleged invention of the ’130 Patent would have recognized
`
`IOLATl and IOLAT2 as the “differential data bus” because it
`
`represents an amplified voltage differential representative of
`
`the data to be read out by the latching sense amplifier. See,
`
`e.g., Temullo 8:45-55. Indeed, one of ordinary skill in the art
`
`at the time of the alleged invention of the ’130 Patent would
`
`have understood IOLATl and IOLAT2 to include differential
`
`data because of the amplified voltage differential on these
`
`lines.
`
`Ternullo discloses a latching sense amplifier (shown in purple)
`
`Page 32 of 92
`
`30
`
`
`
`Declaration of Dr. R. Jacob Baker
`
`Inter Partes Review of US. Patent 6,366,130
`
`coupled to an
`
`wherein an output stage (e.g., read drivers 190, shown in
`
`output of said
`
`orange) is coupled to an output of the first stage (shown in
`
`first stage;
`
`light blue), and wherein the output of the first stage is coupled
`
`wherein the
`
`to an input of the output stage. See, e.g., Temullo Fig. 5
`
`output of the first
`
`(annotated below).
`
`stage is coupled
`
`to an input
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