UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`LG ELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.,
`and SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01502
`Patent 7,542,045
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
`
`Page 1 of 67
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`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`LG ELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.,
`and SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01502
`Patent 7,542,045
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
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`Page 1 of 67
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`I.
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`Introduction
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`1.
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`I am over the age of eighteen (18) and otherwise competent to make
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`this declaration.
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`2. My name is Mitchell Aaron Thornton. I am offering this declaration
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`in the matter listed above on behalf of Parthenon Unified Memory Architecture
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`LLC and at the behest of their attorneys Ahmad, Zavitsanos, Anaipakos, Alavi &
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`Mensing P.C. I am being compensated at my usual rate and my compensation is
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`not dependent on any opinions that I may take in this matter, any testimony, or any
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`intermediate or final resolution in the matter.
`
`3.
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`I understand that the Board has issued an institution Decision in the
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`above-captioned IPR concluding that the Petitioner has established a reasonable
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`likelihood of success with respect to the following grounds (collectively “Instituted
`
`Grounds”):
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`a. Obviousness of claims 1, 4, 5, 7, 10, 12, 16, and 17 over Bowes and
`
`the MPEG Standard;
`
`b. Obviousness of claims 9 and 15 over Bowes, the MPEG Standard and
`
`Rathnam; and
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`c. Obviousness of claims 2, 6, and 13 over Bowes, the MPEG Standard
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`and Stearns.
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`4.
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`This declaration is directed to an analysis of these Instituted Grounds.
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`II. My Background and Qualifications
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`5.
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`I earned a Bachelor of Science degree in Electrical Engineering from
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`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
`
`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
`
`earned a Masters of Science degree in Computer Science from Southern Methodist
`
`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
`
`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
`
`6.
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`I am currently the Cecil H. Green Chair of Engineering and Professor
`
`in the Department of Computer Science and Engineering and in the Department of
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`Electrical Engineering at Southern Methodist University. Prior to 2002, I served as
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`a faculty member at Mississippi State University in the Department of Electrical
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`and Computer Engineering from 1999 through 2002. I served as a faculty member
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`at the University of Arkansas from 1995 through 1999 in the Department of
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`Computer Systems Engineering. In my university positions, my responsibilities
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`are research, teaching, and providing service in my profession. My teaching and
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`research area of expertise is generally in the area of computer engineering where I
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`specialize in hardware design for information processing systems.
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`7.
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`In addition to my academic rank of professor, I am also the Associate
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`and Technical Director of the Darwin Deason Institute for Cyber Security at
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`Southern Methodist University. The Institute mission is to advance the science,
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`policy, application and education of cyber security through basic and problem-
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`driven, interdisciplinary research. As Associate and Technical Director, I am
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`responsible for the coordination and oversight of all research projects within the
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`auspices of this multi-million dollar endowed research Institute that is comprised
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`of 11 principal investigators and their associated research teams. In this role, I am
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`routinely involved with several different state-of-the-art projects regarding the
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`technical aspects of information processing system processes, methods, software,
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`and hardware.
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`8.
`
`Prior to my academic career, I was employed in the commercial sector
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`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
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`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`communications systems. The communications systems I was involved with
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`3
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
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`9.
`
`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`10. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
`
`11.
`
`I am a named inventor on three (3) issued patents and two (2) patent
`
`applications under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
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`4
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`science.
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`12. My curriculum vitae and testimony list are included in Appendix A to
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`this declaration, which more fully sets forth my qualifications.
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`III. Documents Considered
`In addition to my knowledge and experience, I have reviewed and
`13.
`
`relied upon the following materials in performing my analysis:
`
`• The `045 Patent (and the publications incorporated by reference therein)
`
`and its file history;
`
`• Petition for Inter Partes Review of U.S. Patent No. 7,542,045 including
`
`all the exhibits [IPR2015-1502];
`
`• Patent Owner’s Preliminary Response in IPR2015-1502;
`
`• Decision on Institution in IPR2015-1502;
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`• U.S. Patent No. 5,546,547 to Bowes [Ex. 1003] (“Bowes”);
`
`• MPEG Standard [Ex. 1004] (also referred to as “MPEG”);
`
`• S. Rathnam et al., “An Architectural Overview of the Programmable
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`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON `96,
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`pp. 319-326 (1996) [Ex. 1005] (“Rathnam”);
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`• U.S Patent No. 5,774,676 to Stearns [Ex. 1007] (“Stearns”);
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`• Declaration of Harold S. Stone, Phd. [Ex. 1030] (“Stone Decl.”);
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`• DSP3210 Information Manual [Ex. 2001];
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`5
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`• AT&T DSP3210 Digital Signal Processor The Multimedia Solution,
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`Data Sheet, AT&T Microelectronics, March 1993
`
`[Ex. 2003]
`
`(“DSP3210 Datasheet”);
`
`• Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`
`660AV Computers [Ex. 2005] (“Quadra Developer Notes”);
`
`• Deposition testimony of Harold S. Stone, Phd. dated March 17, 2016
`
`[Ex. 2006] (“Stone Depo.”);
`
`• Excerpts from Stone, H.S., High-Performance Computer Architecture,
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`Addison-Wesley Publishing Company, Reading, Massachusetts, 1993,
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`ISBN 0-201-52688-3 [Ex. 2007];
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`• Kitson, F. and Bhaskaran, V., Interactive Video from Desktops to
`
`Settops, HPL-95-58, Hewlett-Packard white paper, June 1995 [Ex.
`
`2008].
`
`IV. Summary of Opinions
`
`14. As detailed below, it is my opinion that the challenged independent
`
`claims are not obvious in view of Bowes and the MPEG Standard and that the
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`challenged dependent claims are also not obvious for at least the same reasons.
`
`V. Legal Standards
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`6
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`15.
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`I am not an attorney or patent agent, and thus, I have relied upon
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`certain legal factors that have been explained to me. Some of these, which form the
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`legal framework for the opinions I am providing, are summarized below.
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`16.
`
`I understand that claims are to be interpreted from the perspective of
`
`one of ordinary skill in the art. I understand that in determining the level of
`
`ordinary skill in the art, the following factors may be considered: (1) the
`
`educational level of the inventor; (2) type of problems encountered in the art; (3)
`
`prior art solutions to those problems; (4) rapidity with which innovations are made;
`
`(5) sophistication of the technology; and (6) educational level of active workers in
`
`the field.
`
`17.
`
`I understand from reading the Board’s decision that in this inter partes
`
`review, claim terms are to be given their broadest reasonable construction in light
`
`of the patent specification. I also understand that claim terms are presumed to be
`
`given their ordinary and customary meaning as would be understood by one of
`
`ordinary skill in the art. Furthermore, I understand that an inventor may provide a
`
`contrary definition of a term in the specification, if it is done with reasonable
`
`clarity, deliberateness, and precision. I also understand that care must be taken not
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`to read a particular embodiment appearing in the specification into the claim if the
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`claim language is broader than the embodiment.
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`18.
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`I understand that a claim may be invalid as anticipated or as being
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`obvious. I understand that anticipation is not at issue in this IPR and therefore, my
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`analysis is focused on the obviousness issue.
`
`19.
`
`I understand that the obviousness standard is defined in the patent
`
`statute (35 U.S.C. § 103(a)). I also understand that a claim is not patentable and is
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`obvious if the differences between a claim and the prior art are such that the
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`claimed subject matter as a whole would have been obvious to a person having
`
`ordinary skill in the art at the time the invention was made. I understand that this
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`inquiry involves examination of number of factors including: (1) determining the
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`scope and content of the prior art; (2) ascertaining the differences between the
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`claim and the prior art; (3) resolving the level of ordinary skill in the prior art; and
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`(4) considering any secondary or objective evidence of non-obviousness. I
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`understand that secondary or objective evidence of non-obviousness include
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`factors such as commercial success, long felt need for the invention, and failure of
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`others.
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`20.
`
`I understand that an obviousness analysis involves comparing a claim
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`to the prior art to determine whether the claimed invention would have been
`
`obvious to a Person of Ordinary Skill in the Art (“POSA”) in view of the prior art,
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`and in light of the general knowledge in the art. I also understand when a POSA
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`would have reached the claimed invention through routine experimentation, the
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`invention may be deemed obvious.
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`21.
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`I also understand that obviousness can be established by combining or
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`modifying the teachings of the prior art to achieve the claimed invention. It is also
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`my understanding that where this is a reason to modify or combine the prior art to
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`achieve the claimed invention, there must also be a reasonable expectation of
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`success in so doing. I understand that the reason to combine prior art references
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`can come from a variety of sources, not just the prior art itself or the specific
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`problem the patentee was trying to solve. And I understand that the references
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`themselves need not provide a specific hint or suggestion of the alteration needed
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`to arrive at the claimed invention; the analysis may include recourse to logic,
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`judgment, and common sense available to a person of ordinary skill that does not
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`necessarily require explication in any reference. Finally, it is my understanding that
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`obviousness can be established by choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success.
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`22.
`
`I further understand that a patent composed of several elements is not
`
`proved obvious merely by demonstrating that each of its elements was,
`
`independently, known in the prior art. I further understand that a showing of a
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`suggestion, teaching, or motivation to combine the prior art references is an
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`essential evidentiary component of an obviousness conclusion. I further understand
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`that a claim is not obvious if the references relied upon in a proposed combination
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`teach away from the claimed combination in a way that would deter any
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`investigation into such a combination. For instance, it is my understanding that a
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`reference teaches way from a combination when using it in that combination would
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`produce an inoperative result.
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`VI. Level of Ordinary Skill in the Art
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`23.
`
`In formulating my opinions, I have also considered the viewpoint of a
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`person of ordinary skill in the art (“POSA”) at the time of the filing of the `045
`
`Patent.
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`24.
`
`I understand that Dr. Stone has opined that a person of ordinary skill
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`in the art as of the effective filing date of the `045 Patent would have held an
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`accredited Bachelor’s degree in Electrical Engineering and/or Computer Science
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`and/or Computer Engineering and had three years’ experience in the fields of data
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`compression and overall computer system architecture. [Stone Decl., Ex 1030,
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`¶79].
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`25. Based upon my knowledge of this field, I conclude that a person of
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`ordinary skill in this art at the time of the filing of the `045 Patent, and for that
`
`matter, at all subsequent times through the present, would have held at least an
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`accredited Bachelor’s degree in electrical engineering, computer engineering, or an
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`equivalent degree in a related discipline from an accredited institution of higher
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`10
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`learning and at least two to three years’ experience in signal and/or image
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`processing, computer architecture at both the systems and micro-architecture level.
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`In lieu of two to three years of experience, a person of ordinary skill in the art may
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`hold, in addition to a Bachelor’s degree as described above, a Master’s or other
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`graduate degree in electrical or computer engineering with a focus in computer
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`architecture and signal and/or image processing with one year of relevant
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`experience.
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`26. My analysis was performed from the perspective of such a person. If
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`I were to apply the level of ordinary skill as proffered by Dr. Stone in his
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`declaration, my analysis and conclusions would remain unchanged.
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`VII. State of the Prior Art and the `045 Patent
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`27. The computer memory storage requirements of a digital representation
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`of an uncompressed image is dependent on its resolution, color depth, and size in
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`pixels. Video files are comprised of sequences of images that are further enhanced
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`with a corresponding audio track to accompany them. As a result, a video file
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`quickly becomes large in size. The transmission of uncompressed video files is
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`prohibitively expensive.
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`28. Accordingly, video files are typically compressed at a transmitting
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`device. The compressed file is then transmitted to a receiving device where it is
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`decompressed. To that end, an encoder at the transmitter compresses the video file
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`and a decoder decompresses the file received at the receiver in order to retrieve the
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`original video and audio data. In order to ensure compatibility between devices, a
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`number of standards for encoding and decoding video files were developed. One of
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`those standards was developed by the Motion Picture Expert Group (“MPEG”) and
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`has been adapted as a standard for the communication of video.
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`29. Typically, a decoder requires its own dedicated memory. For instance,
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`traditional MPEG decoders require a 2 Mbyte dedicated memory which is utilized
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`during the decoding process. This dedicated memory is necessary to allow the
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`decoder to decode images in real-time without dropping frames which would result
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`in a deterioration of the video quality at the receiver. This prior art implementation
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`is shown, for example, in Figure 1c of the `045 Patent.
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`30. The `045 Patent discloses an improved system where the decoder and
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`another device (e.g., a microprocessor) share the main system memory. This
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`improved configuration eliminates the need for a dedicated decoder memory and
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`results in a more efficient utilization of main system memory by ensuring that
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`memory resources not used by the decoder remain available to other system
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`components.
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`VIII. Claim Construction
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`31.
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`I understand that the Board has construed the term “video decoder” to
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`mean “hardware and/or software
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`that
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`translates data streams
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`into video
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`information.” (Institution Decision, Paper 14, at 9-10).
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`32.
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`I understand that the Board has construed the term “fast bus” as “any
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`bus having a bandwidth sufficient to allow the system to operate in real time.”
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`(Institution Decision, Paper 14, at 11).
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`33.
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`I understand that with respect to the term “decoder directly supplies a
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`display device with an image” the Board concluded that an image is “directly
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`supplied” if it is “supplied without being stored in main memory for purposes of
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`decoding subsequent images.” (Institution Decision, Paper 14, at 12).
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`34.
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`I have used the Board’s construction of the term “decoder” in
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`performing my analysis. I have used the plain and ordinary meaning of the
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`remaining claim terms when performing my analysis.
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`IX. Analysis of Instituted Grounds
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`A. Claims 1, 4, 5, 7, 10, 12, 16 and 17
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`1) Bowes and MPEG Standard fail to disclose the decoder receiving
`data from the main memory corresponding to at least one previously
`decoded image [claims 1, 4, 5, 12]
`35. Figure 1c of the `045 Patent depicts a system having a decoder in
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`accordance with the prior art.
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`36. The system includes a number of components that are connected to a
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`peripheral bus (170) via interfaces. [`045 Pat., 2:56-63]. A Central Processing Unit
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`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
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`circuit (146) enabling the main memory (168) of the system to be shared between
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`the CPU (152) and other peripherals that may require it. [`045 Pat., 2:64-67].
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`Typically, one of the peripherals connected to the peripheral bus (170) as a master
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`is a decoder (10). [`045 Pat., 3:1-3]. The decoder (10) receives encoded or
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`compressed data from a source peripheral (22) and decodes that data. For instance,
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`if the data to be decoded is image data, the decoder then directs the decoded
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`images to a video controller (120) for display. [`045 Pat., 3:3-14].
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`37. Traditionally, the decoder (10) included its own dedicated memory
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`(22) which was divided into three image area buffers (M1, M2, M3) and a
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`Compressed Data Buffer (CDB) where the compressed image to be decoded is
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`stored before it is decoded. [`045 Pat., 3:14-19]. Typically, the decoding of images
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`under the MPEG Standard involves processing of “I”, “P” and “B” frames. “I”
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`frames are so called “intra” image frames whose compressed data directly
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`corresponds to an actual image. [`045 Pat., 3:22-23]. “P” frames are so called
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`“predicted” image frames the construction of which uses pixel blocks of a
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`previously decoded image frame. [`045 Pat., 3:23-25]. Finally, “B” frames are so
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`called “bidirectional” image frames the construction of which uses pixel blocks
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`from two previously decoded images. [`045 Pat., 3:26-28]. Accordingly, the “I”
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`and “P” image frames are required to be used to reconstruct subsequent “P” and
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`“B” frames while “B” frames are not used to decode subsequent image frames.
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`[`045 Pat., 3:28-30].
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`38. Figure 1c depicts how a prior art decoder (10) uses the buffers M1,
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`M2, and M3 of its dedicated memory (22) during the decoding process. [`045 Pat.,
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`3:28-30; 3:40-60]. Accordingly, in prior art systems, although the system included
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`a main memory (168) which the decoder (10) could access via the peripheral bus
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`(170), the decoder (10) utilized its local dedicated memory (22) not the main
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`memory (168) when decoding an image. Specifically, an image to be decoded was
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`stored in the CDB of the dedicated memory (22). The decoder (10) then received
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`the image to be decoded from the CDB in its dedicated memory (22). The decoder
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`(10) also received a previously decoded image (i.e., an “I” image frame or a “P”
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`image frame) from the buffers (M1, M2, M3) in its dedicated memory (22). The
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`decoder (10) then used the previously decoded image (i.e., the “I” or “P” image
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`frame) to decode the image to be decoded using, for example, the MPEG decoding
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`standard. The use of this dedicated memory (22) allowed the decoder (10) to
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`decode a compressed image without having to access the main memory and
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`avoided dropping image frames while preserving the available bandwidth on the
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`peripheral bus (170). [`045 Pat., 3:60-4:48].
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`39. The `045 Patent discloses an improved system which allows the
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`decoder and a first device (e.g., a CPU) to share the main system memory when
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`decoding an image and eliminates the need for a dedicated memory for the
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`decoder.
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`40.
`
` Figure 4 of the `045 Patent depicts an embodiment of the claimed
`
`invention where the decoder/encoder (80) shares the main memory (168) with
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`other peripheral devices (e.g., the CPU (152)). [`045 Pat., 10:14-17]. As shown in
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`Figure 4, the decoder/encoder (80) does not have a dedicated memory and instead
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`uses a region (22’) of the main memory (168) of the system for the decoding
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`process. [`045 Pat., 10:24-26]. The region (22’) of the main memory (168) includes
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`a Compressed Data Buffer (CDB) into which the image source (122) writes a
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`compressed image (i.e., an image to be decoded) and two image buffers M1, and
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`M2 associated with “I” and “P” image frames (i.e., previously decoded images).
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`[`045 Pat., 10:27-30]. The third buffer (M3) used in dedicated memory of prior art
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`decoders has been eliminated and the “B” frames which are not used to decode
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`other images are directly supplied to the display adapter (120) as they are being
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`decoded. [`045 Pat., 10:30-33].
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`
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`41. Accordingly, in the improved system of the `045 Patent an image to
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`be decoded is directed from the source (122) to the CDB in the main memory
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`(168). [`045 Pat., 10:34-36]. This image to be decoded is transferred from the CDB
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`in the main memory (168) to the decoder/encoder (80) over the peripheral bus
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`(170) and is decoded by the decoder. [`045 Pat., 10:36-39]. If the decoded image is
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`an “I” image frame or a “P” image frame, the decoder/encoder (80) retransmits the
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`decoded image to buffers M1 and M2 in the main memory (168). [`045 Pat., 10:36-
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`39]. These “I” and “P” image frames may then be transmitted from the buffers M1
`
`and M2 in the main memory (168) back to the decoder and used in decoding of
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`subsequent “P” or “B” image frames or may be transmitted to the display adapter
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`(120) for display. [`045 Pat., 10:44-47]. If an image to be decoded corresponds to a
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`“B” image frame, the decoder/encoder (80) decodes the image and directly
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`supplies it to the display adapter (120) without storing it in the main memory (168)
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`if it is ready for display in the display sequence time frame. [`045 Pat., 10:39-44].
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`42. Accordingly, in the improved system disclosed in the `045 Patent, the
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`decoder’s dedicated memory is eliminated and instead, the decoder receives an
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`image to be decoded (i.e., compressed image stored in CDB) and a previously
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`decoded image (i.e., “I” image frames or “P” image frames stored in M1 and M2)
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`from a region 22’ in the main memory (168). These “I” and “P” image frames may
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`then be utilized in decoding of subsequent “P” or “B” image frames by the
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`decoder. [`045 Pat., 10:61-64].
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`43. Consistent with this improvement, independent claims 1, 4, 5 and 12
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`recite a [video] decoder configured to receive data from the [main]/[system]
`
`memory corresponding to at least one previously decoded [video] image and to a
`
`current [video] image to be decoded.
`
`44. The Petitioner relies on the combination of Bowes and the MPEG
`
`Standard for disclosing a [video] decoder that receives a previously decoded
`
`[video] image from the main memory. First, as discussed below, a POSA would
`
`not have been motivated to combine Bowes and the MPEG Standard. Moreover,
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`even if a POSA were to combine Bowes with the MPEG Standard, such a
`
`combination would not disclose a video circuit that receives a previously decoded
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`18
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`Page 19 of 67
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`video image from the main memory for at least three reasons: (1) Bowes’ DSP is
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`not a video decoder; (2) if such a combination was made, a POSA would have
`
`stored a previously decoded image in the dedicated memory of the Bowes’ DSP (as
`
`in the prior art disclosed in the `045 Patent); and (3) Bowes does not disclose the
`
`DSP writing data into the main memory and then reading the same data from the
`
`main memory.
`
`BOWES’ DSP IS NOT A “VIDEO DECODER”
`
`45.
`
`I understand that the Petitioner has identified the DSP (20) of Bowes
`
`as being analogous to the video circuit recited in the `045 Patent. [Petition at 36].
`
`The word “video” is only mentioned four times in Bowes. [Bowes, 1:34; 1:37;
`
`1:41; 6:16]. The first three times the term “video” is used in conjunction with a
`
`description of related art and the fourth time, the term “video” is used in reference
`
`to a NuBus peripheral bus video controller and not in reference to a processing
`
`application. The words “decode” or “decoding” never appear in Bowes.
`
`46.
`
`Instead, Bowes specifically teaches that the DSP in the preferred
`
`embodiment is suitable for audio processing, image signal processing, speech
`
`processing, and modem emulation. [Bowes Pat., 1:48-49; 6:32-37]. Bowes does
`
`not state that the DSP is suitable for video compression and decompression
`
`applications such as the implementations of the MPEG Standard. A POSA would
`
`recognize that audio processing, speech processing and modem emulation are
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`19
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`Page 20 of 67
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`clearly distinct from video compression and decompression. The same is true with
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`respect to “image processing.”
`
`47. Dr. Stone, Petitioner’s expert, defines “image processing” in his
`
`textbook as “a computation performed on a digitized representation of an image
`
`whose purpose is to enhance the image or to extract information about the image.”
`
`[Ex. 2007 at 499]. This textbook was published in 1993 and accurately reflects
`
`how a person of skill in the art would have understood the term “image
`
`processing” as of the priority date of the `045 Patent. In contrast, the MPEG
`
`Standard is directed to compressing and decompressing video sequences. [Ex.
`
`1004, p. 4]. Such a compression and decompression of video sequences is wholly
`
`different from
`
`image processing. For example, video compression and
`
`decompression requires maintaining the temporal relationship between consecutive
`
`image frames, an important concept that is absent when processing a single image.
`
`[See Stone Deposition, 102:19-104:5].
`
`48. There are additional reasons why a POSA would recognize that a DSP
`
`used for
`
`image processing
`
`is not suitable for video compression and
`
`decompression. Specifically, image processing requires precision and involves a
`
`host of arithmetic operations. In contrast, the primary concern in video
`
`compression and decompression is speed to ensure that video is delivered to
`
`viewer in real time. Therefore, video compression and decompression processes
`
`20
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`Page 21 of 67
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`typically do not require the same level of precision and arithmetic operations as
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`image processing. As a result, a POSA would typically use a different type of DSP
`
`for image processing as compared to video compression and decompression.
`
`Specifically, the internal architecture of a DSP may be categorized according to the
`
`type of numerical format it utilizes. A “floating point” DSP utilizes a format
`
`wherein a single value is specified with three fields, a sign field indicating whether
`
`the value is positive or negative; a mantissa or significand field indicating the
`
`precision of the value; and a signed exponent field indicating the magnitude. In
`
`contrast, a “fixed point” DSP utilizes a format wherein a single value represents
`
`the signed value using an appropriate signed value encoding such as 2’s
`
`complement and where the binary- or radix point is in a “fixed” position.
`
`49. That the DSP (20) of Bowes is not suitable for video compression and
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`decompression is further evident from the fact that Bowes states that in a preferred
`
`embodiment, the DSP (20) of Bowes is the AT&T DSP3210. [Bowes, 6:28-30].
`
`Such a DSP is not suitable for MPEG video decoding because it is a floating point
`
`DSP. [Ex. 2003, at 1]. Specifically, the AT&T DSP3210 utilizes a floating-point
`
`Data Arithmetic Unit (DAU) that “is the primary execution unit for signal
`
`processing algorithms.” [Ex. 2003, at 5].
`
`50. Due to its use of a more complex format, a floating point DSP
`
`generally incurs increased latency but provides increased accuracy and dynamic
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`Page 22 of 67
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`range (i.e., it can represent a wider range of numerical values). In contrast, a fixed
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`point DSP allows higher performance but at the expense of decreased accuracy and
`
`dynamic range. Therefore, a POSA would appreciate that a floating point DSP is
`
`not well-suited for video compression and decompression. [See, also, Stone Depo.,
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`Ex. 2006, 201:20-202:7].
`
`51. A POSA would appreciate that MPEG decoding is a high throughput
`
`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
`
`VLD, de-quantization, and other processes. Floating-point DSPs (such as the
`
`DSP3210) provide for higher dynamic range and more accuracy in their
`
`computations, but at the expense of increased latency whereas a fixed point DSP
`
`requires shorter internal data paths providing for performance advantages. While it
`
`may appear that the increased accuracy provided by floating-point DSPs would be
`
`advantageous in IDCT operations, for video and specifically MPEG video
`
`decompression, the IDCT operations are performed over relatively short bit-exact
`
`data that ultimately represents a pixel value, thus increased precision as provided
`
`by a more costly floating-point DSP would offer no advantage when used as an
`
`MPEG video decoder. Further, the other intensive processes require a considerable
`
`amount of control instructions to be executed rather than arithmetic instructions
`
`(e.g., table lookups). A POSA would therefore recognize that a floating point DSP
`
`(such as the DSP3210 of Bowes) is not well-suited for MPEG video decoding.
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`22
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`Page 23 of 67
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`Indeed the disclosed and intended applications of the DSP in the preferred
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`embodiments of Bowes are those that would require the extended dynamic range
`
`and precision provided by a floating point DSP such as audio, image processing,
`
`speech processing, and modem emulation. [Bowes Pat., 1:48-49; 6:32-37].
`
`52. Moreover, floating-point processors are incompatible with MPEG
`
`decoding due to the format of the encoded and decoded MPEG video data as in the
`
`MPEG standard and the H.262 specifications. The video data as per the standard
`
`and specification is not in the form of floating point values and would require
`
`conversions to floating-point prior to decoding and a conversion back to its initial
`
`format after decoding. A POSA would recognize that these conversions would
`
`incur additional processing delay that would be otherwise unnecessary if a fixed-
`
`point DSP were used. Floating-point values require that the significand fall within
`
`a numerical range between 1 and 2, with the exponent field used to indicate the
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`actual location of the binary-point. Thus, all input encoded MPEG values would
`
`need to be converted to this floating-point format before processing, and the
`
`resulting decoded values would have t
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