CHAPTER 2
`
`Hardware Details
`
`The pin assignments for the 96-pin Euro-DIN NuBus accessory card connectors in the
`NuBus interface are shown in Table 2-17.
`
`Table 2-17
`
`NuBus pin assignments
`
`Pin
`
`a1
`
`a2
`
`a3
`
`a4
`
`a5
`
`a6
`
`a7
`
`a8
`
`a9
`
`a11
`
`a12
`
`a13
`
`a14
`
`a15
`
`a16
`
`a17
`
`a18
`
`Name
`
`—12V
`
`5130
`
`/SPV
`
`/51>
`
`/TM1
`
`/AD1
`
`/AD3
`
`/AD5
`
`/AD7
`
`/AD9
`
`/AD11
`
`/AD13
`
`/AD15
`
`/AD17
`
`/AD19
`
`/AD21
`
`/AD23
`
`/AD25
`
`/AD27
`
`/AD29
`
`/AD31
`
`GND
`
`GND
`
`/ARB1
`
`/ARB3
`
`/GA1
`
`/GA3
`
`/ACK
`
`Pin
`
`b1
`
`b2
`
`b3
`
`b4
`
`b5
`
`b6
`
`b7
`
`b8
`
`b9
`
`Name
`
`—12V
`
`GND
`
`GND
`
`+5V
`
`+5v
`
`+5V
`
`+5v
`
`/TM02
`
`/CMO
`
`/CM1
`
`b11
`
`/CM2
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`GND
`
`/cL1<2x
`
`STDBYPWR+
`
`/CLKZXEN
`
`/CBUSY
`
`+5v
`
`NuBus Interface
`
`Page 67 of 500
`
`continued
`
`41
`
`PUMA EXHIBIT 200
`
`PART 2 OF 10
`
`Page 67 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Table 2-17
`
`NuBus pin assignments (continued)
`
`Pin
`
`a29
`
`a3O
`
`a31
`
`a32
`
`Name
`
`+5V
`
`/ RQST
`
`/ NMRQX
`
`+12V
`
`Pin
`
`b29
`
`b30
`
`b31
`
`b32
`
`Name
`
`+5V
`
`GND
`
`GND
`
`+12V
`
`Pin
`
`C29
`
`C30
`
`C31
`
`C32
`
`* A slash before a signal name indicates that it is in the low state when active.
`J‘ Trickle +5 V supply.
`
`The power available and maximum capacitance loading for each expansion card are
`shown in Table 2-18.
`
`Table 2-18
`
`Power budget for each slot card
`
`Maximum
`
`Maximum
`
`Voltage (V)
`+5
`
`current (A)
`2.0
`
`capacitance (uF)
`1513
`
`+12
`
`-12
`
`0.175
`
`0.15
`
`536
`
`698
`
`Digital AudioNideo Expansion Connector
`
`In the Macintosh Quadra 840AV, a digital audio / Video (DAV) expansion connector is
`mounted on the main circuit board in line with NuBus slot address $C (the slot nearest
`
`the center of the computer), to let an accessory card access sound and video data directly.
`In the Macintosh Centris 660AV, the DAV connector is mounted on the optional NuBus
`adapter card (shown in Figure 2-13). Both models can accept a short NuBus accessory
`card that accesses the DAV connector; the Macintosh Quadra 840AV can also accept a
`long card.
`
`Figure 2-14 illustrates the lower-right portion of a standard short or long NuBus card
`that has a connector added to plug into the DAV connector. It shows the mechanical
`relation between the DAV connector and the normal NuBus connector, with dimensions
`
`given in inches.
`
`The DAV connector provides access to the system's 4:2:2 unsealed YUV video input
`signal and to the digital audio signal input for the Singer codec. One use for this feature
`is to provide a hardware audio or Video compression capability on an accessory card,
`which could write out compressed data to NuBus. The DAV connector is a 40-pin type,
`model KEL 8801-40-170L. Table 2-19 gives its pin assignments.
`
`NuBus Interface
`
`Page 68 of 500
`
`Page 68 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Figure 2-14
`
`DAV connection on a NuBus card
`
`Long board
`
`0
`
`Short board
`
`Table 2-19
`
`DAV connector pin assignments
`
`Pin
`15
`
`Signal
`Y bit 0
`
`'
`
`Signal
`UV bit 1
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
`28
`
`Ground
`
`UV bit 7
`
`FEI~
`
`UV bit 6
`
`Ground
`
`UV bit 5
`
`iicSDA
`
`UV bit 4
`
`Ground
`
`UV bit 3
`
`iicSCL
`
`UV bit 2
`
`Ground
`
`NC (reserved)
`
`UV bit 0
`
`Ground
`
`SingerSync
`
`Ground
`
`SingerSerOut
`
`SingerBitClk
`
`SingerSerIn
`
`Ground
`
`Ground
`
`SingerMClk
`
`3 :
`
`O\O0O\‘lO'\0‘Ii-l>QJNi—\
`
`l-\
`
`l-\l-\
`
`l--\I0
`
`I-4CD
`
`I-4rl>-
`
`Signal
`Y bit 7
`
`LLC1k
`
`Y bit 6
`
`Ground
`
`Y bit 5
`
`VS
`
`Y bit 4
`
`Ground
`
`Y bit 3
`
`HRef
`
`Y bit 2
`
`Ground
`
`Y bit 1
`
`vdcCRef
`
`NuBus Interface
`
`Page 69 of 500
`
`Page 69 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`DAV Sound Interface
`
`The Singer sound codec uses time-division multiplexing to transfer multiple audio
`channels between the DAV connector, the Singer chip, and the PSC for DMA transfers to
`and from RAM memory. The sound signals that appear at the DAV connector are listed
`in Table 2-20. These signals have a minimum setup time of 10 ns and a minimum hold
`time of 8 ns; they can tolerate a maximum load of 20 pF.
`
`Table 2-20
`
`DAV connector sound signals
`
`Signal
`
`singerMC1k
`
`singerBitClk
`
`Description
`24.576 MHz master clock
`
`Bit clock that clocks serial data on singerSerOut and singerSerIn;
`256 times the sample rate; also used to clock singersync
`
`singerSync
`
`Signal that marks the beginning of a frame and a word
`
`singerSerOut
`
`Sound output from PSC to DAV connector
`
`singerSerIn
`
`Sound input from DAV connector to PSC
`
`The Singer codec transfers data in 256-bit frames, each of which contains four subframes
`of 64 bits each. Each subframe carries two 32-bit audio samples, one left and one right.
`Each sample contains 20 data bits and 12 auxiliary bits. Subframe 1 is reserved for the
`Macintosh system sound I/ O; the other subframes are available for applications and
`accessory cards to use. The Singer frame structure is shown in Figure 2-15
`
`Figure 2-15
`
`Singer sound frame
`
`256 bits
`I
`
`Subframe 1
`
`Subframe 2
`
`Subframe 3
`
`Subframe 4
`
`W
`
`Word syncs
`
`(
`
`Frame
`sync
`
`Left channel (20) bits
`
`(aux. 12 bits)
`
`Right channel (20 bits)
`
`(aux. 12 bits)
`
`NuBus Interface
`
`Page 70 of 500
`
`Page 70 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`The signals singerSync, singerSerOut, and singerSerIn are clocked by the singerBitClk
`signal. The falling edge of the clock is used to clock the signals, and the rising edge is
`used to sample them. As shown in Figure 2-16, a frame sync is marked by a pulse two
`singerBitClk cycles wide; a word sync is marked by a pulse one singerSync cycle wide.
`
`Figure 2-16
`
`Sound frame and word synchronization
`
`256
`
`1
`
`2
`
`3
`
`singerBitC|k
`
`I
`
`I
`
`I
`
`J
`
`I
`
`singerSync
`
`I
`
`I
`
`I
`
`Word
`
`The singerSync synchronization signals for each subframe are shown in Figure 2-17.
`
`Figure 2-17
`
`Sound subframe synchronization
`
`Frame = 256 singerBitC|k cycles
`I
`
`Subframe 1
`64 bits
`I
`
`I
`
`Y
`
`Subframe 2
`64 bits
`I
`
`I
`
`I
`
`I
`
`Subframe 3
`64 bits
`
`I
`
`Subframe 4
`64 bits
`I
`
`I
`
`I
`
`Y
`
`I
`
`singersync
`
`IIIIIIII
`
`Word syncs
`
`DAV Video Interface
`
`At the DAV connector, the digital video signal data format conforms to CCIR
`Specification 601 and is compatible with most Video compression chips. In the DAV
`interface, Video lines are defined by the HRef signal; it goes high during the image
`transmission and low during the blanking interval. The DAV video signal timing
`relations are shown in Figure 2-18.
`
`NuBus Interface
`
`Page 71 of 500
`
`Page 71 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Figure 2-18
`
`DAV video timing
`
`Start of a video line
`
`HRef_
`
`—> Y and UV data valid on the rising edge of conLLC|k
`when HRef and CRef are high
`
`End of a video line
`
`HRef_
`
`Processor-Direct Cards for the Macintosh Centris 66OAV
`
`The Macintosh Centris 66OAV (but not the Macintosh Quadra 840AV) can accept an
`accessory card that plugs directly into the main circuit board instead of into the adapter
`card shown in Figure 2-13. An accessory card plugged into the main circuit board can
`gain access to the processor as well as to the DAV bus. The resulting processor—direct slot
`(PDS) capability is similar to that of the Macintosh Centris 610 computer, described in
`the Macintosh Centris 610 Developer Note.
`
`The Macintosh Centris 610 computer uses an AMP type 650231-5 connector for PDS
`cards; the Macintosh Centris 66OAV uses an AMP type 650231-3 connector. Because
`the corresponding pins are aligned, it is possible to design PDS cards that work on
`both models.
`
`Processor-Direct Cards for the Macintosh Centris 66OAV
`
`Page 72 of 500
`
`Page 72 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`The Macintosh Centris 660Av PDS Connector
`
`The pin assignments for the Macintosh Centris 660AV PDS connector are given in
`Table 2-21. Pin numbers preceded by an asterisk have signals that are different from
`those in the Macintosh Centris 610. Pin numbers preceded by a minus sign are not used
`by the Macintosh Centris 660AV.
`
`Table 2-21
`
`Macintosh Centris 660AV PDS connector pin assignments
`
`Pin number
`
`Signal name
`
`Pin number
`
`Signal name
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`38
`
`+5 V
`
`D(19)
`
`D(17)
`
`GND
`
`D(14)
`
`D(13)
`
`13(11)
`
`13(9)
`
`D(8)
`
`D(6)
`
`D(4)
`
`+5 V
`
`13(1)
`
`GND
`
`Am
`
`AG)
`
`A(4)
`
`A(6)
`
`A(7)
`
`A(9)
`
`A(11)
`
`A(13)
`
`A(15)
`
`GND
`
`A(18)
`
`1 2 3 4 5 6 7 8 9
`
`l-\ ®
`
`I-4I-\
`
`I--\I0
`
`l-—|03
`
`l--\I-P
`
`l-—|U1
`
`l-—| C'\
`
`1-1 \1
`
`l--\ ®
`
`1-1 \O
`
`[UG
`
`N1-1
`
`I\-)I0
`
`IQDJ
`
`IQ11>-
`
`NJ()1
`
`A(19)
`
`A(21)
`
`A(23)
`
`A(24)
`
`A(26)
`
`A(29)
`
`A(31)
`
`D(31)
`
`D(29)
`
`D(27)
`
`D(25)
`
`D(24)
`
`D(22)
`
`39
`
`40
`
`41
`
`-42
`
`*43
`
`44
`
`*45
`
`*46
`
`47
`
`-48
`
`49
`
`*50
`
`GND
`
`SIZE(1)
`
`RW
`
`/TIP.CPU*
`
`GND"
`
`/ TEA
`
`/ NC
`
`GND
`
`/TRST
`
`/CI.OUT
`
`GND
`
`NC
`
`continued
`
`Processor-Direct Cards for the Macintosh Centris 660AV
`
`Page 73 of 500
`
`Page 73 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Table 2-21
`
`Macintosh Centris 660AV PDS connector pin assignments (continued)
`
`Pin number
`
`Signal name
`
`Pin number
`
`Signal name
`
`-51
`
`52
`
`53
`
`54
`
`55
`
`56
`
`*57
`
`58
`
`59
`
`60
`
`61
`
`62
`
`63
`
`/ BR.40SLOT
`
`/ BB
`
`/LOCK
`
`/MEM.RESET
`
`/ CPURESETOUT
`
`+5 V
`
`040INPROGRESS
`
`/ NMRQ(6)
`
`GND
`
`/ IPL(0)
`
`/ IPL(1)
`
`/IPL(2)
`
`—12V
`
`82
`
`83
`
`84
`
`35
`
`86
`
`87
`
`88
`
`89
`
`90
`
`91
`
`92
`
`93
`
`94
`
`95
`
`A(17)
`
`+5 V
`
`A(20)
`
`A(22)
`
`GND
`
`A(25)
`
`A(27)
`
`A(28)
`
`A(30)
`
`D(30)
`
`D(28)
`
`D(26)
`
`GND
`
`D(23)
`
`64
`
`*65
`
`*66
`
`*67
`
`*68
`
`*69
`
`70
`
`71
`
`72
`
`73
`
`74
`
`75
`
`76
`
`77
`
`78
`
`79
`
`80
`
`81
`
`96
`
`97
`
`98
`
`99
`
`100
`
`101
`
`102
`
`GND
`
`NC
`
`NC
`
`/NMRQ(5)
`
`/NMRQ(4)
`
`/04OLOCKE
`
`+5 V
`
`AUX.CPUCLK
`
`A(0)
`
`A(2)
`
`+5 V
`
`A(5)
`
`GND
`
`A(8)
`
`A(10)
`
`A(12)
`
`A(14)
`
`A(16)
`
`D(21)
`
`D(20)
`
`D(18)
`
`D(16)
`
`D(15)
`
`+5 V
`
`D(12)
`
`D(10)
`
`GND
`
`D(7)
`
`D(5)
`
`D(3)
`
`D(2)
`
`D(0)
`
`SIZE(0)
`
`+5 V
`
`+5 V
`
`Processor-Direct Cards for the Macintosh Centris 660AV
`
`Page 74 of 500
`
`Page 74 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Table 2-21
`
`Macintosh Centris 660AV PDS connector pin assignments (continued)
`
`Pin number
`
`Signal name
`
`Pin number
`
`Signal name
`
`113
`
`114
`
`115
`
`*116
`
`*117
`
`*118
`
`-119
`
`120
`
`121
`
`122
`
`123
`
`124
`
`-125
`
`-126
`
`/ TA
`
`GND
`
`/ TS
`
`GND
`
`+5 V
`
`+5 V
`
`/ BG.4OSLOT
`
`/ BG.CPU
`
`+5 V
`
`TT(0)
`
`TT(1)
`
`GND
`
`TLN (0)
`
`TLN (1)
`
`127
`
`-128
`
`-129
`
`-130
`
`131
`
`*132
`
`133
`
`134
`
`135
`
`136
`
`*137
`
`*138
`
`139
`
`140
`
`/ SYS.RESET
`
`TM(0)
`
`TM(1)
`
`TM(2)
`
`+5 V
`
`NC
`
`+12V
`
`GND
`
`BS.CLK
`
`/BS.MODE
`
`MUNI / RQ
`
`NC
`
`reserved
`
`+5 V
`
`* A slash before a signal name indicates that it is in the low state when active.
`J’ GND on pin 43 identifies the Macintosh Centris 660AV; on the Macintosh Centris 610 pin 43 is
`not connected.
`
`Most of the signals listed in Table 2-21 are connected directly to the computer's
`processor. Table 3-22 lists the PDS signals that are connected to the computer's processor
`but that should not be connected to a processor on a PDS card. Table 3-23 lists the PDS
`signals that are not directly connected to the computer's processor.
`
`Table 3-22
`
`Restricted microprocessor signals on the PDS connector
`
`Signal name
`
`Direction
`9:
`
`Function
`
`/ IPL(0—2)
`
`I
`
`/ TIP.CPU
`
`*1 indicates input to the PDS card.
`
`Interrupt priority lines from the PSC; not to be used as
`wire-OR lines; can be monitored by a PDS card
`
`From the MC68040 on the main circuit board; not
`connected to any other part of the computer
`
`Observe the following additional cautions when designing PDS cards for the Macintosh
`Centris 660AV:
`
`Processor-Direct Cards for the Macintosh Centris 660AV
`
`Page 75 of 500
`
`Page 75 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Table 3-23
`
`Nonmicroprocessor signals on the PDS connector
`
`Direction
`
`Function
`
`I/0*
`
`Enables PDS to drive system reset signal; used only
`for testing
`
`Buffered version of main processor's bus clock (BClk)
`
`Bus grant for main processor
`
`Bus grant for PDS card
`
`Bus request for PDS card
`
`Fast reset generated for memory controller IC
`
`Memory inhibit from PDS card to memory
`controller IC
`
`NuBus slot $E interrupt; also connected to
`NuBus slot $E
`
`I
`
`O I
`
`O I 0
`
`O
`
`Signal name
`
`/SYS.RESET
`
`AUX.CPU.CLK
`
`/ BG.CPU
`
`/ BG.40SLOT
`
`/ BR.40SLOT
`
`/ MEM.RESET
`
`/ MI.SLOT
`
`/ NMRQ(6)
`
`*
`
`I indicates input to the PDS card; 0 indicates output from the PDS card.
`
`Most signals on the PDS connector are connected directly to the main processor
`with no buffers. Therefore, the PDS card must present capacitive loads of not more
`than 40 pF on the address, data, and clock lines and not more than 20 pF on the
`control lines.
`
`The AUX.CPUCLK line (pin 71) is terminated with a series resistor. To reduce
`reflections on this line, all loads on the card should be lumped.
`
`/DLE (pin 45) is not connected because DLE-type read actions are not supported by
`some Macintosh Centris 66OAV bus masters.
`
`The Macintosh Centris 66OAV does not support snooping; pins 46 and 116 are
`grounded.
`
`/ BR.CPU (pin 50) is not connected because the Macintosh Centris 66OAV system bus
`arbiter always grants bus control to the microprocessor when there are no other
`high-priority bus requests.
`
`The Macintosh Centris 66OAV does not support /BG.4OSLOT (pin 119) and /
`BR.4OSLOT (pin 51) because it does not support using an accessory card as a bus
`master in addition to the existing bus masters (the processor, the DSP, the PSC, and
`the MUNI).
`
`/ TBI (pin 112) is connected to +5 V because the TBI signal is not allowed by some
`bus masters.
`
`/ PDS.SLOT.E.EN (pin 132) is not connected because the MUNI is programmed to
`decode or ignore individual slots.
`
`The 040INPROGRESS signal (pin 57) is high when the main processor is the bus master.
`When this signal is low, a different bus master can use the alternate burst write timing
`protocol described in the next section.
`
`Processor-Direct Cards for the Macintosh Centris 66OAV
`
`Page 76 of 500
`
`Page 76 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Processor Bus Burst Write Timing
`
`The Macintosh Centris 660AV computer's processor bus supports two different timing
`protocols for burst write actions. When pin 57 of the PDS connector is high, the main
`processor is bus master and burst write actions must use the timing shown in the
`top half of Figure 2-19. When pin 57 of the PDS connector is low, an alternate bus
`master may perform burst write actions using the timing shown in the bottom half
`of Figure 2-19.
`
`Figure 2-19
`
`Burst write timing
`
`Motorola 68040 burst write timing
`
`S|Z[1:O] (burst)
`
`TA
`
`o[31:o]
`
`S|Z[1:O] (burst)
`
`TA
`
`D[31:O]
`
`Processor-Direct Cards for the Macintosh Centris 660AV
`
`Page 77 of 500
`
`Page 77 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`RAM Expansion Cards
`
`The user can expand RAM capacity by inserting 72-pin SIMM cards in RAM expansion
`slots. Table 3-24 shows the RAM SIMM pin assignments.
`
`Table 3-24
`
`RAM SIMM pin assignments
`
`Pin
`
`Name
`
`Pin
`
`Name
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`DQ22
`
`DQ7
`
`DQ23
`
`A7
`
`NC
`
`A8
`
`A9
`
`/ RAS3*
`
`/ RAS2
`
`Reserved
`
`Reserved
`
`49
`
`50
`
`51
`
`52
`
`53
`
`54
`
`55
`
`56
`
`59
`
`60
`
`DQ8
`
`DQ24
`
`DQ9
`
`DQ25
`
`DQ10
`
`DQ26
`
`DQ11
`
`DQ27
`
`DQ12
`
`DQ28
`
`+5V
`
`DQ29
`
`Name
`
`GND
`
`DQ0
`
`DQ16
`
`DQ1
`
`DQ17
`
`DQ2
`
`DQ18
`
`DQ3
`
`DQ19
`
`+5V
`
`NC
`
`A0
`
`'_°. :3
`
`1 2 3 4 5 6 7 8 9
`
`I-1 O
`
`l—|I-—‘
`
`I-1 N
`
`I-1 U)
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`NC
`
`DQ4
`
`DQ20
`
`DQ5
`
`DQ21
`
`DQ6
`
`I-1IF
`
`I-1 U1
`
`|—\ ON
`
`I-1 \l
`
`I—\ X
`
`|—\ \D
`
`I\)O
`
`NI-1
`
`I\)I\)
`
`IOU)
`
`24
`
`37
`
`38
`
`39
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`48
`
`Reserved
`
`Reserved
`
`GND
`
`/ CASO
`
`/ CAS2
`
`/ CAS3
`
`/ CAS1
`
`/ RASO
`
`/ RAS1
`
`NC
`
`WE
`
`NC
`
`61
`
`62
`
`63
`
`64
`
`65
`
`66
`
`67
`
`68
`
`69
`
`70
`
`71
`
`72
`
`DQ13
`
`DQ30
`
`DQ14
`
`DQ31
`
`DQ15
`
`NC
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`
`Reserved
`
`GND
`
`* A slash before a signal name indicates that it is in the low state when active.
`
`RAM Expansion Cards
`
`Page 78 of 500
`
`Page 78 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Figure 2-20 shows the mechanical dimensions of SIMM modules for expanding RAM.
`Dimensions are given in millimeters, with inch equivalents in brackets.
`
`Figure 2-20
`
`RAM SIMM mechanical dimensions
`
`R1.5710.1
`[.062 1 .004]
`
`32.0 [1.26]
`
`10161020
`[.400 1 .003]
`6.35 1 0.20
`
`[.250 1 .003]
`
`i
`(6.35) T
`
`[.250]
`
`t
`
`1
`
`2.03 1 0.20
`[.080 1 .008]
`
`SEE DETAIL A /(
`
`35 x 1.27 [.050] =
`44.45 1 0.20
`[1.75 1 .008]
`
`5-35i°-05
`[.250 1 .002]
`
`€19 0.10 [.004] M A B
`
`R 1.57 1 0.12
`[.062 1 .005]
`
`35 x 1.27 [.050] =
`44.45 1 0.20
`[1 .75 1 .008]
`
`+ 0.17
`0'90 -0.03
`j .035 "-003]
`* L
`‘-003
`2.54[.100]
`
`<_ 127 1 0'10
`[050 i 004]
`
`DETAIL A
`ROTATED 90°CCW
`
`RAM Expansion Cards
`
`2x Q3.18 1 0.1
`[.125 1.004]
`
`F
`E 9.4 [.37] X
`MAX
`
`Page 79 of 500
`
`+0.10
`F127 _()_()8
`j? £050 + .004]
`
`— .003
`
`'
`
`Device on this
`side optional.
`
`Page 79 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`Because of signal loading limits, there may not be more than eight chips per bank of
`RAM; composite SIMM cards cannot be used.
`
`The Macintosh Quadra 840AV also accepts SIMM cards of a different configuration to
`expand its VRAM, as shown in the next section.
`
`VRAM Expansion Cards
`
`The Macintosh Quadra 840AV lets the user expand VRAM capacity by inserting 68-pin
`SIM cards in its two VRAM expansion slots. Figure 2-21 shows the mechanical
`dimensions of SIMM modules for expanding VRAM, which are different from the RAM
`cards discussed in the previous section. Dimensions are given in millimeters, with inch
`equivalents in brackets.
`
`Figure 2-21
`
`VRAM SIMM mechanical dimensions
`
`.—1o2.s7[4.o5o1 I 0.15[.D06] ® A. ——
`95.11 1 6410 [3.784 ¢.oo4]
`
`2x 3.151.124] —> <—
`MIN
`
`5.35
`[250]
`
`$- o.1o[.oo4] ®A|s
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`[.062 1 .002]
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`
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`
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`10.15 : 0.08
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`
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`
`‘: 635 1: 0.03 [.250 1001]
`
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`«er 2x 34 EQSPACES
`I
`@ 127 1 one [.050 ¢ .001]
`= 41.92 [1 5501
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`
`«j 90.17 : 0405 [3550 : .0021
`
`H} o.1o[.oo4] ® A B
`
`—» <— s8x1.o4 2 0.03
`[.041 1 .001]
`
`|$| o.1o[.oo41 (9
`
`Contact zone
`must be free
`of holes
`Card
`edge
`
`o.2o[.oo3] —— <— J J
`
`254 [.100] MIN
`
`DETAIL A
`
`VRAM Expansion Cards
`
`Page 80 of 500
`
`Page 80 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`VRAM SIMM pin assignments are shown in Table 3-25.
`
`Table 3-25
`
`VRAM SIMM pin assignments
`
`Pin
`
`Name
`
`Pin
`
`Name
`
`I-kl-\F-‘O\oO0\‘lO‘\UIn-I=UJNo—t
`
`+5V
`
`DSF
`
`SDQO
`
`SDQ1
`
`/DT-OE0*
`
`DQO
`
`DQ1
`
`SDQ3
`
`SDQ2
`
`/WEO
`
`/RAS
`
`/ SEO
`
`DQ3
`
`DQ2
`
`A0
`
`A1
`
`A2
`
`A3
`
`GND
`
`GND
`
`SDQ4
`
`SDQ5
`
`NC
`
`DQ4
`
`25
`
`26
`
`27
`
`28
`
`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`38
`
`39
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`48
`
`DQ5
`
`SDQ7
`
`SDQ6
`
`NC
`
`+5V
`
`DQ7
`
`DQ6
`
`/CASO
`
`A4
`
`A5
`
`GND
`
`SC
`
`SDQ8
`
`SDQ9
`
`/DT-OE1
`
`DQ8
`
`DQ9
`
`SDQ11
`
`SDQIO
`
`/WE1
`
`/SE1
`
`DQ11
`
`DQ10
`
`A6
`
`* A slash before a signal name indicates that it is in the low state when active.
`
`VRAM Expansion Cards
`
`Page 81 of 500
`
`Page 81 of 500
`
`

`
`CHAPTER 2
`
`Hardware Details
`
`VRAM access times in numbers of clock cycles are shown in Table 3-26. The Random
`columns in Table 3-26 show the times required for random accesses; the Second columns
`show the times required for immediately succeeding accesses.
`
`Table 3-26
`
`VRAM access times
`
`Macintosh Quadra 840Av
`
`Macintosh Centris 660Av
`
`Access type
`
`Random
`
`Single write
`Burst write
`
`Single read
`Burst read
`
`5
`5-3-3-3
`
`7
`7-3-3-3
`
`VDC write
`
`19
`
`Second
`
`7
`7-3-3-3
`
`7
`7-3-3-3
`
`20
`
`Random
`
`3
`3-2-2-2
`
`4
`4-2-2-2
`
`19
`
`Second
`
`4
`4-2-2-2
`
`4
`4-2-2-2
`
`20
`
`VRAM Expansion Cards
`
`Page 82 of 500
`
`Page 82 of 500
`
`

`
`Real-Time Data Processing
`
`This part of the Macintosh Quadra 840AV and Macintosh Centris 660AV Developer
`Note covers the software technology of the Macintosh Quadra 84OAV and
`Macintosh Centris 66OAV digital signal processing facilities. It contains
`three chapters:
`
`Chapter 3, "Introduction to Real-Time Data Processing,” describes the
`software architecture of the real-time data processing facility in the
`Macintosh Quadra 840AV and Macintosh Centris 660AV. This facility
`consists of an AT&T DSP3210 chip that performs data-processing
`operations for applications that contain digital signal processor (DSP) code.
`
`Chapter 4, ”Real Time Manager,” describes a new part of the Macintosh
`system software that supplies all the services an application requires to use
`the DSP, including loading and running DSP code and performing DSP
`memory management.
`
`Chapter 5, ”DSP Operating System,” covers the DSP operating system,
`contained in the DSP chip. It provides the services every DSP program
`needs to work with the Macintosh Operating System.
`
`Page 83 of 500
`
`Page 83 of 500
`
`

`
`CHAPTERS
`
`Introduction to Real-Time
`
`Data Processing
`
`Page 84 of 500
`
`Page 84 of 500
`
`

`
`CHAPTER 3
`
`Introduction to Real-Time Data Processing
`
`This chapter describes the new real—time data processing software architecture for the
`Macintosh Quadra 840AV and Macintosh Centris 660AV computers, including the
`functional specifications, features, programming interface, capabilities, and performance.
`For hardware information about these computers’ DSP implementation, see Chapter 2,
`”Hardware Details.”
`
`For the novice in digital signal processing, this chapter begins with an overview of the
`AT&T DSP3210 digital signal processor and the architecture of real—time data processing.
`It provides the basics for understanding the rest of the chapter, which provides a more
`complete discussion of all the concepts and fuller architectural details.
`
`The serious programmer of real—time data processing should read this entire chapter. You
`must understand several concepts introduced in the section ”Real—Time Processing
`Architecture” to handle real—time programming and data flow properly.
`
`Other parts of this book supplement this chapter. Chapter 4, "Real Time Manager,”
`provides information to the Macintosh programmer and can be skipped by the DSP
`programmer. Chapter 5, ”DSP Operating System,” provides information to the DSP
`programmer and can be skipped by the Macintosh programmer. However, for a
`complete understanding of the interrelationships and dependencies between the two
`types of programming anyone doing system debugging or integration should read both
`chapters. For information about installing and debugging DSP programs in the
`Macintosh Quadra 840AV and Macintosh Centris 660AV, see Appendix A, ”DSP d
`Commands for MacsBug,” Appendix B, ”BugLite User's Guide,” and Appendix C,
`”Snoopy User's Guide.”
`
`Introduction to Digital Signal Processors
`
`Real-time data processing requires a hardware and software architecture for integrating
`digital signal processing technology into the Macintosh Quadra 840AV and Macintosh
`Centris 66OAV computers. The architecture supports the computer's digital signal
`processor as a coprocessor that has its own operating system but is capable of accessing
`the same data memory as the main processor.
`
`Concepts of Digital Signal Processing
`
`Digital signal processing is the manipulation and conversion of digitized data. Digitized
`data are digital representations of analog signals, which may represent sounds, images,
`speech, or other analog forms. To correctly process these signals it is necessary to know
`at what rate they were converted (the sample rate) and the format of the digital bits used
`to represent the original data. With this information the signal can be manipulated by a
`conventional program using the digitized data as its input. The result can then be stored
`on disk or converted back into an analog signal.
`
`Introduction to Digital Signal Processors
`
`Page 85 of 500
`
`Page 85 of 500
`
`

`
`CHAPTER 3
`
`Introduction to Real-Time Data Processing
`
`All such processing accomplished by a computer is called digital signal processing. The
`digital signal processor supports the math routines required in a special chip designed
`specifically for signal processing applications. The multiply / accumulate operation is the
`basic ingredient of signal processing programs. The digital signal processor is designed
`to perform this operation Very rapidly.
`
`The equivalent of digital signal processing in the analog domain is accomplished using
`electronic components, such as inductors, capacitors, resistors, and transistors. The
`advantage of doing the processing in the digital domain is that the functions can be very
`precise, reliable, elaborate, and software-configurable. It is difficult and costly to achieve
`these same goals in the analog domain.
`
`Real-Time Processing Capability
`
`The Macintosh Quadra 840AV and Macintosh Centris 660AV computers’ real—time
`capability uses a multi-tasking coprocessor to give high-performance processing of
`sound, communications, speech, and images (both graphic and video) while utilizing
`the system's low—cost dynamic random—access memory (DRAM) for primary storage
`of data and code. The standard hardware is the AT&T DSP3210 and the audio and
`
`telephone input / output (I/ 0) ports. The software is a custom operating system
`designed to perform isochronous (real—time) and asynchronous (timeshare) algorithms.
`The operating system is based on a team processing approach where the work of the total
`system is carefully separated and delegated between the main processor and the digital
`signal processor.
`
`This approach has the benefit of
`
`I greatly reducing implementation and hardware costs
`
`I simplifying and speeding up interprocessor communications and data sharing or data
`streaming
`
`allowing flexible dynamic load sharing between the main processor and the DSP on
`selected algorithms
`
`maximizing the potential to meet future needs for higher performance and multiple
`coprocessors
`
`I increasing the range of possible application functions the DSP can provide
`
`The DSP software architecture supports dual threaded processing streams. Real-time
`processing uses interrupt-level isochronous algorithms with guaranteed processing
`bandwidth to execute real—time functions requiring precisely timed signal generation or
`inputs such as sound and communications. (Guaranteed processing bandwidth is
`defined in the next section.) Timeshare processing uses asynchronous algorithms that
`employ the excess DSP bandwidth for functions not requiring time-correlated
`processing, such as still image decompression or scientific computing.
`
`Additionally, the architecture supports the implementation of NuBus cards to make
`configurations of multiple DSPs possible.
`
`Introduction to Digital Signal Processors
`
`Page 86 of 500
`
`Page 86 of 500
`
`

`
`CHAPTER 3
`
`Introduction to Real-Time Data Processing
`
`Real-Time Processing Architecture
`
`Program execution on the DSP is divided into segments of time called frames, typically
`10 ms in length, as diagrammed in Figure 3-1. During each frame an attempt is made to
`run all of the code that is installed on the DSP. Tasks are blocks of DSP code that are
`
`grouped together by the programmer to perform a specific function.
`
`Figure 3-1
`
`Frames
`
`Time
`
`Frame n — 2
`
`Frame n — 1
`
`Frame n
`
`Frame n + 1
`
`Frame n + 2
`
`There are two types of tasks: real-time and timeshare. During each frame all of the
`real-time tasks are executed and then any remaining time in the frame is used for
`executing timeshare tasks, as diagrammed in Figure 3-2. Real-time tasks are useful for
`sound, modem, and video processing where there is a fixed amount of data that must be
`processed during each frame; if more processing time were available it would not be
`used. However, timeshare tasks use as much processing power as they can get each
`frame. Image decompression is an example of a timeshare task, since it should
`decompress the image as fast as possible. This means that when a faster version of the
`DSP3210 is available timeshare tasks run faster but real-time tasks continue to process
`the same amount of data.
`
`Figure 3-2
`
`Real-time and timeshare tasks
`
`10 ms frame
`
` k 4
`
`<:|
`
`Real-time tasks
`
`I: <:|
`
`Timeshare tasks
`
`|:>
`
`Each task is assembled out of modules, which are the functions that the DSP
`
`programmer creates, and each module is composed of sections. This relationship is
`shown in Figure 3-3.
`
`Real-Time Processing Architecture
`
`Page 87 of 500
`
`Page 87 of 500
`
`

`
`CHAPTER 3
`
`Introduction to Real-Time Data Processing
`
`Figure 3-3
`
`Task list
`
`To understand the need for sections, it is necessary to understand how the memory
`system of the DSP works. To keep hardware costs down, the DSP uses the same DRAM
`as the main processor. Because the DSP can access memory at a much higher rate than
`the RAM can provide, and must also compete with the main processor for RAM access,
`some type of caching on the DSP is needed. The DSP does not have a hardware cache
`like that in the 68040 main processor. It has a small amount of memory on the DSP
`chip that is accessed in the same way as main RAM. It is called on-chip memory, in
`contrast to main memory, which is off-chip. The lack of DSP hardware caching means
`that caching must be managed by the DSP program and the DSP operating system.
`This is called visible caching as opposed to the transparent operation of most main
`processor caches.
`
`To accomplish visible caching, the DSP programmer must mark which sections of the
`code are loaded in on-chip memory before execution and which sections are saved
`off-chip after execution. Visible caching operates in one of two modes. In AutoCache
`mode, loading and saving are controlled by the DSP operating system; there is only
`one set of sections on-chip during the execution of a module. In DemandCache mode,
`loading and saving are controlled by the DSP program, so sections can be moved on and
`off-chip during the execution of the module. Caching modes are discussed in more detail
`in ”Visible Caching” and "Execution Models,” later in this chapter.
`
`To make modules slightly more general, a mechanism is provided for a single module
`to work at different frame rates and sample rates. This is done by making sections
`individually scalable. The DSP programmer has the option of saying which sections are
`scalable and the possible sizes of the scalable sections. For example, if a reverberation
`module works with both 24k Hz and 48k Hz sound at a 10 millisecond frame rate it
`
`would have an input and an output section, both of which would be scalable to either
`240 or 480 samples per frame. When the Macintosh program loads the module from disk,
`it specifies the module scale of operation.
`
`To ensure that all of the real—time tasks are executed during each frame, the DSP
`programmer must specify an upper bound for the execution time of the module. If there
`is enough processing power on the DSP, the task that contains this module will be
`installed and executed. As long as every module's estimate is correct, the DSP will
`execute frames evenly. However, if a module's estimate is not its upper bound, the DSP
`
`Real-Time Processing Architecture
`
`Page 88 of 500
`
`Page 88 of 500
`
`

`
`CHAPTER 3
`
`Introduction to Real-Time Data Processing
`
`could take more time to execute the real-time tasks than is available in a given frame.
`When this frame overrun occurs the DSP operating system will find the module that
`specified its incorrect upper bound, remove the task that contains this module from the
`execution stream, and then resume execution. This procedure is called guaranteed
`processing bandwidth (GPB).
`
`Since a task is made up of modules which typically share data, optimization is provided
`to keep the data on—chip between modules, instead of saving it off—chip in one module
`and then loading it back on-chip for the next module. This is accomplished by
`connecting sections from one module to another, letting the DSP operating system
`decide if data saving and loading is required. Data that must be shared between tasks,
`such as the sound going to the speaker, is passed between tasks in intertask buffers
`(ITBs). The only logical difference between ITBS and connected sections is that the
`sections are in different tasks for ITBs and in the same task for connected sections. Both
`
`ITBs and connected sections are managed by the Macintosh programmer, as described in
`”Data Buffering,” later in this chapter.
`
`Software Model
`
`The software model for real-time data processing in the Macintosh Quadra 840AV and
`Macintosh Centris 660AV computers consists of three distinct pieces:
`
`I The host toolbox is the Real Time Manager. The Real Time Manager runs on the main
`processor and is written in C for portability.
`
`The DSP Driver contains both main processor code and DSP code components. All
`hardware-dependent functions are included in the drivers. They are written in the
`68000 and DSP assembly languages for efficiency.
`
`The DSP toolbox is called the DSP operating system. The DSP operating system runs
`on the DSP, and is Written in DSP assembly language for efficiency.
`
`Almost all routines in the Real Time Manager are reentrant and callable from interrupt
`level. This is necessary, since communications between the DSP and main processor
`often take the form of interrupt messages.
`
`A major component of the model is a shared block of memory This memory consists of
`local memory as well as main memory. The local memory is either in system DRAM or
`in optional card memory. It is through data structures and semaphores in this shared
`memory that the main processor and DSP toolboxes communicate. A more complete
`diagram of the software model is shown in Figure 3-4.
`
`Dual Programming Model
`
`Figure 3-4 shows the dual programming interface for real-time data processing: the
`application programming interface (API) in the Real Time Manager, and the module
`programming interface (MPI) in the DSP operating system. These two interfaces are
`completely separate, and designed to be used by different programmers. It is not
`necessary for a programmer to be both a Macintosh programmer and a DSP programmer.
`
`Software Model
`
`Page 89 of 500
`
`Page