Trials@uspto.gov
`Tel: 571-272-7822
`
`
`
`
`
`Paper 52
`Entered: January 4, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`HTC CORPORATION and HTC AMERICA, INC.,1
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`
`____________
`
`Case IPR2015-01502
`Patent 7,542,045 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`1 Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.; and
`LG Electronics, Inc. were terminated from this proceeding. See Papers 28
`and 41.
`
`
`Tel: 571-272-7822
`
`
`
`
`
`Paper 52
`Entered: January 4, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`HTC CORPORATION and HTC AMERICA, INC.,1
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`
`____________
`
`Case IPR2015-01502
`Patent 7,542,045 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`1 Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.; and
`LG Electronics, Inc. were terminated from this proceeding. See Papers 28
`and 41.
`
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`
`I. INTRODUCTION
`In its Petition requesting inter partes review, HTC Corporation and
`HTC America, Inc. (collectively, “Petitioner”) asserted the unpatentability of
`claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 (“the challenged claims”) of U.S.
`Patent No. 7,542,045 B2 (Ex. 1001, “the ’045 patent”), owned by Parthenon
`Unified Memory Architecture LLC (“Patent Owner”). Paper 2 (“Pet.”), 1.
`The Petition identifies HTC Corporation; HTC America, Inc.; LG
`Electronics, Inc.; LG Electronics U.S.A., Inc.; LG Electronics MobileComm
`U.S.A., Inc.; Samsung Electronics Co., Ltd.; and Samsung Electronics
`America, Inc. as real parties-in-interest. Id. at 2. We have jurisdiction under
`35 U.S.C. § 6, and this Final Written Decision, issued pursuant to 35 U.S.C.
`§ 318(a) and 37 C.F.R. § 42.73, addresses issues and arguments raised
`during the review. For the reasons discussed below, we determine that
`Petitioner has met its burden to prove, by a preponderance of the evidence,
`that claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of the ’045 patent are
`unpatentable on the grounds upon which we instituted inter partes review.
`
`A.
`
`Procedural History
`On June 24, 2015, Petitioner filed a Petition to institute an inter partes
`review of claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of the ’045 patent.
`Pet. 1. Petitioner asserted grounds for unpatentability based on the
`following references and declarations:
`
`Exhibit
`1002
`1003
`
`
`References and Declarations
`File History of Patent No. US 7,542,045 B2
`Patent No. US 5,546,547 (“Bowes”)
`
`
`2
`
`
`
`1005
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`
`Exhibit
`1004
`
`References and Declarations
`International Organization for Standardization, “ISO/IEC
`11172-2: Information
`technology—Coding of moving
`pictures and associated audio for digital storage media at up
`to about 1,5 Mbit/s—Part 2: Video,” (1st ed. Aug. 1, 1993)
`(“MPEG”)
`S. Rathnam et al., “An Architectural Overview of the
`Programmable Multimedia Processor, TM-1,” PROC.
`COMPCON, IEEE Computer Society Press, Los Alamitos,
`CA, 1996, pp. 319–326 (1996) (“Rathnam”)
`Patent No. US 5,774,676 (“Stearns”)
`1007
`Declaration of Santhana Chari, Ph.D.
`1008
`Declaration of Harold S. Stone, Ph.D.
`1030
`Pet. vii–viii. Patent Owner filed a Preliminary Response (Paper 7). On
`January 6, 2016, we issued an Institution Decision (Paper 14, “Inst. Dec.”),
`instituting inter partes review on the following grounds:
`References
`Basis
`Claims challenged
`Bowes and MPEG
`35 U.S.C. § 103(a) 1, 4, 5, 7, 10, 12, 16,
`and 17
`Bowes, MPEG, and Rathnam 35 U.S.C. § 103(a) 9 and 15
`Bowes, MPEG, and Stearns
`35 U.S.C. § 103(a) 2, 6, and 13
`Inst. Dec. 29; see Pet. 5–6.
`After institution, Patent Owner filed a Patent Owner Response to the
`Petition (Paper 21, “PO Resp.”), and Petitioner replied (Paper 32, “Reply”).
`A hearing for the instant proceeding and related Cases IPR2015-01500 and
`IPR2015-01501 was held on September 19, 2016. A transcript (Paper 51,
`“Tr.”) of that hearing is included in the record.
`
`B.
`
`Related Proceedings
`The ’045 patent is involved in several cases pending in the U.S.
`District Court for the Eastern District of Texas. Pet. 2–4; Paper 5, 2–3.
`Petitioner also has filed other petitions seeking inter partes review of related
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`patents in related Cases IPR2015-01500 and IPR2015-01501. Pet. 3–4.
`Further, an unrelated petitioner, Apple Inc., has filed a petition challenging
`claims of the ’045 patent. See IPR2016-01134, Paper 7, 2 & 32 (instituting
`inter partes review of claims 1, 4, 5, 7, 9, 10, 12, and 15–17).
`
`A.
`
`II. THE ’045 PATENT (EX. 1001)
`Subject Matter
`The ’045 patent relates generally “to the field of electronic systems
`having a video and/or audio decompression and/or compression device, and
`is more specifically directed to sharing a memory interface between a video
`and/or audio decompression and/or compression device and another device
`contained in the electronic system.” Ex. 1001, col. 1, ll. 36–41. As of the
`effective filing date of the ’045 patent,2 a typical decoder included a
`dedicated memory, which represented a significant percentage of the cost of
`the decoder and which went unused most of the time. Id. at col. 2, ll. 21–63,
`col. 4, ll. 43–60, Figs. 1a–1c.
`To address these and other concerns, the ’045 patent discloses an
`electronic system in which a first device and a video and/or audio
`decompression and/or compression device are coupled to a shared memory
`through a bus that may have bandwidth sufficient for the video and/or audio
`
`
`2 The ’045 patent claims the benefit of a string of earlier-filed U.S. patent
`applications, the earliest of which was filed on August 26, 1996. Ex. 1001 at
`[63]. Petitioner does not challenge the entitlement of the ’045 patent to this
`earliest filing date and argues that the ’045 patent expired in August of 2016,
`presumably based on this earliest filing date. Pet. 12–13. Patent Owner
`implicitly claims the entitlement of the ’045 patent to the benefit of this
`earliest filing date and expressly states that the ’045 patent expired on
`August 26, 2016. Paper 8, 1.
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`decompression and/or compression device to operate in real time. Id. at
`col. 4, l. 64–col. 5, l. 7. Figure 2 of the ’045 patent is reproduced below.
`
`
`
`Figure 2 is a block diagram of an electronic system that contains a device
`with a memory interface, an encoder and decoder. Id. at col. 6, ll. 3–5.
`“First device 42 can be a processor, a core logic chipset, a graphics
`accelerator, or any other device that requires access to the memory 50 . . . .”
`Id. at col. 6, ll. 29–32. Both first device 42 and decoder/encoder 80 have
`access to memory 50 through memory interfaces 72 and 76, respectively,
`coupled to fast bus 70. Id. at col. 6, ll. 27–29, col. 7, ll. 26–28, 48–51. Fast
`bus 70 may have at least the bandwidth required for decoder/encoder 80 to
`operate in real time and, preferably, has a bandwidth of at least
`
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`approximately twice the bandwidth required for decoder/encoder 80 to
`operate in real time. Id. at col. 7, ll. 48–51, col. 8, ll. 28–33.
`During operation, decoder/encoder 80, first device 42, and refresh
`logic 58, if it is present, request access to memory 50 through arbiter 82. Id.
`at col. 12, ll. 53–56. Arbiter 82 determines which of the devices may access
`memory 50. Id. at col. 12, ll. 57–58. For instance, decoder/encoder 80 may
`get access to memory 50 in a first time interval, and first device 42 may get
`access to memory 50 in a second time interval. Id. at col. 12, ll. 58–61.
`Direct Memory Access (DMA) engine 52 of decoder/encoder 80 determines
`the priority of decoder/encoder 80 for access to memory 50 and the burst
`length when decoder/encoder 80 has access to memory 50. Id. at col. 12,
`ll. 61–67. DMA engine 60 of first device 42 determines its priority for
`access to memory 50 and the burst length when first device 42 has access to
`memory 50. Id. at col. 12, ll. 65–67.
`When decoder/encoder 80 or one of the other devices generates a
`request to access memory 50, the request is transferred to arbiter 82, and
`access to memory 50 is determined based on the state of arbiter 82 and on a
`priority scheme. Id. at col. 13, ll. 1–30. The priority scheme can be any
`scheme that ensures decoder/encoder 80 gets access to memory 50 often
`enough to operate properly, but does not starve entirely other devices
`sharing memory 50. Id. at col. 13, ll. 31–37; see id. at col. 8, ll. 9–13
`(describing a “starvation period”).
`
`B.
`
`Illustrative Claim
`Of the challenged claims, claims 1, 4, 5, and 12 are independent.
`Ex. 1001, col. 15, ll. 35–56 (claim 1), col. 15, l. 63–col. 16, l. 36 (claims 4
`and 5), col.16, l. 54–col. 17, l. 2 (claim 12). Claim 2 depends directly from
`
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`claim 1 (id. at col. 15, ll. 57–60); claims 6, 7, 9, and 10 depend directly from
`claim 5 (id. at col. 16, ll. 37–42, 46–49); and claims 13 and 15–17 depend
`directly from claim 12 (id. at col. 17, ll. 3–6, col. 18, ll. 1–8). Claim 1 is
`illustrative and is reproduced below, with disputed claim limitations
`emphasized:
`An electronic system comprising:
`1.
`a bus coupleable to a main memory having stored therein
`data corresponding to video images to be decoded and also
`decoded data corresponding to video images that have previously
`been decoded;
`a video decoder coupled to the bus for receiving encoded
`video images and for outputting data for displaying the decoded
`video images on a display device, the decoder configured to
`receive data from the main memory corresponding to at least one
`previously decoded video image and to a current video image to
`be decoded and outputting decoded data corresponding to a
`current video image to be displayed, the current video image to be
`displayed adapted to be stored in the main memory;
`a microprocessor system configured to be coupled to the
`main memory, the microprocessor system for storing non-image
`data in and retrieving non-image data from the main memory; and
`an arbiter circuit coupled to both the microprocessor
`system and the video decoder for controlling the access to said
`main memory by the video decoder and the microprocessor.
`Ex. 1001, col. 15, ll. 35–56 (emphases added).
`
`III. CLAIM CONSTRUCTION
`Petitioner argues that the ’045 patent expired in August of 2016. Pet.
`12–13. Patent Owner states that the ’045 patent expired on August 26, 2016.
`Paper 8, 1. Thus, the parties agree that the ’045 patent has expired.
`As a result, we construe the claims in accordance with the principles
`followed in district court. 37 C.F.R. § 42.100(b); see Phillips v. AWH Corp.,
`415 F.3d 1303, 1314 (Fed. Cir. 2005) (en banc) Toyota Motor Corp. v.
`
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`Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8–10 (PTAB Aug. 14,
`2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012)
`(“While claims are generally given their broadest possible scope during
`prosecution, the Board’s review of the claims of an expired patent is similar
`to that of a district court’s review.”) (internal citation omitted). Although
`Petitioner proposed a construction of certain claim terms under the broadest
`reasonable construction standard, Petitioner argues that its proposed
`construction will remain the same even if we apply the district court claim
`construction, consistent with the principles set forth in Phillips. Pet. 13
`(stating that “this change in standards would not affect any of the proposed
`grounds in this Petition, especially in view of Patent Owner’s interpretations
`of the claims under the Phillips standard.”).
`In our Decision on Institution, we construed three terms: “video
`decoder, “fast bus,” and “decoder directly supplies a display device with an
`image.” Inst. Dec. 9–12. In particular, we construed:
`1. “video decoder” to mean “hardware and/or software that translates
`data streams into video information” (id. at 9–10);
`2. “fast bus” to mean “any bus having a bandwidth sufficient to
`allow the system to operate in real time” (id. at 11); and
`3. “decoder directly supplies a display device with an image” to
`mean that an image as being “directly supplied” if it is supplied
`without being stored in main memory for purposes of decoding
`subsequent images (id. at 12; see Ex. 1011, 19–20; Ex. 1012, 17–
`18; Ex. 1013, 1; see also Power Integrations, Inc. v. Lee, 797 F.3d
`1318, 1326 (Fed. Cir. 2015) (“The fact that the board is not
`generally bound by a previous judicial interpretation of a disputed
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`
`claim term does not mean, however, that it has no obligation to
`acknowledge that interpretation or to assess whether it is
`consistent with the broadest reasonable construction of the
`term.”)).
`Neither party challenges these constructions. See Tr. 15:24–16:17, 51:19–
`52:20. Therefore, after reviewing the complete record and finding no reason
`to alter our previous constructions, we adopt those constructions.3
`Neither Petitioner nor Patent Owner offers other constructions of any
`claim term in the challenged claims. See Pet. 8–13. Only terms which are in
`controversy in this proceeding need to be construed, and then only to the
`extent necessary to resolve the controversy. Wellman, Inc. v. Eastman
`Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011) (explaining that “claim
`terms need only be construed ‘to the extent necessary to resolve the
`controversy’”) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999)). For purposes of this Final Written
`Decision, no other claim terms require express construction.
`
`IV. ANALYSIS
`Petitioner asserts that claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of the
`’045 patent are unpatentable under 35 U.S.C. § 103(a) as obvious over
`Bowes and MPEG, alone or in combination with Rathnam or Stearns. See
`supra Section I.A. Petitioner also relies upon the declaration of its declarant,
`Dr. Stone. See Ex. 1030 ¶¶ 33–59, 70–76, 82, 83, 174–221 (claims 1, 4, 5,
`
`
`3 On this record, we also are persuaded that our construction of the terms
`“video decoder,” “fast bus,” and “decoder directly supplies a display device
`with an image” set forth above would have been substantially the same had
`we applied the broadest reasonable interpretation standard. See Pet. 13.
`
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`7, 10, 12, 16, and 17), 84, 222–229 (claim 9 and 15), 60–63, 85, 230–243
`(claim 2, 6, and 13).
`A. Obviousness Over Bowes and MPEG
`1. Overview
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are “such
`that the subject matter[,] as a whole[,] would have been obvious at the time
`the invention was made to a person having ordinary skill in the art to which
`said subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
`406 (2007). The question of obviousness is resolved on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art;4 and (4) objective evidence of
`nonobviousness, i.e., secondary considerations.5 Graham v. John Deere
`
`
`4 Petitioner proposes an assessment for a person of ordinary skill in the art.
`Pet. 13 (citing Ex. 1030 ¶¶ 78–81); see Ex. 2009 ¶ 24. Patent Owner’s
`declarant, Dr. Thornton, proposes an alternative assessment for a person of
`ordinary skill in the art. Ex. 2009 ¶ 25. Nevertheless, Dr. Thornton testifies
`that “my analysis and conclusions would remain unchanged” regardless of
`which assessment is applied. Id. ¶ 26; see Tr. 40:8–42:11, 76:20–77:9. To
`the extent necessary and for purposes of this Final Written Decision, we
`adopt Petitioner’s assessment, which each party’s declarant meets or
`exceeds. See Ex. 1030 ¶¶ 2–6; Ex. 2009 ¶¶ 5–11.
`5 Patent Owner does not contend in the Patent Owner Response that such
`secondary considerations are present. See Paper 15, 6 (“Patent Owner is
`cautioned that any arguments for patentability not raised in the response will
`be deemed waived.”).
`
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`Co., 383 U.S. 1, 17–18 (1966).6 For the reasons set forth below, we
`determine that Petitioner has shown by a preponderance of the evidence that
`claims 1, 4, 5, 7, 10, 12, 16, and 17 of the ’045 patent are rendered obvious
`over Bowes and MPEG.
`
`a. Bowes (Ex. 1003)
`Bowes describes a memory bus arbiter for a computer system having
`a DSP co-processor. Ex. 1003, Title. According to Bowes,
`[i]n prior art computer systems, because of the high bandwidth
`required for real-time processing by a DSP, it has not been
`possible for the DSP to run off of the computer system’s
`[dynamic random access memory (DRAM)] in the way the
`[central processor unit (CPU)] 10 utilizes it without adversely
`affecting the rest of the computer system. Thus, there has been
`provided a large block of [static random access memory
`(SRAM)] 24 for use by the DSP 20. . . .
`A significant disadvantage to the prior art computer architecture
`of FIG. 1 is the requirement of a substantial block of static
`random access memory 24. SRAMs are significantly more
`expensive than DRAM which greatly increases the cost of
`computer systems which incorporate SRAM.
`Id. at col. 2, ll. 36–48. Thus, it is an object of Bowes “to provide a
`mechanism and method for arbitrating the memory bus bandwidth to
`efficiently allow the use of a digital signal processor and a CPU over a
`common memory bus sharing the system’s dynamic random access
`
`
`6 There is no requirement to enumerate each Graham factor and to include
`findings specifically in terms of the factors as long as “the required factual
`determinations were actually made and it is clear that they were considered
`while applying the proper legal standard of obviousness.” Specialty
`Composites v. Cabot Corp., 845 F.2d 981, 990 (Fed. Cir. 1988).
`
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`memory subsystem without requiring an expensive block static
`random access memory.” Id. at col. 2, ll. 57–63 (emphasis added).
`Figure 2 of Bowes is reproduced below.
`
`
`Figure 2 illustrates a block diagram of a computer architecture incorporating
`the arbitration scheme described in Bowes. Id. at col. 3, ll. 62–64. “The
`scheme is implemented such that the DSP is provided with sufficient
`bandwidth to perform real-time digital signal processing using the system’s
`[DRAM] and not requiring the incorporation of an expensive block of
`[SRAM].” Id. at col. 4, ll. 55–60. As shown in Figure 2, the system
`includes CPU 10, memory controller and arbiter (MCA) 200, main memory
`subsystem 14, and DSP 20. Id. at Fig. 2. “Unlike prior art computer
`systems, the [system of Bowes] provides for the DSP 20 to reside on the
`system’s memory bus and operate from the computer systems’ main
`memory subsystem 14.” Id. at col. 6, ll. 22–26. “[T]his greatly reduces
`system cost by eliminating the need for an expensive block of SRAM.” Id.
`at col. 6, ll. 26–29. In a preferred embodiment, MCA 200 “is an
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`application[] specific integrated circuit (ASIC) for arbitrating memory bus
`110 between the various bus masters subject to the constraints each imposes
`to provide optimal bandwidth for each, particularly the DSP which is
`responsible for a significant amount of real-time signal processing.” Id. at
`col. 6, ll. 46–52.
`
`b. MPEG (Ex. 1004)
`MPEG describes the coded representation of video for digital storage
`media and specifies the decoding process for the MPEG-2 standard.
`Ex. 1004, 1. The MPEG standard was known and accessible at least as of
`August of 1993. Ex. 1008 ¶ 8.
`
`2. Analysis
`We are persuaded by Petitioner’s arguments and cited evidence that
`the combination of the teachings of Bowes and MPEG teaches or suggests
`all of the recited limitations of challenged, independent claims 1, 4, 5, and
`12. Pet. 32–48; see Inst. Dec. 22–27. In particular, Bowes discloses
`supporting video applications (Ex. 1003, col. 1, ll. 24–41), and specifically
`discloses video controllers 131 coupled to memory bus 110 (id. at col. 6, ll.
`6–18). Pet. 35. Moreover, DSP 20 performs “image processing.” Id. at 37
`(citing Ex. 1003, col. 6, ll. 33–38). Thus, Petitioner argues that Bowes
`discloses that both CPU 10 (i.e., the “microprocessor system” of claim 1)
`and DSP 20 (i.e., the “video circuit” of claim 1) are attached to memory bus
`110, from which they access main memory subsystem 14. Pet. 38–39; see
`also id. at 42, 47 (“central processing unit” of claims 4 and 12). In addition,
`Petitioner argues that Bowes discloses a memory controller and arbiter (i.e.,
`MCA 200) that teaches the “arbiter circuit” limitation of claims 1 and 4. Id.
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`at 39–40; see also id. at 44–45 (“memory arbiter” of claim 5), 47 (“arbiter”
`of claim 12). We agree.
`Petitioner further argues that a person of ordinary skill in the art
`would have found it obvious to combine the teachings of Bowes and MPEG
`to achieve the systems, methods, and circuits limitations recited in the
`challenged, independent claims.
`To the extent Bowes (Ex. 1003) does not describe transferring
`and processing data in the MPEG format, it would have been
`obvious to combine Bowes with the MPEG Standard (Ex. 1004),
`in light of the knowledge of one of ordinary skill in the art in
`1996, given that the ’045 patent acknowledges that MPEG was a
`“coding standard currently in use.” Ex. 1001 at 1:53–54. The
`’045 patent describes the MPEG standards, including MPEG-1
`and MPEG-2, as being “well accepted standards for one-way
`communication.” Id. at 2:6–7. Given Bowes’ aim to “support a
`broad range of new multimedia (i.e., voice, video and traditional
`data) applications,” Ex. 1003 at 1:32–34, as well as its use of a
`digital signal processor (DSP 20) for “image processing,” id. at
`6:33-35, incorporating the known MPEG standard into Bowes’
`system would yield predictable results. Moreover, the MPEG
`Standard describes a protocol of interpolated and predicted
`image frames resulting in “high compression ratio while
`preserving good picture quality.” Ex. 1004 at 4 (§ 0.2). Because
`Bowes acknowledges DSPs “require a large amount of
`bandwidth to memory” for real time processing, Ex. 1003 at
`1:51–53, an ordinary artisan would have been motivated to
`combine the MPEG Standard’s highly efficient compression to
`address Bowes’ bandwidth requirement. See Ex. 1030, Stone
`Decl. at ¶ 45–59, 82, 83, 174–177.
`Pet. 33–34 (emphasis added); see id. at 45 (MPEG Standard was developed
`to satisfy the “growing need for a common format representing compressed
`video on various digital storage media.”); Ex. 1032 ¶¶ 84–88; see also KSR,
`550 U.S. at 421 (“When there is a design need or market pressure to solve a
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`problem and there are a finite number of identified, predictable solutions, a
`person of ordinary skill has good reason to pursue the known options within
`his or her technical grasp.”). In particular, Petitioner argues that
`One of ordinary skill in the art would have understood that
`Bowes’ DSP 20 would “block read” from and “block write” to
`main memory subsystem 14 such coded or decoded MPEG video
`images because MPEG video involves large amounts of data,
`and Bowes’ video controllers 131 can access the decoded video
`images from main memory subsystem 14 for display. Ex. 1030,
`Stone Decl. at ¶ 45-59, 82, 83, 174–177. A person of ordinary
`skill would have found that using Bowes to read and write MPEG
`data would have been a simple and commonsense combination
`of known prior art elements according to known methods to yield
`predictable results. See KSR Int’l Co., 550 U.S. at 401, 417; see
`also Ex. 1030, Stone Decl. at ¶ 45–59, 82, 83, 174–177. Bowes,
`in combination with MPEG Standard, therefore provides for
`storing data corresponding to video images to be decoded,
`decoded data corresponding to video images that have
`previously been decoded. See Ex. 1030, Stone Decl. at ¶ 45–59,
`82, 83, 174–177 . . . .
`Pet. 35–36 (emphases added); see Ex. 1032 ¶81; see also id. at 38 stating
`that
`
`One of ordinary skill in the art would have understood that during
`MPEG decoding, Bowes’ DSP 20 would block-read from the
`main memory subsystem 14 data corresponding to at least one
`previously decoded video images and to a current video images
`to be decoded, in accordance with the MPEG Standard.
`Reply 15–21; see Ex. 1032 ¶¶ 72–82. We are persuaded that a person of
`ordinary skill in the art would have had reason to incorporate teachings of
`the known MPEG standard into Bowes’s system and that doing so would
`have satisfied a design need with a known solution to yield predictable
`results. See Reply 20.
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`Patent Owner contends that Petitioner fails to demonstrate by a
`
`preponderance of the evidence that claims 1, 4, 5, 7, 10, 12, 16, and 17 of the
`’045 patent are obvious over the applied art for four reasons. PO Resp.
`3–38. Specifically, referring to the challenged independent claims, Patent
`Owner contends that (a) the combination of the teachings of Bowes and
`MPEG does not teach “the decoder configured to receive data from the main
`memory corresponding to at least one previously decoded video image” (id.
`at 3–24); (b) the combination of the teachings of Bowes and MPEG does not
`teach “an arbiter circuit coupled to both the microprocessor system and the
`video decoder for controlling the access to said main memory by the video
`decoder and the microprocessor” (id. at 24–29); and (c) a person of ordinary
`skill in the art would not have had reason to combine the teachings of Bowes
`and MPEG (id. at 29–38). We address each contention in turn.
`
`a. “the decoder configured to receive data from the main memory
`corresponding to at least one previously decoded video image”
`(Claims 1, 4, 5, and 12)
`Patent Owner contends that the combined teachings of Bowes and
`MPEG do not teach or suggest this limitation of challenged claims 1, 4, 5,
`and 12 for three reasons. First, Bowes does not teach or suggest that its
`DSP 20 is a video decoder. PO Resp. 9–17. Second, Bowes does not teach
`that its DSP receives a previously decoded video image from the main
`memory, rather than a dedicated memory. Id. at 6–9, 17–22. Third, Bowes
`does not teach that the DSP reads data from and writes data to a main
`memory. Id. at 22–24. We disagree with each of Patent Owner’s reasons.
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`i. Whether Bowes’s DSP teaches a “Video Decoder”
`Patent Owner asserts that Bowes’s DSP does not teach a “video
`decoder,” as recited in the challenged independent claims. Id. at 9–17. In
`particular, Patent Owner contends that Bowes only mentions the word
`“video” four times and only once in relation to its system and that Bowes
`does not mention the words “decode” or “decoding” at all. Id. at 9–10.
`Further, Bowes only uses the word “video” in relation to the NuBus
`peripheral bus video controller and not in relation to DSP 20. Id.
`Consequently, Patent Owner contends that “Bowes does not state that the
`DSP is suitable for video compression and decompression applications such
`as the MPEG Standard” (id. at 10 (citing Ex. 2009 ¶ 46)), and that “a [person
`of ordinary skill in the art (POSA)] would recognize that audio processing,
`speech processing and modem emulation are clearly distinct from video
`compression and decompression. The same is true with respect to ‘image
`processing.’” (id.). See Tr. 62:11–65:4.
`Although Bowes explicitly teaches the use of DSP 20 for “image
`processing” (Ex. 1003, col. 6, l. 35), Bowes does not teach explicitly the use
`of DSP 20 for video compression and decompression. The grounds of
`unpatentability, however, are based upon a modification of the teachings of
`Bowes’s DSP 20 to perform video decoding according to the MPEG
`Standard. Pet. 37 (“Bowes contemplates supporting video applications,
`Ex. 1003 at 1:24-41, and discloses video controllers 131 coupled to memory
`bus 110, Ex. 1003 at 6:6-18. And MPEG Standard teaches decoding
`compressed video images to generate decoded video images adapted to be
`displayed on a display device.”); see Ex. 1030 ¶ 190. Dr. Stone testifies that
`“MPEG Standard teaches the decoder receiving data from memory
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`corresponding to at least one previously decoded image and to a current
`image to be decoded and outputting decoded data corresponding to a current
`image to be displayed.” Ex. 1030 ¶ 193 (citing Ex. 1004, 56 (Figure D.7.)).
`Bowes further, teaches that DSP 20 “may be an off-the-shelf DSP.”
`Ex. 1003, col. 2, ll. 21–22.
`As noted above, neither party has challenged our construction of the
`term “video decoder” as “hardware and/or software that translates data
`streams into video information,” including video decompression (Ex. 1030
`¶ 187); and “neither Patent Owner nor its expert dispute that the prior art
`included ‘off the shelf’ DSPs capable of video compression and
`decompression pursuant to the MPEG Standard or that a skilled artisan
`could have implemented the Bowes/MPEG combination using such prior art
`DSPs.” Reply 4 (citing Ex. 1032 ¶¶ 8–10); see Ex. 2009 ¶ 45; Ex. 1037,
`66:5–12; 67:8–14; 69:2–8; see also Ex. 1032 ¶ 10 (“[A] person of skill
`would understand Bowes to be pointing out that any available DSP could
`potentially be used in the system of Bowes”) (citing Exs. 1006, 1035, 1036,
`2008); Ex. 1023, col. 6, ll. 20–22 (“digital system chip 112 also preferably
`includes a general purpose DSP engine 206 which is programmable to
`perform various functions such as MPEG decoding.” (emphasis added)).
`Thus, even assuming that Bowes’s “image processing” does not indicate
`video decompression expressly, we, nevertheless, are persuaded that “off the
`shelf” DSPs existed that were capable of decompressing MPEG video, and
`that it was within the level of ordinary skill in the art to use, in the system of
`Bowes, such a DSP as DSP 20 to operate in accordance with the well-known
`MPEG Standard. See Ex. 1008 ¶ 8 (“As a published standard, those in the
`field of image/video coding . . . would have known about, sought out, and
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`had access to the MPEG Standard, at least as of August 1993.”); Ex. 2009
`¶ 48 (“Therefore, video compression and decompression processes typically
`do not require the same level of precision and arithmetic operations as image
`processing. As a result, a POSA would typically use a different type of DSP
`for image processing as compared to video compression and
`decompression.”); KSR, 550 U.S. at 421 (“When there is a design need or
`market pressure to solve a problem and there are a finite number of
`identified, predictable solutions, a person of ordinary skill has good reason
`to pursue the known options within his or her technical grasp.”).
`Patent Owner also contends that DSP 20 is not suitable for video
`decompression because it is a floating-point DSP. PO Resp. 11–15; but see
`Reply 5–6. Initially, we note that Bowes does not mention “fixed” or
`“floating” point DSPs. See Tr. 91:15–20; but see id. at 66:20–25. This
`contention is not persuasive because it is based on an exemplary
`implementation provided in Bowes, namely the use of the AT&T DSP3210.
`Reply 5–6; see Ex. 1001, col. 6, ll. 28–30 (“In the preferred embodiment
`implementation, the DSP 20 is an AT&T DSP3210 which provides an
`internal 8K SRAM cache.” (emphasis added)). The teachings of Bowes,
`however, are not limited to the use of the AT&T DSP3210 as DSP 20.
`Moreover, Patent Owner’s contention that the AT&T DSP3210 is too slow
`to decode MPEG images is not adequately supported by evidence. Reply
`5–6 (alleging that Dr. Thornton’s testimony contains errors); see Tr.
`91:21–92:4 (citing Ex. 1032 ¶¶ 12–17); cf. PO Resp. 15.
`Finally, Patent Owner contends that its assertion that “the DSP of
`Bowes is not suitable for video compression and decompression is further
`evident from the way that DSP is used in the industry.” PO Resp. 15 (citing
`
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`Ex. 2009 ¶ 54). For instance,
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