IPR2015-01501
`Patent Owner Response
`U.S. Patent No. 7,777,753
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC Corporation,
`HTC America, Inc.,
`LG Electronics, Inc.,
`Samsung Electronics, Co., Ltd., and
`Samsung Electronics America, Inc.
`PETITIONERS
`
`V.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR No: 2015-01501
`Patent No. 7,777,753
`Title: ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO
`A SHARED MEMORY
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
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`
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`Patent Owner Response
`U.S. Patent No. 7,777,753
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`HTC Corporation,
`HTC America, Inc.,
`LG Electronics, Inc.,
`Samsung Electronics, Co., Ltd., and
`Samsung Electronics America, Inc.
`PETITIONERS
`
`V.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR No: 2015-01501
`Patent No. 7,777,753
`Title: ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO
`A SHARED MEMORY
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
`
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`IPR2015-01501
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`TABLE OF CONTENTS
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`INTRODUCTION ..................................................................................................... 1
`I.
`II. THE `753 PATENT .............................................................................................. 2
`III. THE CHALLENGED CLAIMS ARE PATENTABLE ................................................... 3
`A. Bowes and the MPEG Standard [claims 1 and 2] ............................................ 3
`1. The Combination of Bowes and the MPEG Standard Does Not Disclose
`Every Element of the Challenged Claims ............................................................... 3
`a. The proposed combination does not disclose “providing access to the main
`memory for a request for access to the main memory when the arbiter circuit is
`in an idle state” [claim 1] ..................................................................................... 3
`b. The proposed combination does not disclose “wherein the video circuit is
`further configured to receive data from the main memory corresponding to at
`least one previously decoded video image” [claim 2] ......................................... 5
`c. The proposed combination does not disclose an arbiter that controls access
`to the main memory [claim 1] ........................................................................... 26
`2. No Motivation to Combine Bowes and the MPEG Standard. ....................... 32
`B. Bowes in view of the MPEG Standard and Stearns [claim 3] ....................... 41
`C. Bowes in view of the MPEG Standard and Shanley [claim 4] ...................... 41
`IV. CONCLUSION ................................................................................................... 42
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`TABLE OF AUTHORITIES
`
`
`Cases
`
`C.R Bard, Inc. v. M3 Sys., Inc.,
`157 F.3d 1350 (Fed. Cir. 1998) ............................................................................ 31
`
`
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) ..................................................................... 40, 41
`
`
`In re Wilson,
`424 F.2d 1382 (CCPA 1970) .................................................................................. 3
`
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) .............................................................................................. 31
`
`
`
`Rules
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`35 U.S.C. § 314(a) ..................................................................................................... 1
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`TABLE OF EXHIBITS
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`Exhibit Description
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`U.S. Patent No. 7,777,753 (“`753 Patent”)1
`File History of `753 Patent
`U.S. Patent No. 5,546,547 (“Bowes”)
`The “MPEG Standard” or “MPEG”
`S. Rathnam et al., “An Architectural Overview of the Programmable
`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON ’96,
`pp. 319-326 (1996) (“Rathnam”)
`U.S. Patent No. 5,774,676 (“Stearns”)
`Expert Declaration of Dr. Harold Stone (“Stone Decl.”)
`DSP3210 Information Manual
`Affidavit of Mitchell A. Thornton Relating to Ex. 2003
`AT&T DSP3210 Digital Signal Processor The Multimedia Solution,
`Data Sheet, AT&T Microelectronics, March 1993 (“DSP3210
`Datasheet”)
`Affidavit of Mitchell A. Thornton Relating to Ex. 2005
`Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`660AV Computers (“Quadra Developer Notes”)
`Deposition testimony of Harold S. Stone, Phd. dated March 17, 2016
`(“Stone Depo”)
`Excerpts from Stone, H.S., High-Performance Computer Architecture,
`Addison-Wesley Publishing Company, Reading, Massachusetts,
`1993, ISBN 0-201-52688-3.
`Kitson, F. and Bhaskaran, V., Interactive Video from Desktops to
`Settops, HPL-95-58, Hewlett-Packard white paper, June 1995
`Declaration of Mitchell A. Thornton (“Thornton Decl.”)
`
`
`
`Exhibit
`No.
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`1001
`1002
`1003
`1004
`1005
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`1007
`1030
`2001
`2002
`2003
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`2004
`2005
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`2006
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`2007
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`2008
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`2009
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`1 Ex. 1001, 1002, 1003, 1004, 1005, 1007, 1030 and 2001 are already of record and
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`not attached to this Response.
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`iv
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`I.
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`INTRODUCTION
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`IPR2015-01501
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
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`Owner”) hereby submits the following response to the Petition for Inter Partes
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`review (“Petition”) filed by HTC Corp., HTC America, Inc., LG Electronics,
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`Inc., Samsung Electronics Co., Ltd., and Samsung Electronics America, Inc.
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`(collectively, “Petitioner”) regarding certain claims of U.S. Patent No.
`
`7,777,753 (“`753 Patent”) filed on June 24, 2015 and Decision Granting
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`Institution of Inter Partes Review 37 C.F.R. 42.108 issued on January 6, 2016
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`(“Institution Decision”).
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`The Board instituted an Inter Partes review with respect to the following
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`three proposed grounds:
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`1. Alleged Ground C: Obviousness of claims 1 and 2 under 35 U.S.C. §
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`103 over Bowes and the MPEG Standard;
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`2. Alleged Ground D: Obviousness of claim 3 under 35 U.S.C. § 103
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`over Bowes, the MPEG Standard and Stearns; and
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`3. Alleged Ground E: Obviousness of claim 4 under 35 U.S.C. § 103 over
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`Bowes, the MPEG Standard and Shanley.
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`For the reasons discussed below, Bowes and the MPEG Standard do not
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`render claims 1 and 2 obvious. Claims 3 and 4 are allowable for at least the
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`same reasons. The discussion below first discusses the `753 Patent and claims. It
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`then rebuts the adopted grounds of unpatentability on the merits.
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`II. THE `753 PATENT
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`The `753 Patent is generally directed to sharing a memory interface
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`between a video decoder and another device contained in an electronic system.
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``753 Pat. [Ex. 1001], Abstract; independent claims 1 and 7. Accordingly, the
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`electronic system includes a bus and a main memory coupled to the bus. Id. at
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`claim 1. The main memory has stored therein data corresponding to video
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`images to be decoded. Id. A video circuit is coupled to the bus and receives data
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`from the main memory corresponding to a video image to be decoded. Id. The
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`video circuit outputs decoded video data corresponding to the current video
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`image to be displayed on a display device. Id. The current video image to be
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`displayed is stored in the main memory. Id. In addition to the video circuit, the
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`electronic system includes another device such as, for example, a processor that
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`is coupled to the main memory. Id. An arbiter circuit is coupled to the processor
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`and the video circuit and is configured to receive requests for access to the main
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`memory from the video circuit and the processor and control access to the main
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`memory. Id.
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`IPR2015-01501
`Patent Owner Preliminary Response
`U.S. Patent No. 7,777,753
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`III. THE CHALLENGED CLAIMS ARE PATENTABLE
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`A. Bowes and the MPEG Standard [claims 1 and 2]
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`Independent claim 1 and dependent claim 2 are not invalid as obvious in
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`view of Bowes and the MPEG Standard because: (1) Bowes and the MPEG
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`Standard, alone or in combination, fail to disclose all limitations of these claims;
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`and (2) one of ordinary skill would not have been motivated to combine Bowes
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`and the MPEG Standard as suggested by the Petitioner because the references
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`teach away from the proposed combination and/or the proposed combination
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`would create an inoperable assembly.
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`1. The Combination of Bowes and the MPEG Standard Does
`Not Disclose Every Element of the Challenged Claims
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`The proposed combination does not disclose “each and every” claim
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`limitation. See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All
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`words in a claim must be considered in judging the patentability of that claim
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`against the prior art”).
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`a. The proposed combination does not disclose “providing access
`to the main memory for a request for access to the main memory
`when the arbiter circuit is in an idle state” [claim 1]
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`Bowes does not disclose this limitation because the arbiter of Bowes does
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`not have an “idle state.” [Ex. 2009, Thornton Decl. ¶33]. The `753 Patent
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`discloses an arbiter which has three states, one of which is the idle state. [`753 Pat.,
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`13:4-6]. In the idle state, “there is no device accessing the memory and there are no
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`requests to access the memory.” [`753 Pat., 13:4-6]. Bowes does not disclose such
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`an idle state. Instead, in Bowes, “the state of the memory bus assignment defaults
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`to the CPU and remains parked on the CPU until other resources request the
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`memory bus.” [Bowes, 8:30-33]. Accordingly, in Bowes, even if there are no
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`requests to access the memory, the CPU is given access to the memory. [Ex. 2009,
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`Thornton Decl. ¶34]. Therefore, the arbiter of Bowes does not have an “idle state”
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`in which no device accesses the memory. Id.
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`The use of the recited “idle state” is beneficial compared to the arbitration
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`scheme of Bowes. [Ex. 2009, Thornton Decl. ¶35]. A POSA would understand
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`that the `753 memory arbiter being in an “idle state” allows for bus traffic that does
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`not require memory access to occur in an unimpeded fashion. Id. As an example, a
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`video decoder could receive data from a peripheral device such as a DVD drive
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`directly via the bus while the `753 memory arbiter was in the “idle state.” Id.
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`Thus, a POSA would appreciate that the `753 “idle state” aids in ensuring that no
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`device monopolizes the bus starving the other devices. [`753 Pat., 5:66-4:5]. In
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`contrast, the Bowes bus arbiter would not allow such bus traffic to occur until such
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`time that the statically fixed priority schedule according to the Bowes arbiter state
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`diagram allows a device to control the bus for a “time slice” period. Id. The Bowes
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`bus arbiter causes the bus to be monopolized during the “time slice” period that the
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`bus is assigned to a particular bus master. [Bowes Pat., 8:23-27; 8:45-56; 9:11-15;
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`FIG. 3]; [Ex. 2009, Thornton Decl. ¶35].
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`b. The proposed combination does not disclose “wherein the video
`circuit is further configured to receive data from the main
`memory corresponding to at least one previously decoded video
`image” [claim 2]
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`Figure 1c of the `753 Patent depicts a system having a decoder in accordance
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`with the prior art.
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`The system includes a number of components that are connected to a
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`peripheral bus (170) via interfaces. [`753 Pat., 2:56-63]. A Central Processing Unit
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`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
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`circuit (146) enabling the main memory (168) of the system to be shared between
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`the CPU (152) and other peripherals that may require it. [`753 Pat., 2:64-67].
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`Typically, one of the peripherals connected to the peripheral bus (170) as a master
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`is a decoder (10). [`753 Pat., 3:1-3]. The decoder (10) receives encoded or
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`compressed data from a source peripheral (22) and decodes that data. For instance,
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`if the data to be decoded is video image data, the decoder then directs the decoded
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`video images to a video controller (120) for display. [`753 Pat., 3:3-14].
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`Traditionally, the decoder (10) included its own dedicated memory (22)
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`which was divided into three image area buffers (M1, M2, M3) and a Compressed
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`Data Buffer (CDB) and the compressed image to be decoded was stored in the
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`CDB before it was decoded. [`753 Pat., 3:14-19]. Typically, the decoding of
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`images under the MPEG Standard involves processing of “I”, “P” and “B” frames.
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`“I” frames are so called “intra” image frames whose compressed data directly
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`corresponds to an actual image. [`753 Pat., 3:31-32]. “P” frames are so called
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`“predicted” image frames the construction of which uses pixel blocks of a
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`previously decoded image frame. [`753 Pat., 3:23-25]. Finally, “B” frames are so
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`called “bidirectional” image frames the construction of which uses pixel blocks
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`from two previously decoded images. [`753 Pat., 3:26-28]. Accordingly, the “I”
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`and “P” image frames are used to reconstruct subsequent “P” and “B” frames while
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`“B” frames are not used to reconstruct subsequent image frames. [`753 Pat., 3:28-
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`30].
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`Figure 1c depicts how a prior art decoder (10) uses the buffers M1, M2, and
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`M3 of its dedicated memory (22) during the decoding process. [`753 Pat., 3:20-22;
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`3:31-50]. Accordingly, in prior art systems, although the system included a main
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`memory (168) which the decoder (10) could access via the peripheral bus (170),
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`the decoder (10) utilized its local dedicated memory (22) not the main memory
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`(168) when decoding an image. Specifically, an image to be decoded was stored in
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`the CDB of the dedicated memory (22). The decoder (10) then received the image
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`to be decoded from the CDB in its dedicated memory (22). The decoder (10) also
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`received a previously decoded image (i.e., an “I” image frame or a “P” image
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`frame) from the buffers (M1, M2, M3) in its dedicated memory (22). The decoder
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`(10) then used the previously decoded image (i.e., the “I” or “P” image frame) to
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`decode the image to be decoded using, for example, the MPEG decoding standard.
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`The use of this dedicated memory (22) allowed the decoder (10) to decode a
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`compressed image without having to access the main memory and avoided
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`dropping image frames while preserving the available bandwidth on the peripheral
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`bus (170). [`753 Pat., 3:60-4:48].
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`The `753 Patent discloses an improved system which allows the decoder and
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`a first device (e.g., a CPU) to share the main system memory when decoding an
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`image and eliminates the need for a dedicated memory for the decoder. [Ex. 2009,
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`Thornton Decl. ¶40].
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`Figure 4 of the `753 Patent depicts an embodiment of the claimed invention
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`where the decoder/encoder (80) shares the main memory (168) with other
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`peripheral devices (e.g., the CPU (152)). [`753 Pat., 10:14-17]. As shown in Figure
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`4, the decoder/encoder (80) does not have a dedicated memory and instead uses a
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`region (22’) of the main memory (168) of the system for the decoding process.
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`[`753 Pat., 10:24-26]. The region (22’) of the main memory (168) includes a
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`Compressed Data Buffer (CDB) into which the image source (122) writes a
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`compressed image (i.e., an image to be decoded) and two image buffers M1, and
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`M2 associated with “I” and “P” image frames (i.e., previously decoded images).
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`[`753 Pat., 10:27-30]. The third buffer (M3) used in dedicated memory of prior art
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`decoders has been eliminated and the “B” frames which are not used to decode
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`other images are directly supplied to the display adapter (120) as they are being
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`decoded. [`753 Pat., 10:30-33].
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`Accordingly, in the improved system of the `753 Patent an image to be
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`decoded is directed from the source (122) to the CDB in the main memory (168).
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`[`753 Pat., 10:34-36]. This image to be decoded is transferred from the CDB in the
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`main memory (168) to the decoder/encoder (80) over the peripheral bus (170) and
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`is decoded by the decoder. [`753 Pat., 10:36-37]. If the decoded image is an “I”
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`image frame or a “P” image frame, the decoder/encoder (80) retransmits the
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`decoded image to buffers M1 and M2 in the main memory (168). [`753 Pat., 10:37-
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`39]. These “I” and “P” image frames may then be transmitted from the buffers M1
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`and M2 in the main memory (168) back to the decoder and used in decoding of
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`subsequent “P” or “B” image frames or may be transmitted to the display adapter
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`(120) for display. [`753 Pat., 10:44-47]. If an image to be decoded corresponds to a
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`“B” image frame, the decoder/encoder (80) decodes the image and it may directly
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`supply it to the display adapter (120) without storing it in the main memory (168)
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`if it is ready for display in the display sequence time frame. [`753 Pat., 10:39-42].
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`Accordingly, in the improved system disclosed in the `753 Patent, the
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`decoder’s dedicated memory is eliminated and instead, the decoder receives an
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`image to be decoded (i.e., compressed image stored in CDB) and a previously
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`decoded image (i.e., “I” image frames or “P” image frames stored in M1 and M2)
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`from a region 22’ in the main memory (168). [Ex. 2009, Thornton Decl. ¶43].
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`These “I” and “P” image frames may then be utilized in decoding of subsequent
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`“P” or “B” image frames by the decoder. [`753 Pat., 10:44-47].
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`Consistent with this improvement, dependent claim 2 recites that “the video
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`circuit is further configured to receive data from the main memory corresponding
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`to at least one previously decoded image.” Petitioner relies on the combination of
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`Bowes and the MPEG Standard for disclosing this limitation. However, Bowes
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`and the MPEG Standard, alone or in combination, do not disclose this
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`limitation. First, as discussed below, a POSA would not have been motivated to
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`combine Bowes and the MPEG Standard. Moreover, even if a POSA were to
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`combine Bowes with the MPEG Standard, such a combination would not disclose
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`a video circuit that receives a previously decoded video image from the main
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`memory for at least three reasons: (1) Bowes’ DSP is not a video circuit; (2) if
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`such a combination was made, a POSA would have stored a previously decoded
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`image in the dedicated memory of the Bowes’ DSP (as in the prior art disclosed in
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`the `753 Patent); and (3) Bowes does not disclose the DSP writing data into the
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`main memory and then reading the same data from the main memory. [Ex. 2009,
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`Thornton Decl. ¶45].
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`Bowes’ DSP Is Not a “Video Circuit”
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`Petitioner has identified the DSP (20) of Bowes as being analogous to the
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`video circuit recited in the `753 Patent. [Petition at 40]. The word “video” is only
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`mentioned four times in Bowes. [Bowes, 1:34; 1:37; 1:41; 6:16]. The first three
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`times the term “video” is used in conjunction with a description of related art and
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`the fourth time, the term “video” is used in reference to a NuBus peripheral bus
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`video controller and not in reference to a processing application. [Ex. 2009,
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`Thornton Decl. ¶46]. The words “decode” or “decoding” never appear in Bowes.
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`Id.
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`Instead, Bowes specifically teaches that the DSP in the preferred
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`embodiment is suitable for audio processing, image signal processing, speech
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`processing, and modem emulation. [Bowes Pat., 1:48-49; 6:32-37]. Bowes does
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`not state that the DSP is suitable for video compression and decompression
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`applications such as the implementations of the MPEG Standard. [Ex. 2009,
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`Thornton Decl. ¶47]. A POSA would recognize that audio processing, speech
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`processing and modem emulation are clearly distinct from video compression and
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`decompression. Id. The same is true with respect to “image processing.” Id.
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`Dr. Stone, Petitioner’s expert, defines “image processing” in his textbook as
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`“a computation performed on a digitized representation of an image whose purpose
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`is to enhance the image or to extract information about the image.” [Ex. 2007 at
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`499]. This textbook was published in 1993 and accurately reflects how a person of
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`skill in the art would have understood the term “image processing” as of the
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`priority date of the `753 Patent. [Ex. 2009, Thornton Decl. ¶48]. In contrast, the
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`MPEG Standard is directed to compressing and decompressing video sequences.
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`Id. (citing Ex. 1004, p. 4). Such a compression and decompression of video
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`sequences is wholly different from image processing. [Ex. 2009, Thornton Decl.
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`¶48]. For example, video compression and decompression requires maintaining the
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`temporal relationship between consecutive image frames, an important concept
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`that is absent when processing a single image. Id. (citing Stone Deposition, 102:19-
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`104:5).
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`There are additional reasons why a POSA would recognize that a DSP used
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`for image processing is not suitable for video compression and decompression.
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`[Ex. 2009, Thornton Decl. ¶49]. Specifically, image processing requires precision
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`and involves a host of arithmetic operations. Id. In contrast, the primary concern in
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`video compression and decompression is speed to ensure that video is delivered to
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`viewer in real time. Id. Therefore, video compression and decompression processes
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`typically do not require the same level of precision and arithmetic operations as
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`image processing. Id. As a result, a POSA would typically use a different type of
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`DSP for image processing as compared to video compression and decompression.
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`Id. Specifically, the internal architecture of a DSP may be categorized according to
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`the type of numerical format it utilizes. Id. A “floating point” DSP utilizes a format
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`wherein a single value is specified with three fields, a sign field indicating whether
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`the value is positive or negative; a mantissa or significand field indicating the
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`precision of the value; and a signed exponent field indicating the magnitude. Id. In
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`contrast, a “fixed point” DSP utilizes a format wherein a single value represents
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`the signed value using an appropriate signed value encoding such as 2’s
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`complement and where the binary- or radix point is in a “fixed” position. Id.
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`That the DSP (20) of Bowes is not suitable for video compression and
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`decompression is further evident from the fact that Bowes states that in a preferred
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`embodiment, the DSP (20) of Bowes is the AT&T DSP3210. [Bowes, 6:28-30].
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`Such a DSP is not suitable for MPEG video decoding because it is a floating point
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`DSP. [Ex. 2009, Thornton Decl. ¶50 (citing Ex. 2003, at 1)]. Specifically, the
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`AT&T DSP3210 utilizes a floating-point Data Arithmetic Unit (DAU) that “is the
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`primary execution unit for signal processing algorithms.” [Ex. 2003, at 5]. Due to
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`its use of a more complex format, a floating point DSP generally incurs increased
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`latency but provides increased accuracy and dynamic range (i.e., it can represent a
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`wider range of numerical values). [Ex. 2009, Thornton Decl. ¶51]. In contrast, a
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`fixed point DSP allows higher performance but at the expense of decreased
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`accuracy and dynamic range. Id. Therefore, a POSA would appreciate that a
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`floating point DSP is not well-suited for video compression and decompression.
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`Id.; See, also, Stone Depo., Ex. 2006, 201:20-202:7.
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`A POSA would appreciate that MPEG decoding is a high throughput
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`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
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`VLD, de-quantization, and other processes. [Ex. 2009, Thornton Decl. ¶52].
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`Floating-point DSPs (such as the DSP3210) provide for higher dynamic range and
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`more accuracy in their computations, but at the expense of increased latency
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`whereas a fixed point DSP requires shorter internal data paths providing for
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`performance advantages. Id. While it may appear that the increased accuracy
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`provided by floating-point DSPs would be advantageous in IDCT operations, for
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`video and specifically MPEG video decompression, the IDCT operations are
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`performed over relatively short bit-exact data that ultimately represents a pixel
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`value, thus increased precision as provided by a more costly floating-point DSP
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`would offer no advantage when used as an MPEG video decoder. Id. Further, the
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`other intensive processes require a considerable amount of control instructions to
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`be executed rather than arithmetic instructions (e.g., table lookups). Id. A POSA
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`would therefore recognize that a floating point DSP (such as the DSP3210 of
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`Bowes) is not well-suited for MPEG video decoding. Id. Indeed the disclosed and
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`intended applications of the DSP in the preferred embodiments of Bowes are those
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`that would require the extended dynamic range and precision provided by a
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`floating point DSP such as audio, image processing, speech processing, and
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`modem emulation. Id. (citing Bowes Pat., 1:48-49; 6:32-37).
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`Floating-point processors are incompatible with MPEG decoding due to the
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`format of the encoded and decoded MPEG video data as in the MPEG standard
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`and the H.262 specifications. [Ex. 2009, Thornton Decl. ¶53]. The video data as
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`per the standard and specification is not in the form of floating point values and
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`would require conversions to floating-point prior to decoding and a conversion
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`back to its initial format after decoding. Id. A POSA would recognize that these
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`conversions would incur additional processing delay that would be otherwise
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`unnecessary if a fixed-point DSP were used. Id. Floating-point values require that
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`the significand fall within a numerical range between 1 and 2, with the exponent
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`field used to indicate the actual location of the binary-point. Id. Thus, all input
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`encoded MPEG values would need to be converted to this floating-point format
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`before processing, and the resulting decoded values would have to be converted
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`back from this range to appropriate pixel representations that are collections of
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`fixed-point values. Id. Such numerous conversions to and from floating point data
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`could cause the real time decoding constraint to be unrealizable. Id. Furthermore,
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`floating-point representations are unnecessary for MPEG decoding and cause
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`additional processing delay with no technical benefit. Id.
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`Although the DSP3210 also contains a fixed-point processor core denoted as
`
`the CAU in Figure 7, a POSA would not be motivated to attempt to utilize the
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`DSP3210 fixed-point core for MPEG decoding. [Ex. 2009, Thornton Decl. ¶54].
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`This core is used instead “for performing address calculations, branching control,
`
`and 16- or 32-bit integer arithmetic and logic operations.” Id. (citing Ex. 2003, at
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`5). In fact, an attempt to use the DSP3210’s fixed-point CAU unit for real time
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`MPEG decoding would fail since the CAU is rated at 16.7 million instructions per
`
`second (MIPS). Id. (citing Ex. 2001, at 3-3). Specifically, a POSA would have
`
`been aware that 16.7 MIPS is insufficient for real time video decoding under the
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`MPEG Standard which requires 524 MIPS (632 MIPS if YUV to RGB conversion
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`is included) [Ex. 2008, at 8], more than 31 times the maximum amount of
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`processing allowable by the DSP3210. [Ex. 2009, Thornton Decl. ¶54].
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`Finally, that the DSP of Bowes is not suitable for video compression and
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`decompression is further evident from the way that DSP is used in the industry.
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`[Ex. 2009, Thornton Decl. ¶55]. Specifically, the ATT DSP3210 was used in a
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`product from Apple, Inc., called the Quadra, in a fashion remarkably similar to
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`how the use of the DSP is described in Bowes, which was also assigned to Apple
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`Computers, Inc. [See, e.g., Ex. 2005 at 11; Stone Depo, Ex. 2006, at 147:15-
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`148:9]. As shown in the block diagram depicting the architecture of the Quadra,
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`Apple had to use other components for processing video (shown in blue) that were
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`distinct from the ATT DSP 3210 (shown in red) [Ex. 2009, Thornton Decl. ¶55
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`(citing Ex. 2005 at 11)]:
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`This implementation by Apple further confirms that a POSA would
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`recognize that the DSP of Bowes (e.g., the DSP3210) was not suitable for video
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`decoding and was not a video circuit. [Ex. 2009, Thornton Decl. ¶56]. Moreover,
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`the video processing portion of the Apple Quadra had its own dedicated memory
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`for processing video and did not use the main system memory. [Ex. 2009,
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`Thornton Decl. ¶57]. Accordingly, in a system that used the DSP3210, Apple (the
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`assignee of Bowes) used a separate video circuit with its own dedicated memory
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`and did not use the main memory for any video operations such as, for example,
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`video decoding. Id.
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`Even if Bowes and the MPEG Standard Were Combined, A Previously
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`Decoded Image Would Have Been Stored in the DSP’s Dedicated Memory,
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`Not in the Main Memory
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`If a POSA were to combine Bowes with the MPEG Standard, a previously
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`decoded image would have been stored in the dedicated memory of the Bowes’
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`DSP, not in the main memory. [Ex. 2009, Thornton Decl. ¶58].
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`The Bowes’ DSP (20) included a local dedicated memory. [Bowes, 6:28-30
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`(“In the preferred embodiment implementation, the DSP 20 is an AT&T DSP3210
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`which provides an internal 8K SRAM cache”); 6:66-7:2 (“Ideally, software written
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`for the DSP should be segmented in such a way that blocks may be loaded into the
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`cache of the DSP allowing the DSP to run as much of the time as possible from its
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`internal cache”)]. Accordingly, if the Bowes’ DSP were to function as a video
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`decoder to implement the MPEG Standard, a person of ordinary skill in the art
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`would have stored the “I” image frames and the “P” image frames generated by the
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`decoder (i.e., previously decoded images) in the local SRAM block of the DSP
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`(20) and not in the main memory (14). [Ex. 2009, Thornton Decl. ¶59].
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`Although Bowes provides an illustrative example where the memory
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`associated with the DSP (20) is an 8K SRAM cache which is insufficient to store a
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`previously decoded image frame, if a POSA were to combine Bowes with the
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`MPEG Standard, he would have used a larger dedicated memory with sufficient
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`space to store an image frame and the DSP would retrieve the previously decoded
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`image from this dedicated memory. [Ex. 2009, Thornton Decl. ¶60; See also Stone
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`Deposition, Ex. 2006, 159:17-23; 163:16-23]. Implementing such a configuration
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`would: (a) eliminate the need for the DSP to access the memory bus during the
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`decoding process; (b) allow other devices to access the memory bus during video
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`decoding; (c) provide faster access by the DSP to a previously decoded image; and
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`(d) free up space in the main memory. [Ex. 2009, Thornton Decl. ¶60].
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`Dr. Stone’s testimony also confirms the conclusion that if Bowes were to be
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`combined with the MPEG Standard, a POSA would have used the DSP’s dedicated
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`memory, not the main memory, to store previously decoded images. [Ex. 2009,
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`Thornton Decl. ¶61]. Specifically, Dr. Stone testified that at the time of the filing
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`of the `753 Patent, a POSA would not have concluded that using a shared memory
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`for video decoding is advantageous as compared to using a dedicated memory.
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`[Stone depo, Ex. 2006, 134:23-141:22]. In fact, Dr. Stone testified that in certain
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`circumstances it may be disadvantageous to use shared memory instead of a
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`dedicated memory in a video decoding implementation. [Stone depo, Ex. 2006,
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`141:23-142:12].
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`This
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`is f
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