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`Shelved as: TK7874.6.E87 1991
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`Location: LHL
`
`Title: Euro ASIC '91 : Palais des congres, Porte
`Maillot, Paris, France, May 27-31, 1991
`
`Fax:
`Phone: 213680-8315
`Ariel:
`Email: karen. sanchez@kirkland. com
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`Rush
`
`Volume:
`
`Issue:
`
`Date:
`
`Author: Wang
`
`Article Title: CMOS video cameras
`
`Pages: 100-103, cover, toe,
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`WEB
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`TABLE OF CONTENTS- EURO ASIC '91
`
`I v
`WELCOME . . . . I • • • • I • • I • • I • • • I • • • • I • • I
`COORDINATION COMMITTEE . . . . , , . , , , . . . . . . . . . . . . . . . . . . . . , , .. vi
`INTERNATIONAL PROGRAM COMMITTEE , , . , , , , , . , , , , , , , , , , , , , • , , , , Vl
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`I
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`I
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`I
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`I
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`I
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`I • • I
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`I
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`I • • I
`
`SESSION: MIXED ANALOG DEVICES I
`CHAIR: E. SCHUTZ
`
`Advances in High Speed ECL Technology and Interconnection Techniques . . . , . . . . , . . 2
`K.-1. Ohno
`DBIMOS: The Mix in One Approach , , , . . . . . . . . . . , , . . . . . . . . . . . . . . . . . 8
`E. Teck
`
`SESSION: MIXED ANALOG DEVICES II
`CHAIR: J.M. TISSANDIER
`
`A Versatile Building-Block for High-Speed Current-Mode Analog ICS , . . . . . . . , . , , , 14
`R.B. Steck, A. Kostka, and K. Lehmann
`DSP-ASIC Based Voltage Feedback Switching Regulator Chip for
`Electromechanical Contactor . , . . . . . . . . , . , . . . . . . . . . . . . . . . . . . , . . . • 20
`P. Solanti, T. Karema, and H. Tenhunen
`A Smart Power IC for High Side Driver Applications . . . . . . . , . . . . . . . . . . . • . , .25
`Y. Droinet
`Algorithmic ADC for Use in ASIC Design. , .... , . . . . . . . . . . . . . . . . . . , ... 29
`K. Deevy
`
`SESSION: DIGITAL SIGNAL PROCESSING ASICs
`CHAIR: C. PITOT
`
`KIS5-16: Realization of a DSP Optimized for Digital Mobile Radio Systems . . . . . • . , . . 36
`H. Sahm, J. Schuck, H. Ebert, D. Weinsziehr,
`]. Preissner, and G. Mahlich
`A SIMD Machine for Beamforming on a Chip , , • . . . , . . . . . , , . . . . . , • . . . . , .41
`J.-P. Giacalone and Y. Del Gallo
`VLSIImplementation of a Cochlear Model . . . . , , . . , . , , • , . • . . • . . • . . . . . . 45
`N. Avellana, F. Garrido,]. Carrabina,
`E. Valderrama, and P. GOmez
`Single Chip RNS Two-Port Parallel Adaptor for Wave Digital Filters . . . . . . . . . . . . , . 49
`G.C. Cardarilli and F. Sargeni
`A 16/24-Bit DSP-ASIC Coprocessor for AC Motor Modelling . . . . . . . . . . . . . . . , , . 53
`S.]. Ovaska, 0. Vainio, and]. Pasanen
`
`SESSION: CHIP ARCHITECTURE
`CHAIR: A. LORENZI
`
`Processor Chip Design on Submicron ASICs • . . . . . . , . . . . • . . . . . . . . . . . . . . 58
`H. Schletter
`Design and Implementation of a Dedicated Neural Network for
`Handwritten Digit Recognition . , , • , . . . , . , , . . . . . . . . . • . . . . . . . . . . . • .63
`P.-Y. Alia, L. Masse-Navette, ]. Ouali, G. Saucier, S. Knerr,
`L. Personnaz, and G. Dreyfus
`SICURE®- A Crypto Chip for Rapid Encipherment , . . . . . . . . . . . . . . . . • . . . . . .68
`H.M. Deppermann, ]. Gessner, S. KOsters, and S. Wallstab
`
`vii
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`Reduced Voltage Swing, High Speed CMOS Driver, Receiver Techniques for
`Multiple Chip Set Applications .... , . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . 74
`P.D. Ta
`
`SESSION: HIGH LEVEL LANGUAGES
`CHAIR: F. RAMMIG
`
`VHDL in Logic Synthesis-An Applications Perspective . . . . . . . . . . . . . . . . . . . . . 78
`W. Ries and K.M. Just
`UDL/1 Standardization Effort-Another Approach to HDL Standard . . . . . . . . . . . . . . 83
`0. Karatsu
`
`SESSION: GRAPHIC APPLICATION AND IMAGE PROCESSING ASICs
`CHAIR: R.A. COTTRELL
`
`An Image Decoding ASIC for Space-Based Applications . .
`D.B. Kasle and G. DeMicheli
`A Data-Flow Processor for Real-Time Low-Level Image Processing.
`G. Quenot and B. Zavidovique
`A Dedicated Circuit for Real-Time Motion Estimation . . . . . . . . • . . . . . . . . . . . • . 96
`0. Colavin, A. Artieri, f.-F. Naviner, and R. Pacalet
`CMOS Video Cameras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . .100
`G. Wang, D. Renshaw, P.B. Denyer, and M. Lu
`
`. .. 92
`
`•. ,86
`
`SESSION: LOGIC SYNTHESIS
`CHAIR: G. DUPENLOUP
`
`A New Approach to Timing Driven Partitioning of Combinational Logic . . . . . . . . , . , 106
`N. Wehn and M. Glesner
`Synthesis and Partitioning of Standard Cells for Floorplan Optimization . . . . . . . . . , . .112
`E. Chotin, T. Besson, and G. Saucier
`VLSI-Oriented Asynchronous Controller Synthesis Based on a
`Flip-Flop Cell Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
`K.R. Cho, M.Ikeda, and K. Asada
`
`SESSION: HIGH VoLUME ASICs
`CHAIR: T. BAKER
`
`A Mixed-Mode ASIC for Interface Control of Smart-Card Parcmeter . . . . . . .
`E. Compagne and F. Ilie
`A Double-Sourced ASIC for Contactless Badges . . . . . . . . . . . . . . , . . . . . . . . . . 128
`R. Petigny and P. Cabon
`VLSI ASIC Design for MAC Video Processing Integration in SGS-Thomson
`Microelectronics Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
`A. Lorenzi, G. Vanneuville, V. Verfaille, N. Chaumartin, G. Gerot, and J.M. Troude
`
`, . . . .124
`
`SESSION: LOGIC SYNTHESIS II
`CHAIR: G. DE MICHELI
`
`An Efficient Program for Logic Synthesis of Mod-2 Sum Expressions . . . . . . . . . . . . . 136
`P. W. Besslich and M. W. Riege
`Automatic Synthesis of Boolean Functions on Xilinx and
`Actel Programmable Devices . . . . . . . . . . . . . .
`P. Sicard, M. Crastes, K. Sakouti, and G. Saucier
`
`. . . . . . . . . . . . . . . . . . 142
`
`Vlll
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`Algebraic Decomposition of MCNC Benchmark FSMs for Logic Synthesis . . . . . . . . . . .146
`T. Muller-WipperfUrth and M. Geiger
`
`SESSION: ASICs FOR DEDICATED COMPUTATION AND ARCHITECTURES
`CHAIR: J. HUERTAS
`
`VLSI Chip Set for Floating Point Vector Processing . . . . . . . . . . . . . . . . . . . . . . . 154
`A. Laudenbach, M. Glesner, P. Windirsch, J. Plahl, and W. Clemens
`VLSI Design of an 8-Bit Fixed Point Cordie Processor with
`Extended Operation Set . , . , . . , , . . , . . . , . . . . . . , . . , . . . . . . . . . . . . . 158
`D.E. Metafas, G.A. Krikis, and C.E. Goutis
`Pipeline-Based Design for Numerically Controlled Oscillator . . . , . . . . . . . . . . . . . .162
`L. Ji, D. Li, S. Sheng, and Q. Liang
`Design and Implementation of HRISC2 , . . , , . . . . , . . . . . . . . . . . . . . . . . . . .166
`A. Bouaraoua, Y.I. el-Haffaf, and A. Amari
`Searching Processor . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . 167
`J.B. Barbosa, M.B. Calha, and I.C. Teixeira
`
`SESSION: HIGH LEVEL SYNTHESIS
`CHAIR: s. MARZ
`Resource Assignment with Different Target Architectures .... , , . . . . . . . . . . . . . 172
`A. Mignotte and M. Crastes de Paulet
`Flexible Datapath Compilation for Phideo . , . . . . . . . . . . . . . . . . . . . . . . . . • . 178
`A. van der Werf, B. T. McSweeney, J.L. van Meerbergen,
`P.E.R. Lippens, and W.F.J. Verhaegh
`A New Method for the Minimization of Memory Area in High Level Synthesis . . . • . . . . 184
`B. Rouzeyre and G. Sagnes
`
`SESSION: SIMULATION
`CHAIR: D. AUVERGNE
`
`High Precision SPICE Models for the Simulation of Analogue CMOS Circuits • . . . . . . . .192
`B. Ankele and F. Schrank
`Power Calculation for High Density CMOS Gate Arrays . . . . . . . . . . . . . . . . . . . . 198
`W. Eisenmann and M. Kohl
`ACC: Automatic Cell Characterization , • . . . . . . . . . . . . . . • . . . . . . . . • . . • 204
`K. Anshumali
`
`SESSION: PLACE AND ROUTE
`CHAIR: T. YANAGAWA
`
`Timing Driven Pin Assignment in a Hierarchical Design Environment . . . . . . • . . • . . .212
`G. Meixner and G. Zimmermann
`A Genetic Algorithm for the Routing of VLSI Circuits . . . . . . . . . . . . . . . . . . . . . ,218
`M. Geraci, P. Orlando, G. Vassallo, and F. Sorbello
`A New Graph Theoretical Approach to the Selection of Rip-Ups . . . . . . . . . . . . . . . . 224
`M. Bartholomeus and M. Raith
`Optimal Module Orientation by Block Rotation and Wire Length Minimisation . . . . . . . .230
`P.J. Drenth, J.G.G.P. van Gisbergen, and M. Lousberg
`
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`SESSION: ASICs IMPLEMENTED IN EUROCHIP
`CHAIR: B. COURTOIS
`
`Implementation of a Linear Array Ele~ent for Matrix Multiplication . . . . . . . . . . . . . 236
`M.A. Morante, L. Saiz de Quevedo; P. Tabuenca,
`Jl. Martinez, and E. Villar
`Design of a Complex Combinational ASIC with Educational Aims . . . . . . . . • . . . . . .239
`P. Amblard, M. Hollett, S. Audie, E. Bittar, C. Chaudy,
`P. Coulomb, S. LeMen, 0. Ondoa, E. Piot, and F. Pogodalla
`Serial Data Interface for Telecommunication Satellites . . . . . . . . . . . . . . . . . . . . . 243
`J. Vanneuville, H. Manhaeve, and D. Gevaert
`A Digital CMOS Fully Connected Neural Network with In-Circuit Learning
`Capability and Automatic Identification of Spurious Attractors . . . . . . • . . . . . . . . . 247
`J.-D. Gascuel, M. Weinfeld, and S. Chakroun
`An ASIC for Image Dilation and Erosion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
`Y. Tertre, J. Rampon, and M. Baatour
`Real Time Image Processing System: Design of an Area CCD
`Sensor Driving Integrated Circuit . . . . . . . . . . . . . .
`E. Fauvet, M. Paindavoine, J.-F. Kirilenko, M. Robert,
`D. Deschacht, and D. Auvergne
`
`. . . . . . . . . . . . . . . . .254
`
`SESSION: MULTIPLIER DESIGN
`CHAIR: J.C. ROSICHINI
`
`A Fast Data Path Multiplier . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
`C. Priol and P. Magarshack
`On the Construction of Very Large Integer Multipliers . . . . . . . . . . . . . . . . . . . . • 266
`G. Hotz, P. Molitor, and W. Zimmer
`
`SESSION: CAD FOR TEST
`CHAIR: T. AMBLER
`
`Test Generation Using Cross-Observability Calculations . . . . . . . . . . . . . . . . . . . . 272
`E. Cerny, EM. Aboulhamid, C. Mauras,and P. Rioux
`Comprehensive CAD Support for Boundary Scan Implementation in ASICs . . . . . . . . . 278
`P. Lestrat, R. Leveugle, and P. Magarshack
`Test Generation of Controllers Using the Synthesis Specifications . . . . . . . . . . . . . . . 284
`M. Karam, G. Saucier, and C. Jay
`
`SESSION: ASICs FOR TELECOMMUNICATIONS AND COMMUNICATIONS
`CHAIR: C. AUBERT
`
`ASIC Cryptographical Processor Based on DES . . . . . . . . . . . . . . . . . . . . . . . . . 292
`I. Verbauwhede, F. Hoornaert, J. Vandewalle, and H. De Man
`The Design of the PRJ ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
`F.C. Torre
`ASIC Chip Set Development for PCM 2 & 3-ary Group MUX and
`DEMUX with EIS Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
`J. Jie
`6 Bits Programmable VHF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
`C. Vanhecke
`High-Speed CMOS Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
`S. Schwehr, T. Fuchs, K. Dzahini, B. Boutherin, and M. Le Helley
`
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`SESSION: DESIGN FOR TEST/QUALITY
`CHAIR: R. SEDMAK
`
`High-Quality Physical Designs of CMOS ICs . . . . . . . . . . . . . . . . . . . . . . . . . . .310
`J.J.T. Sousa, F.M. Gonr;alves, and J.P. Teixeira
`Design of Highly Reliable VLSI Processors Incorporating Concurrent
`Error Detection/Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
`G. Russell and I.D. Elliott
`Integrating Verification Testing and Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . .322
`W. Murzyn and A. Krasniewsld
`
`SESSION: TEST MEASUREMENTS TECHNIQUES
`CHAIR: M. LE HELLEY
`
`Testing ASICs At-Speed . , . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
`C. Gauthron
`Ultra-High Speed ICs Set for Test System Design . . . . . . . . . . . . . . . . . • . . . . . . 333
`A. Balevsld, A. Shishkov, R. Elenkova, V. Soliakov, and A. Adamov
`A Temperature and Voltage Measurement Cell for VLSI Circuits . . . . . . . . . . • . . . . .334
`G.M. Qubwt, N. Paris, and B. Zavidovique
`
`SESSION: INDUSTRIAL APPLICATIONS
`CHAIR: H. VAN NIELEN
`
`Digital Speed Regulation for a Washing Machine Motor . . . . . . . . . • . . . . . • . . • . 340
`C. Ferrer and J.M. Aguirre
`Design of a Robust Analog/Digital ASIC Interface for Hard Industrial Environment . . . . • 344
`f. Suutari, H. Tenhunen, and f. Nikula
`ASIC Design Considerations for Power Management in Laptop Computers . . . . . . . . . .348
`Y.A. Dubois and J.J. Farrell III
`An A/D-Chip for Accurate Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . 352
`R. Rauscher and V. Grupe
`Using a CMOS ASIC Technology for the Development of an Integrated ISFET Sensor . . . . 356
`K. Dzahini, F. Gaffiot, and M. Le Helley
`
`SESSION: LAYOUT SYNTHESIS
`CHAIR: J. FREHEL
`
`. . . . . . . . . . . . . 362
`
`Evaluation of VLSI Layout Style Implementations for Efficiency .
`M. Robert, f. Traushessec, G. Cathebras, V. Bonzom, N. Azemard,
`D. Deschacht, and D. Auvergne
`G2L: System for Converting Low-Level Geometrical Designs to a
`Higher Level Representation . . . . , , , , . , . . . . . . . . . . . . . . . . . . . . . . . . . 366
`E. Pajarre, T. Ritoniemi, and H. Tenhunen
`Branch-Based Digital Cell Libraries . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . • .372
`J.M. Masgonty
`Datapath Layout Generation with In-the-Cell Routing and
`Optimal Column Resequencing , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
`P.J. Drenth and C. Strolenberg
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`SESSION: VERIFICATION
`CHAIR: L. CLAESEN
`
`A Review on Formal Methods for Correct VLSI Design . . . . . . . . . . . . . . . . . . . . . 378
`0. Coudert and J.C. Madre
`Application Example of Multi-Level Digital Design Verification by the
`SFG-Tracing Methodology. , ... , ... , . . . . . . . . . . . . . . , . . . . . . . . . , . 379
`L. Claesen, M. Genae, E. Verlind, F. Proesmans, and H. De Man
`A Good Input Ordering for Circuit Verification Based on Binary Decision Diagrams ... , . 385
`G. Saucier and F. Poi rot
`
`AUTHOR INDEX . . . . . • . • . • • • . . . . . . . . . . . . . . . . . . . • . . . . . • . . • .395
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`CMOS Video Cameras
`
`G. Wang, D. Renshaw, P. B. Denyer and M. Lu
`
`University of Edinburgh
`Department of Electrical Engineering
`Mayfield Road
`Edinburgh, EH9 3JL, UK.
`
`Abstract
`A single chip CMOS video camera is presented,
`along with design technique and characterization
`results. The chip comprises a 312 X 287 pixel
`photodiode array together with all the necessary
`sensing, addressing and amplifying circuitry, as
`well as a 1,000 gate
`logic processor, which
`implements synchronization timing to deliver a
`fully-formatted composite video signal and a
`further 1,000 gate logic processor, which imple(cid:173)
`ments automatic exposure control over a 1vide
`range. There are also simple solutions for 'Y
`correction and test.
`
`1. Introduction
`
`We introduce a new capability that extends the
`CMOS ASIC marketplace in a sector of high
`growth rates. This market sector is that of image
`sensing and processing, covering applications
`from electronic cameras to 'smart' vision sys(cid:173)
`tems.
`Camera and vision systems addressed by today's
`CCD technology appear cumbersome, power(cid:173)
`hungry and expensive. The experimental work
`reported here demonstrates
`that high-quality
`image. sensors can be implemented entirely in
`commodity ASIC CMOS technology, operating
`from single 5v supplies.
`
`The reported chip is a highly-integrated CMOS
`VLSI camera, shown in Figure 1. Most of the
`core area is a 312 x 287 pixel image sensor array,
`together with the necessary sensing, addressing
`and amplifying circuitry. The output signal can
`be either linear or 'Y corrected.
`'Y correction is
`achieved by a simple solution which uses the
`nonlinear ID-V GS characteristic of an MOS
`
`TH0367-3/91/0000/01 00$01.00 © 1991 IEEE
`
`100
`
`transistor. The layout of the sensor is custom
`designed to make it as compact as possible.
`
`At the top (Figure 1) is the 2,000 gate logic pro(cid:173)
`cessor, laid out using a semi-custom standard(cid:173)
`cell compiler. Half of these gates generate syn(cid:173)
`chronization
`timing,
`including
`line-sync and
`frame-sync signals
`to format a 625line/50Hz
`standard composite video output. The other
`half of the gates arc included to electronically
`control exposure over a wide range (40,000:1),
`enabling the use of a single fixed-aperture lens.
`The chip measures 7.58mm x7.56mm, using 1.5
`f..Lm, 2 level metal CMOS technology.
`
`Figure 1. Photo-micrograph of single chip
`video camera
`
`9
`
`

`
`A video camera has been built using this chip
`along with a 6 MHz clock source, a 5 volt
`power supply, plus one bipolar transistor and a
`small
`number of
`resistors
`and
`capacitors
`required to match the line impedance to the
`monitor and decouple the power supply. The
`picture quality
`is subjectively excellent, and
`compares well with commercially available cam(cid:173)
`eras.
`
`2. Image Sensor Block
`
`The architecture of the image sensor is shown in
`Figure 2. The light sensing area consists of a
`312 X 2R7 diode array matrix, schematically indi(cid:173)
`cated by the columns and rows of individual
`photodiodes. The pixel size is 19.6j.im X l6j.im,
`giving a light sensing area of 6.12mm x4.59mm.
`This corresponds to the standard 1/2" format.
`
`cvo
`
`supplies
`
`clock
`
`gain
`setting
`
`auto-exposure
`control
`logic
`
`video format
`timing & control
`circuits
`
`* CVO -- composite video output
`
`Figure 2. Architecture of the image sensor
`
`The photodiodes are accessed on the basis of
`sequential selection of each row through a verti-
`
`101
`
`cal shift register. At the top of each column is a
`sense amplifier. The sensed information is read
`out sequentially along the x-direction under con(cid:173)
`trol of a horizontal shift register. At the end of
`the path there is an output amplifier [1.2].
`
`The sense amplifier is a single-ended differential
`charge integrator. Its performance demands an
`accurate capacitor,
`formed by metall/metal2
`and metall/poly. However, commodity ASIC
`CMOS technology sometimes can not guarantee
`the resulting capacitance values. We designed a
`gain-controllable integrator, shown in Figure. 3,
`which allows wide range of programmable varia(cid:173)
`tion of the capacitance value.
`
`Vref
`
`self
`compensation
`
`Figure 3.
`
`Integrator with programmable gain
`and self compensation
`
`The main concern in the output stage design is-,
`the read-out speed required to achieve high
`resolution. A 6 MHz clock was chosen for this
`design; this gives a horizontal resolution of 312
`pixels. The resultant picture quality is assured
`by a two stage output buffer with sample and
`hold function.
`
`3. Automatic Exposure Control
`
`The device automatically controls its exposure
`over a range of 40,000:1. Control is achieved
`by varying the integration time prior to reading
`each row of pixels. The integration time can be
`as long as one field, or as short as three cycles
`of the pixel clock(about 500ns).
`
`10
`
`

`
`The exposure is set by monitoring the video
`stream and estimating the fractions of each pic(cid:173)
`ture which are very white and very black. On
`the basis of this information, the device decides
`whether the picture contrast is acceptable, or too
`white, or too dark. If necessary, the exposure
`time is then changed, in the appropriate direc(cid:173)
`tion.
`
`4. Generation of the Video Format Signal
`
`Figure 4 shows a block diagram for the genera(cid:173)
`tion of the video formatted signal. The -y
`corrected image data is multiplexed with the
`sync-level and blanking-level, controlled by tim(cid:173)
`ing control signals, which are provided from the
`video
`timing block. A
`bipolar
`transistor
`(emitter follower) is needed to provide a low
`impedance output.
`
`in Figure 5.
`
`Vdd
`
`Corrected
`output
`
`Linear
`input
`
`r-i
`
`Figure 5. Gamma corrector
`
`SPICE simulation was carried out and a simula(cid:173)
`tion result is shown in Figure 6. A theoretical
`curve of ideal -y correction ( -y =0.45) is also
`shown in Figure 6.
`
`Video
`
`timing
`
`Image signal
`
`Image
`
`sensor
`
`Vdd
`
`ideal curve
`
`1.
`
`0.8
`
`0.6
`
`0.4
`
`Sync
`level
`
`Blanking
`level
`
`Figure 4. Generation of the video output
`
`5. Simple Solution for -y Correction
`
`to be
`image data needs
`The analogue
`-y
`corrected, to com pen sate for the nonlinearity of
`monitor tubes l3]. This is usually implemented
`using discrete components e.g. a ladder-network
`of diodes,
`resistors and
`reference voltages.
`Unfortunately, this is not suitable for integra(cid:173)
`tion. In this design -y correction is achieved by
`a simple solution which uses the nonlinear ID(cid:173)
`V GS characteristic of an MOS FET, as shown
`
`0.2
`
`0.4
`
`0.6 0.8
`
`1.(
`
`Figure 6. Gamma correction curves
`
`6. Simple Solution fot· Test
`
`Special consideration has been given to make it
`possible to carry out digital wafer test which is
`as complete as possible. The analogue parts arc
`also tested by making them produce digital out(cid:173)
`puts, so avoiding a requirement for full <malo(cid:173)
`gue test. The test includes bit-line tests and
`word-line tests. Only a 0.78% increase in chip
`area was required to implement the on chip
`
`102
`
`11
`
`

`
`~-----------------1-----------------
`
`i __ gM~~~-- --~g.Q_
`5v
`12v
`-----------------
`50mW
`
`~arameter
`operating voltage
`for camera
`power dissipation
`for chip
`power dissipation
`for camera
`s.n.r.
`exposure ran~--­
`saturation level
`r-~ntiblooming fac!.9_!'_
`dark current*
`
`200mW
`
`1W
`
`51 dB
`52 dB
`300:1
`40,000:1
`-----------------
`__ ]_91 u~--j__?-0!~
`100x
`100x
`------- - - - -
`0.0004
`0.005
`----------
`* as fraction of saturation at room temperature,
`20msec integration time
`
`hardware necessary for this form of testing (Fig(cid:173)
`ure 2). The individual photo pixels may be
`tested if a sufficiently long vector set is allow(cid:173)
`able.
`
`The chip can also self-generate a checkerboard
`pattern which may be displayed on a monitor
`screen, or captured by a frame grabber. This
`pattern can be used not only to find defective
`pixels, but also to check analogue performance
`parameters, such as read out speed and unifor(cid:173)
`mity.
`
`7. Eliminating Noise
`
`Complete guard rings are put around all analo(cid:173)
`gue parts to minimize interference from the digi(cid:173)
`tal parts. Routing is arranged with priority to
`analogue output and analogue power supplies.
`Analogue power supplies and digital supplies are
`separated, and supplies to different analogue
`parts arc divided where necessary.
`
`There arc two sources of fixed pattern noise:
`threshold variation in
`the MOS pixel access
`transistors causing speckles, and mismatches
`between
`the column sense amplifiers causing
`vertical stripes. The solution to the pixel thres(cid:173)
`hold variation is to reduce the pixel reset voltage
`below (V dd-Vt) so
`that the reset voltage is
`insensitive to the variation of the threshold Vt.
`
`Column fixed pattern noise arises mostly from
`offset mismatches in the column sense amplif(cid:173)
`iers. We have successfully eliminated this prob(cid:173)
`lem by automatically compensating each amplif(cid:173)
`ier to give zero offset during each line synchron(cid:173)
`ization interval.
`
`8. Characterization
`
`An optical test measurement set-up was used to
`characterize the camera. The following table
`summarize the measured results of the perfor(cid:173)
`mance characterization experiments. The param(cid:173)
`eters of typical monochrome CCD cameras are
`also given for comparison.
`
`' I
`
`9. Conclusions
`
`We have developed several design techniques to
`achieve a single chip camera. in unmodified
`CMOS
`technology. which matches
`the
`performance of CCD cameras. The design has
`proven that three technical barriers which most
`greatly
`influence new product development;
`cost, power consumption and size, are all
`dramatically reduced over
`today's solid-state
`camera technologies.
`
`10. Acknowledgements
`
`the
`We acknowledge support received from
`Science and Engineering Research Council
`(Grant GR/F 36538 IED2/1/1159).
`
`11. References
`
`[1]
`
`[2]
`
`D. Renshaw, et. al., "ASIC Vision", Proc.
`IEEE
`Custom
`Integrated
`Circuits
`Conference, 1990, pp 3038-3041.
`
`Image
`"ASIC
`al.,
`et.
`D. Renshaw,
`Sensors",
`Proc.
`International
`IEEE
`Symposium on Circuits and Systems, 1990,
`pp 7.3.1-7.3.4.
`
`[3]
`
`Eugene Trundle, Television and Video
`Engineers Pocket Book, Heinemann, 1987.
`
`103
`
`I
`
`~----------------------~~~~~)
`
`12