United States Patent [191
`Uesugi et al.
`
`lllllllllllll|||llllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`5,459,683
`Oct. 17, 1995
`
`USOO5459683A
`Patent Number:
`[11]
`[45] Date of Patent:
`
`[54] APPARATUS FOR CALCULATING THE
`SQUARE ROOT OF THE SUM OF TWO
`SQUARES
`
`,bth
`75 Inet :MitsrU ';K 'h'H
`[
`1
`v n ors of Ygirhm?zuipanomc l onma 0
`’
`[73] Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan
`
`[21] Appl. No.: 277,826
`
`0437876 7/1991 European Pat. Off. .
`2146200 4/1985 United Kingdom .
`
`OTHER PUBLICATIONS
`
`_
`Electronics Letters, vol. 10, No. 13, 27 Jun. 1974, Engage
`GB, pp. 255-256, Braun et al. ‘Digital hardware for approxi
`matmg to the amphtude of quadrature Pans’
`Electronics, vol. 56, No. 17, 25 Aug. 1983, New York US,
`pp. 138-139, H0 et al. ‘Comparator compares 2’s comple
`111cm numbers’
`
`Jul‘ 20’ 1994
`[22] Filed:
`[30]
`Foreign Application Priority Data
`
`Primary Examiner—Tan V. Mai
`Attorney, Agent, or Flrm—-Lowe, Pnce, LeBlanc & Becker
`
`Aug. 2, 1993
`
`[JP]
`
`Japan .................................. .. 5-191099
`
`[57]
`
`ABSTRACT
`
`[56]
`
`3,829,671
`3,829,672
`
`[51] Int. Cl.6 ...................................................... .. G06F 7/38
`[52] U-S- (31-
`364/752
`[58] Field of Search ............................................. .. 364/752
`_
`References Cited
`m E
`U'S' PATENT DOC
`NTS
`8/1974 Gathright et al. .................... .. 364/752
`8/1974 Sather ........... ..
`364/752
`1;;
`lgin?foig -
`4,553,260 11/1985 Belt et a1‘
`4 599 701 7,1986 v ..
`364/752
`4,694,417
`9/1987 Camwen
`364/752
`4,736,334 4/1988 Mehrgardt ......... ..
`364/752
`4,747,067
`5/193g jagodnik, Jr et a1
`5,159,567 10/1992 Gobert .................................. .. 364/757
`
`,
`
`,
`
`a 1ns
`
`,
`
`,
`
`ojir et al. ..
`
`364/752
`
`364/752
`
`A ?rst digital Signal of a Serial form is processed into a
`second digital signal of a serial form. The second digital
`signal represents an absolute value of a value represented by
`the ?rst digital signal. A third digital signal of a serial form
`is processed into a fourth digital signal of a serial form. The
`fourth digital signal represents an absolute value of a value
`represented by the third digital signal. The values repre
`sented by the ?rst and third digital signals are compared to
`generate a comparison-result digital signal representing a
`result of the comparison. A calculation-result digital signal
`of a senal form is generated in response to the second digital
`signal, the fourth digital signal, and the comparison-result
`digital signal. The calculation-result digital slgnal represents
`a value which is aPPmXimate 1° a square T°?t_°f aPUm of *1
`square of the value represented by the ?rst d1g1tal signal and
`a square of the value represented by the third digital signal.
`
`'
`
`-
`
`-
`
`-
`
`-
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`FOREIGN PATENT DOCUMENTS
`
`0238300 9/1987 European Pat. Off. .
`
`4 Claims, 9 Drawing Sheets
`
`l
`
`/V
`
`[,V
`
`Sa —><l>———*——+ ABSOLUTE
`
`Sb ——#<
`
`VALUE
`——> COMPA
`
`——————-+
`
`.
`
`'
`
`i
`
`So
`MUL ——<>-——>
`
`/V
`—--> ABSOLUTE —————-—>
`
`CALC
`
`-~*——~*
`
`|
`
`RTL345-2_1024-0001
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 1 of 9
`
`5,459,683
`
`FIG. 7 PRIOR ART
`
`.
`
`W2
`
`Sa
`
`N
`
`_
`
`“Pa: ""59
`'
`W3
`N-BIT
`I : MUL
`
`Sb
`N
`’?| 7
`
`‘
`
`N5
`?g‘é’T‘RE —<>-——>
`
`"+1
`1’
`
`,V
`M
`I,‘ _
`, "A35?
`"
`
`FIG. 2 PRIOR ART
`
`~97“
`Sb -N ""2? { "HEP
`
`_
`
`_
`
`S
`H
`was '11
`M "A39 / 3884‘RE 41H
`
`0
`
`_
`
`+
`
`RTL345-2_1024-0002
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 2 of 9
`
`5,459,683
`
`FIG.‘ 3
`
`;13
`
`N-BIT
`4 SUB
`
`I
`
`Wu J [V14
`a ,2‘. 2:52am +1"
`"I
`
`W17
`
`so
`
`I
`
`W12
`—§/V15 mp1s
`Sb
`N
`N-BIT
`N
`r
`u
`-—><5+> ABSOLUTE +—1>__’ "Q3? / "iBF
`VALUE
`i
`t
`
`.
`
`FIXED
`VALUE
`
`Sa
`
`Sb
`
`W20
`ABSOLUTE
`VALUE
`—> COMPA
`
`W22
`
`I
`
`A, 21
`ABSOLUTE
`VALUE
`CALC
`
`So
`MUL —-<>_-->
`
`'
`
`RTL345-2_1024-0003
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 3 of 9
`
`5,459,683
`
`FIG. 5
`
`'
`
`‘
`
`'
`
`'
`
`$20
`
`88
`—--—>O——-——-—¢——>
`Sb
`EX-OR -—» LATCH
`———><>
`
`N23
`
`W 24
`
`1'
`
`"—“’ 1-BIT
`
`ADD —-+ MPX —-+ EX-OR T 1 27
`
`
`
`
`3°
`
`5
`
`LATCH
`
`25“
`
`,
`
`1~BIT
`
`'
`
`NOT --+ ADD
`
`28
`5
`
`-
`
`LATCH
`
`RTL345-2_1024-0004
`
`

`
`US. Patent
`
`0a. 17, 1995
`
`Sheet 4 of 9
`
`5,459,683
`
`FIG. 6
`
`-
`
`34A
`
`SHIFT
`REGISTER 9 EH“
`
`-
`
`21A
`
`37A T‘
`36A
`I
`, 1-BIT
`Sd
`ADD
`
`"
`LATCH
`
`5 35A I
`
`38A
`
`I
`
`LATCH
`
`34B
`I
`SHIFT
`REGISTER
`
`_
`
`I
`
`36B
`
`'
`
`5 8
`
`373
`IV
`1~BIT
`_
`EX OR _’ ADD —?’_—’
`5 358
`I
`
`LATCH
`
`388
`
`F LATCH
`
`_"‘
`
`-
`
`Sb
`
`RTL345-2_1024-0005
`
`

`
`U.S. Patent
`
`Oct. 17, 1995
`
`Sheet 5 of 9
`
`I I I l|||I|llIu .!|IIull{Iu
`
`RTL345-2 1024-0006
`
`RTL345-2_1024-0006
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 6 of 9
`
`5,459,683
`
`F/G. 8
`
`I
`
`III
`
`SIGNAL Sa
`SIGNAL Sb
`
`EX-OR 23
`
`LATCH 24
`
`ADDER 26
`
`LATCH 27
`
`ADDER 28
`
`LATCH 29
`
`r ll roll
`
`
`
`Ill‘ lil
`
`HULTIPLEXER 30
`
`EX-OR 31
`
`FIG. 9
`
`SIGNAL
`Sb
`0;
`0
`S
`NEGATIVE
`NEGATIVE
`02
`0 S
`
`O;
`O S
`0;
`NEGATIVE
`NEGATIVE
`' NEGATIVE NEGATIVE
`NEGATIVE NEGATIVE
`
`RELATION BETWEEN
`Sa AND Sb
`
`NULTIPLEXER
`OUTPUT
`
`RTL345-2_1024-0007
`
`

`
`Ll
`
`«.1
`
`5,459,683
`
`SIGNAL Sc.
`
`9All
`
`0.....I....7
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`
`U.S. Patent
`
`MNNN
`
`.EEEE0maLVVVV0Mb<_.<__....I..H<__5...ul..U1-5---
`7.,FR34|
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`.allEEEE1!.Inn.3:run
`nun»amMMmw.R333ILILATHRHANFC0CNGIAT_T.GIH4AXAISS3..LELS
`
`RTL345-2_1024-0008
`
`RTL345-2_1024-0008
`
`
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 8 of 9
`
`5,459,683
`
`FIG. 72
`
`MULTIPLEXER 43
`
`MULTIPLEXER 44?; 15 0
`
`0
`
`0
`
`1| 0
`
`o 0 0 0
`
`0 1| 1
`
`1. 1| 0
`
`1: ..|| ||: |.... 5... 531:7: |..|
`
`
`
`1 0 0
`
`0 0 O ‘ 1|
`
`
`||| ||| III III ||| |..| 1:41: ii
`
`o O 0 4|
`
`0 1 0
`
`1| 0
`
`1 0 O
`
`ADDER 62
`
`ADOER 65
`
`ADDER 68
`
`ADDER 70
`
`0 a]
`
`0 All
`
`III
`
`1 0
`
`TIME
`
`RTL345-2_1024-0009
`
`

`
`US. Patent
`
`Oct. 17, 1995
`
`Sheet 9 0f 9
`
`5,459,683
`
`m @I
`
`mm
`
`R}
`>8.
`
`NN
`
`cm
`
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`
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`
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`
`w3<>
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`
`5
`
`mm
`
`>28 m3
`
`mm
`
`pm
`
`RTL345-2_1024-0010
`
`

`
`5,459,683
`
`1
`APPARATUS FOR CALCULATING THE
`SQUARE mm or THE SUM OF Two
`SQUARES
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`This invention relates to an apparatus for calculating the
`square root of the sum of the square of the value represented
`by a ?rst digital signal and the square of the value repre
`sented by a second digital signal.
`2. Description of the Prior Art
`In digital signal processing, some calculations are
`intended to derive the square root So of the sum of the square
`of a ?rst value represented by a ?rst digital signal and the
`square of a second value represented by a second digital
`signal. Speci?cally, the square root So is expressed as S0:
`: A2+B2 where “A” denotes the value represented by the
`?rst digital signal and “B” denotes the value represented by
`the second digital signal.
`As will be described later, prior-art apparatuses for such
`calculations tend to be complicated in structure.
`
`SUMMARY OF THE INVENTION
`
`It is an object of this invention to provide an improved
`calculation apparatus.
`This invention provides a calculation apparatus compris
`ing ?rst means for processing a ?rst digital signal of a serial
`form into a second digital signal of a serial form, the second
`digital signal representing an absolute value of a value
`represented by the ?rst digital signal; second means for
`processing a third digital signal of a serial form into a fourth
`digital signal of a serial form, the fourth digital signal
`representing an absolute value of a value represented by the
`third digital signal; third means for comparing the values
`represented by the ?rst and third digital signals, and gener
`ating a comparison-result digital signal representing a result
`of said comparing; and fourth means for generating a
`calculation-result digital signal of a serial form in response
`to the second digital signal, the fourth digital signal, and the
`comparison-result digital signal, the calculation-result digi
`tal signal representing a value which is approximate to a
`square root of a sum of a square of the value represented by
`the ?rst digital signal and a square of the value represented
`by the third digital signal.
`It is preferable that the ?rst means comprises a shift
`register for temporarily storing the ?rst digital signal; a ?rst
`latch for latching an MSB of the ?rst digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an
`output signal from the ?rst latch; a second latch for latching
`the MSB of the ?rst digital signal as an initial value; and a
`l-bit adder for adding an output signal from the Exclusive
`OR circuit and an output signal from the second latch, and
`generating the second digital signal; wherein the second
`latch is operative for latching a carry signal generated by the
`adder.
`It is preferable that the second means comprises a shift
`register for temporarily storing the third digital signal; a ?rst
`latch for latching an MSB of the third digital signal; an
`Exclusive-OR circuit for executing Exclusive-OR operation
`between an output signal from the shift register and an
`output signal from the ?rst latch; a second latch for latching
`the MSB of the third digital signal as an initial value; and a
`
`10
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`2
`l-bit adder for adding an output signal from the Exclusive
`OR circuit and an output signal from the second latch, and
`generating the fourth digital signal; wherein the second latch
`is operative for latching a carry signal generated by the
`adder.
`It is preferable that the third means comprises a ?rst
`Exclusive-OR circuit for executing Exclusive-OR operation
`between the ?rst digital signal and the third digital signal; a
`?rst latch for latching an output signal from the ?rst Exclu
`sive-OR circuit; an inverter for inverting the third digital
`signal; a ?rst l-bit adder for adding the ?rst digital signal
`and the second digital signal; a second latch for latching a
`carry signal generated by the ?rst adder; a second l-bit adder
`for adding the ?rst digital signal an output signal from the
`inverter; a third latch for latching a carry signal generated by
`the second adder; a multiplexer for selecting one of an
`output signal from the ?rst adder and an output signal from
`the second adder in response to an output signal from the
`?rst latch; and a second Exclusive-OR circuit for executing
`Exclusive-OR operation between the ?rst digital signal and
`an output signal from the multiplexer, and for generating the
`comparison-result signal in response to the ?rst digital signal
`and the output signal from the multiplexer.
`It is preferable that the fourth means comprises a ?rst
`multiplexer for selecting one of the second digital signal and
`the fourth digital signal in response to the comparison-result
`signal; a second multiplexer for selecting one of the second
`digital signal and the fourth digital signal in response to the
`comparison-result signal; a ?rst series combination of ?ip
`?ops successively storing an output signal from the ?rst
`multiplexer; a second series combination of ?ip-?ops suc
`cessively storing an output signal from the second multi
`plexer; a ?rst l-bit adder for adding am output signal from
`the ?rst combination of the ?ip-?ops and the output signal
`from the second multiplexer; a ?rst latch for latching a carry
`signal generated by the ?rst adder; a second l-bit adder for
`adding output signals from given ?ip-?ops in the second
`combination; a second latch for latching a carry signal
`generated by the second adder; a third l-bit adder for adding
`an output signal from the second combination of the flip
`?ops and an output signal from the second adder; a third
`latch for latching a carry signal generated by the third adder;
`a fourth l-bit adder for adding an output signal from the ?rst
`adder and an output signal from the third adder; and a fourth
`latch for latching a carry signal generated by the fourth
`adder.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a ?rst prior-art calculation
`apparatus.
`FIG. 2 is a block diagram of a second prior-art calculation
`apparatus.
`FIG. 3 is a block diagram of an approximate calculation
`apparatus.
`FIG. 4 is a block diagram of a calculation apparatus
`according to a ?rst embodiment of this invention.
`FIG. 5 is a block diagram of an absolute-value comparator
`in FIG. 4.
`FIG. 6 is a block diagram of an absolute-value calculator
`in FIG. 4.
`FIG. 7 is a block diagram of a multiplier in FIG. 4.
`FIG. 8 is a time-domain diagram of various signals in the
`absolute-value comparator of FIG. 5.
`FIG. 9 is a diagram of the relation among the values
`
`RTL345-2_1024-0011
`
`

`
`5,459,683
`
`3
`represented by input digital signals Sa and Sb, and the logic
`state of the output signal from a multiplexer 30 in the
`absolute-value comparator of FIG. 5.
`FIG. 10 is a diagram of the relation among the values
`represented by the input digital signals Sa and Sb, and the
`logic state of the output signal Sc from an Exclusive-OR
`circuit 31 in the absolute-value comparator of FIG. 5.
`FIG. 11 is a time-domain diagram of various signals in the
`absolute-value calculator of FIG. 6.
`FIG. 12 is a time-domain diagram of various signals in the
`multiplier of FIG. 7.
`FIG. 13 is a block diagram of a calculation apparatus
`according to a second embodiment of this invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Prior-art calculation apparatuses will now be described
`for a better understanding of this invention.
`FIG. 1 shows a ?rst prior-art calculation apparatus. As
`shown in FIG. 1, the ?rst prior-art calculation apparatus
`includes N~bit multipliers 2 and 3, an M-bit adder 4, and a
`square root calculator 5, where “N” and “M” denote given
`natural numbers respectively.
`An input N-bit digital signal Sa having a parallel form is
`applied to the multiplier 2 while another input N -bit digital
`signal Sb having a parallel form is applied to the other
`multiplier 3. The multiplier 2 calculates the square “Saz” of
`the value represented by the digital signal Sa, and outputs an
`M-bit digital signal indicating the calculated square “Sal”.
`The multiplier 3 calculates the square “Sb2” of the value
`represented by the digital signal Sb, and outputs an M-bit
`digital signal indicating the calculated square “8b”.
`The adder 4 receives the output signals from the multi
`pliers 2 and 3, and calculates the sum “Sa'2+Sb2” of the
`values “Sal” and ‘<‘Sb2” represented by the output signals
`from the multipliers 2 and 3. The adder 4 outputs an
`(M2+1)-bit digital signal indicating the calculated sum “Sa2+
`Sb ”.
`The square root calculator 5 receives the output signal
`from the adder 4, and calculates the square root
`“= Sa2+Sb2” of the value “Sa2+Sb2” represented by the
`output signal from the adder 4. The square root calculator 5
`outputs a digital signal So indicating the calculated square
`
`FIG. 2 shows a second prior-art calculation apparatus. As
`shown in FIG. 2, the second prior-art calculation apparatus
`includes an N-bit multiplexer 6, an N-bit multiplier 7, an
`M-bit latch 8, an M-bit adder 9, and a square root calculator
`10, where “N” and “M” denote given natural numbers
`respectively.
`An input N-bit digital signal Sa having a parallel form,
`and an input N-bit digital signal Sb having a parallel form
`are applied to the multiplexer 6. The multiplexer 6 sequen
`tially selects the digital signal Sa or the digital signal Sb, and
`passes the selected signal to the multiplier 7. When the
`multiplexer 6 selects the digital signal Sa and passes it to the
`multiplier 7, the multiplier 7 calculates the square “Sa2” of
`the value represented by the digital signal Sa and outputs an
`
`M-bit digital signal indicating the calculated square “Sa The latch 8 receives and holds the output signal from the
`multiplier 7 which represents the calculated square “Sa2”.
`When the multiplexer 6 selects the digital signal Sb and
`passes it to the multiplier 7, the multiplier 7 calculates the
`
`10
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`square “8b” of the value represented by the digital signal Sb
`and outputs an M-bit digital signal indicating the calculated
`square “Sb2”. In this case, the adder 9 receives the output
`signal from the multiplier 7 which represents the calculated
`square “Sb2”. At the same time, the adder 9 receives the
`output signal from the latch 8 which represents the calcu
`lated square “Sa2”.
`The adder 9 calculates the sum “Sa2+Sb2” of the values
`“8a” and “8b” represented by the output signals from the
`multiplier 7 and the latch 8. The adder 9 outputs an (M+l)
`bit digital signal indicating the calculated sum “Sa2+Sb2”.
`The square root calculator 10 receives the output signal
`from the adder 9, and calculates the square root
`“= Sa2+Sb2” of the value “Sa2+Sb2” represented by the
`output signal from the adder 9. The square root calculator 10
`outputs a digital signal So indicating the calculated square
`root “= Sa2+Sb2”.
`FIG. 3 shows an approximate calculation apparatus which
`is not prior art against this invention. As shown in FIG. 3, the
`approximate calculation apparatus includes N-bit absolute
`value calculators 11 and 12, an N-bit subtracter 13, N-bit
`multiplexers 14 and 15, an N-bit multiplier 16, and an M-bit
`adder 17, where “N” and “M” denote given natural numbers
`respectively.
`The approximate calculation apparatus of FIG. 3 is
`designed to operate on input N-bit digital signals Sa and Sb
`of a parallel form which represent an in-phase component
`and a quadrature component of a constant-envelope analog
`signal respectively. In this case, the square root of the sum
`of the square of the value “A” represented by the digital
`signal Sa and the square of the value “B” represented by the
`digital signal Sb is approximately given by the following
`equation.
`
`\I A2+B2 =MAX(|A|, |B|)+MlN(|Al, IB|)x(\I_2_ - 1)
`
`'
`
`(I)
`
`where MAX denotes an operator for selecting the greatest of
`two in the following parentheses, and MIN denotes an
`operator for selecting the smallest of two in the following
`parentheses.
`The input N-bit digital signal Sa is applied to the absolute
`value calculator 11 while the other input N-bit digital signal
`Sb is applied to the absolute-value calculator 12. The device
`11 calculates the absolute value “IAI” of the value “A”
`represented by the digital signal Sa, and outputs an N-bit
`digital signal indicating the calculated absolute value “IAI”.
`The device 12 calculates the absolute value “IBI” of the value
`“B” represented by the digital signal Sb, and outputs an
`N-bit digital signal indicating the calculated absolute value
`“IBI”.
`The subtracter 13 receives the output signals from the
`absolute-value calculators l1 and 12, and calculates a dif
`ference between the values “IAI” and “lBl” represented by
`the received signals. The subtracter 13 decides which of the
`values “IAI” and “IBI” is greater, and outputs a digital signal
`representing the result of the decision. The subtracter 13
`may be replaced by a comparator.
`The multiplexer 14 receives the output signals from the
`absolute-value calculators 11 and 12. Also, the multiplexer
`14 receives the output signal from the subtracter 13. The
`multiplexer 14 selects one of the output signals from the
`absolute-value calculators 11 and 12 in response to the
`output signal from the subtracter 13, and passes the selected
`signal to the adder 17. Speci?cally, the multiplexer 14
`selects one of the output signals from the absolute-value
`
`RTL345-2_1024-0012
`
`

`
`5,459,683
`
`5
`calculators 11 and 12 which corresponds to the greater of the
`values “IAI” and “IE1”. Thus, the multiplexer 14 has the
`function corresponding to the term “MAX(|A|, IBI)” in the
`equation (1).
`The multiplexer 15 receives the output signals from the
`absolute-value calculators 11 and 12. Also, the multiplexer
`15 receives the output signal from the subtracter 13. The
`multiplexer 15 selects one of the output signals from the
`absolute-value calculators 11 and 12 in response to the
`output signal from the subtracter 13, and passes the selected
`signal to the multiplier 16. Speci?cally, the multiplexer 15
`selects one of the output signals from the absolute-value
`calculators 11 and 12 which corresponds to the smaller of the
`values “IA!” and “IBI”. Thus,'the multiplexer 15 has the
`function corresponding to the term “MIN(lAl, IBI)” in the
`equation (1).
`The multiplier 16 receives the output signal from the
`multiplexer 15 which represents the value “MIN(IA[, IBI)”.
`Also, the multiplier 16 receives an output digital signal from
`a register or memory (not shown) which represents a ?xed
`value of : 2—-1. The multiplier 16 calculates the product of
`the value “MIN(IAl, IBI)” and the value “: 2-1”, and
`outputs a digital signal indicating the calculated product
`“MIN(|A|, IBI)><(= §—1)”.
`The adder 17 receives the output signal from the multi
`plexer 14 which represents the value “MAXUAI, IBI)”. Also,
`the adder 17 receives the output signal from the multiplier 16
`which represents the value “MIN(|Al, |Bl)><(= 2-1)”. The
`adder 17 calculates the sum of the values represented by the
`output signals from the multiplexer 14 and the multiplier 16,
`and outputs a digital signal So indicating the calculated sum
`“MAXOAI, IBI)+MIN(IA|, lB|)x(= 2-1)”. In this way, the
`adder 17 outputs a digital signal So representing the right
`hand side of the equation (1) which is approximate to the
`value “= A2+B2”.
`In cases where the hit number “N” of the input digital
`signals Sa and Sb is great, the prior-art calculation appara
`tuses of FIGS. 1 and 2 and the approximate calculation
`apparatus of FIG. 3 tend to be complicated in structure since
`the adders and the multipliers therein need, large numbers of
`gates.
`FIG. 4 shows a calculation apparatus according to a ?rst
`embodiment of this invention. As shown in FIG. 4, the
`calculation apparatus includes an absolute-value comparator
`20, an absolute-value calculator 21, and a multiplier 22.
`The absolute-value comparator 20 and the absolute-value
`calculator 21 are connected to the multiplier 22. Input digital
`signals Sa and Sb having a serial form are applied to the
`absolute-value comparator 20 and the absolute-value calcu
`lator 21. The absolute-value comparator 20 generates a
`digital signal Sc in response to the input digital signals Sa
`and Sb, and outputs the generated signal Sc to the multiplier
`22. The absolute~value calculator 21 generates digital sig
`nals Sd and Se in response to the input digital signals Sa and
`Sb, and outputs the generated signals Sd and Se to the
`multiplier 22. The multiplier 22 generates a digital signal So
`in response to the digital signals Sc, Sd, and Se, and outputs
`the generated digital signal So.
`As shown in FIG. 5, the absolute-value comparator 20
`includes an Exclusive-OR circuit 23, a latch 24, a NOT
`circuit (an inverter) 25, a 1-bit adder 26, a latch 27, a l-bit
`adder 28, a latch 29, a multiplexer 30, and an Exclusive-OR
`circuit 31.
`The input digital signals Sa and Sb are applied to ?rst and
`second input sides of the Exclusive-OR circuit 23 respec
`tively. The output side of the Exclusive-OR circuit 23 is
`connected to the input side of the latch 24. The output side
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`45
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`55
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`65
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`15
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`20
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`25
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`30
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`35
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`6
`of the latch 24 is connected to a control terminal of the
`multiplexer 30. The input digital signals Sa and Sb are
`applied to ?rst and second input sides of the adder 26
`respectively. The output side of the adder 26 is connected to
`a ?rst input side of the multiplexer 30. A carry terminal of
`the adder 26 is connected to the latch 27. The input digital
`signal Sa is applied to a ?rst input side of the adder 28. The
`input digital signal Sb is applied to the input side of the NOT
`circuit 25. The output side of the NOT circuit 25 is con~
`nected to a second input side of the adder 28. The output side
`of the adder 28 is connected to a second input side of the
`multiplexer 30. A carry terminal of the adder 28 is connected
`to the latch 29. The output side of the multiplexer 30 is
`connected to a ?rst input side of the Exclusive-OR circuit
`31. A second input side of the Exclusive-OR circuit 31 is
`subjected to the input digital signal Sa. The output side of the
`Exclusive-OR circuit 31 is followed by the multiplier 22 of
`FIG. 4.
`The circuit 23 executes Exclusive-OR operation between
`the input digital signals Sa and Sb. The output signal from
`the Exclusive-OR circuit 23 is held by the latch 24 before
`being transmitted to the multiplexer 30. The device 26 adds
`the input digital signals S21 and Sb. The output signal from
`the adder 26 is fed to the multiplexer 30. The latch 27 holds
`a carry signal generated by the adder 26. The input digital
`signal Sb is inverted by the NOT circuit 25. The output
`signal from the NOT circuit 25 is applied to the adder 28.
`The device 28 adds the input digital signal Sa and the output
`signal from the NOT circuit 25. The output signal from the
`adder 28 is fed to the multiplexer 30. The latch 29 holds a
`carry signal generated by the adder 28. The multiplexer 30
`selects one of the output signals from the adders 26 and 28
`in response to the output signal from the latch 24, and passes
`the selected signal to the Exclusive-OR circuit 31. The
`circuit 31 executes Exclusive-OR operation between the
`input digital signal Sa and the output signal from the
`multiplexer 30. The output signal from the Exclusive~OR
`circuit 31 is used as a signal Sc fed to the multiplier 22 of
`FIG. 4.
`As shown in FIG. 6, the absolute-value calculator 21 is
`separated into ?rst and second portions 21A and 21B which
`operate on the input digital signals Sa and Sb respectively.
`The ?rst portion 21A of the absolute-value calculator 21
`includes a shift register 34A, a latch 35A, an Exclusive-OR
`circuit 36A, a l-bit adder 37A, and a latch 38A.
`The input digital signal Sa is applied to the input side of
`the shift register 34A. The output side of the shift register
`34A is connected to a ?rst input side of the Exclusive-OR
`circuit 36A. The input digital signal Sa is applied to the input
`side of the latch 35A. The output side of the latch 35A is
`connected to a second input side of the Exclusive-OR circuit
`36A. The output side of the Exclusive-OR circuit 36A is
`connected to the input side of the adder 37A. The output side
`of the adder 37A is followed by the multiplier 22 of FIG. 4.
`A carry terminal of the adder 37A is connected to the latch
`38A. The input digital signal Sa is applied to the latch 38A.
`Sequential bits of the input digital signal Sa are written
`into the shift register 34A one by one, being shifted from
`storage segments to subsequent storage segments in the shift
`register 34A before being outputted from the shift register
`34A one by one. Thus, the shift register 34A delays the input
`digital signal Sa by a predetermined time. The output signal
`from the shift register 34A, that is, the delay-resultant signal,
`is fed to the Exclusive-OR circuit 36A. The highest bit (sign
`bit, MSB) of the input digital signal Sa is held by the latch
`35A before being fed to the Exclusive-OR circuit 36A. The
`circuit 36A executes Exclusive-OR operation between the
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`RTL345-2_1024-0013
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`5,459,683
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`7
`output signals from the shift register 34A and the latch 35A.
`The output signal from the Exclusive-OR circuit 36A is fed
`to the adder 37A. The highest bit (sign bit, MSB) of the input
`digital signal Sa is stored into the latch 38A to initialize the
`latch 38A. The device 37A adds the output signals from the
`Exclusive-OR circuit 36A and the latch 38A. The latch 38A
`holds a carry signal generated by the adder 37A. The output
`signal from the adder 37A is used as a signal Sd fed to the
`multiplier 22 of FIG. 4.
`The second portion 21B of the absolute-value calculator
`21 includes a shift register 34B, a latch 35B, an Exclusive
`OR circuit 36B, a l-bit adder 373, and a latch 38B.
`The input digital signal Sb is applied to the input side of
`the shift register 34B. The output side of the shift register
`34B is connected to a ?rst input side of the Exclusive-OR
`circuit 36B. The input digital signal Sb is applied to the input
`side of the latch 35B. The output side of the latch 35B is
`connected to a second input side of the Exclusive-OR circuit
`36B. The output side of the Exclusive-OR circuit 36B is
`connected to the input side of the adder 37 B. The output side
`of the adder 37B is followed by the multiplier 22 of FIG. 4.
`A carry terminal of the adder 37B is connected to the latch
`38B. The input digital signal Sb is applied to the latch 38B.
`Sequential bits of the input digital signal Sb are written
`into the shift register 34B one by one, being shifted from
`storage segments to subsequent storage segments in the shift
`register 34B before being outputted from the shift register
`348 one by one. Thus, the shift register 34B delays the input
`digital signal Sb by a predetermined time. The output signal
`from the shift register 34B, that is, the delay-resultant signal,
`is fed to the Exclusive-OR circuit 36B. The highest bit (sign
`bit, MSB) of the input digital signal Sb is held by the latch
`358 before being fed to the Exclusive-OR circuit 36B. The
`circuit 36B executes Exclusive-OR operation between the
`output signals from the shift register 34B and the latch 35B.
`The output signal from the Exclusive-OR circuit 36B is fed
`to the adder 37B. The highest bit (sign bit, MSB) of the input
`digital signal Sb is stored into the latch 38B to initialize the
`latch 38B. The device 37B adds the output signals from the
`Exclusive-OR circuit 36B and the latch 38B. The latch 38B
`holds a carry signal generated by the adder 37B. The output
`signal from the adder 37B is used as a signal Se fed to the
`multiplier 22 of FIG. 4.
`As shown in FIG. 7, the multiplier 22 includes multiplex
`ers 43 and 44, latches 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
`55, and 56, l-bit adders 62, 65, 68, and 70, and latches 63,
`66, 69, and 71.
`The output signals Sd and Se from the absolute-value
`calculator 21 are applied to ?rst and second input sides of the
`multiplexer 43 respectively. The output signal Sc from the
`absolute-value comparator 20 is applied to a control terminal
`of the multiplexer 43. The output signals Sd and Se from the
`absolute-value calculator 21 are applied to ?rst and second
`input sides of the multiplexer 44 respectively. The output
`signal Sc from the absolute-value comparator 20 is applied
`to a control terminal of the multiplexer 44. The output
`terminal of the multiplexer 43 is successively followed by
`the latches 45, 46, 47, 48, 49, 50, and 51. The output side of
`the latch 51 is connected to a ?rst input side of the adder 62.
`The output terminal of the multiplexer 44 is successively
`followed by the latches 52, 53, 54, 55, and 56. The output
`side of the multiplexer 44 is also connected to a second input
`side of the adder 62. A carry terminal of the adder 62 is
`connected to the latch 63. The output side of the latch 53 is
`connected to a ?rst input side of the adder 65. The output
`side of the latch 55 is connected to a second input side of the
`adder 65. A carry terminal of the adder 65 is connected to the
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`latch 66. The output side of the adder 65 is connected to a
`?rst input side of the adder 68. The output side of the latch
`56 is connected to a second input side of the adder 68. A
`carry terminal of the adder 68 is connected to the latch 69.
`The output side of the adder 62 is connected to a ?rst input
`side of the adder 70. The output side of the adder 68 is
`connected to a second input side of the adder 70. A carry
`terminal of the adder 70 is connected to the latch 71. The
`adder 70 outputs a digital signal So.
`The multiplexer 43 selects one of the output signals Sd
`and Se from the absolute-value calculator 21 in response to
`the output signal Sc from the absolute-value comparator 20,
`and passes the selected signal to the latch 45. The output
`signal from the multiplexer 43 is successively held by the
`latches 45, 46, 47, 48, 49, 50, and 51 before being outputted
`from the latch 51. The combination of the latches 45—51
`delays the output signal from the multiplexer 43 by a
`predetermined time. Each of the latches 4551 includes a
`?ip-?op. The output signal Sg from the latch 51, that is, the
`delay-resultant signal, is fed to the adder 62.
`The multiplexer 44 selects one of the output signals Sd
`