IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of: Morton et al.
`U.S. Patent No.: 7,296,121
`Issue Date:
`Nov. 13, 2007
`Appl. Serial No.: 10/966,161
`Filing Date:
`Oct. 15, 2004
`Title:
`REDUCING PROBE TRAFFIC IN MULTIPROCESSOR
`SYSTEMS
`
`IPR Control No.: IPR2015-01376
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 7,296,121 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`

`
`U.S. Patent No.: 7,296,121
`
`TABLE OF CONTENTS
`
`6.
`
`3.
`4.
`5.
`
`I. MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1) ................................ 2
`A. Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) ................................ 2
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2) ......................................... 2
`C. Lead And Back-Up Counsel and Service Information ............................. 3
`II. PAYMENT OF FEES – 37 C.F.R. § 42.103 ....................................................... 4
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ............................... 4
`A. Grounds for Standing Under § 42.104(a) ................................................. 4
`B. Challenge Under § 42.104(b) and Relief Requested ................................ 4
`C. Claim Construction under 37 C.F.R. §§ 42.104(b)(3) .............................. 6
`1.
`“processing node” (claims 1, 2, 8, 11, 15, 16, 25) .......................... 6
`2.
`“interconnected by a first point-to-point architecture” (claims 1,
`16, 25) .............................................................................................. 8
`“probe” (claims 1-3, 8, 11, 15-17, 19, 20, 22, 24, 25) .................... 9
`“probe filtering information” (claims 1, 3, 16, 25) ....................... 10
`“states associated with selected ones of the cache memories”
`(claims 1, 16, 25) ........................................................................... 11
`“transmit the probes only to selected ones of the processing
`nodes” (claims 1 and 16) ............................................................... 12
`“cache coherence controller” (claim 3) ......................................... 13
`7.
`“cache coherence directory” (claim 3) .......................................... 14
`8.
`“the probes” (claim 8) ................................................................... 15
`9.
`IV. SUMMARY OF THE ‘121 PATENT .............................................................. 16
`A. Brief Technology Overview ................................................................... 16
`B. Brief Description of the ‘121 Patent ....................................................... 19
`C. Summary of the Prosecution History of the ‘121 Patent ........................ 20
`V. MANNER OF APPLYING CITED PRIOR ART TO EVERY CLAIM FOR
`WHICH IPR IS REQUESTED, THUS ESTABLISHING A REASONABLE
`LIKELIHOOD THAT AT LEAST ONE CLAIM OF THE ‘121 PATENT IS
`UNPATENTABLE ........................................................................................ 21
`A. Pong Anticipates Claims 1-3, 8, 11, 12, 15, 16, 25. ............................... 21
`1.
`Pong Anticipates Claim 1 .............................................................. 24
`2.
`Pong Anticipates Claim 2 .............................................................. 28
`3.
`Pong Anticipates Claim 3 .............................................................. 29
`4.
`Pong Anticipates Claim 8 .............................................................. 30
`5.
`Pong anticipates Claim 11 ............................................................. 31
`6.
`Pong Anticipates Claim 12 ............................................................ 33
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`i
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`U.S. Patent No.: 7,296,121
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`Pong Anticipates Claim 15 ............................................................ 36
`7.
`Pong Anticipates Claim 16 ............................................................ 37
`8.
`Pong Anticipates Claim 25 ............................................................ 38
`9.
`B. Pong in view of Smith Renders Claims 17-24 Obvious ......................... 46
`VI. CONCLUSION ................................................................................................ 50
`
`
`ii
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`

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`
`APPL-1001
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`APPL-1002
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`APPL-1003
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`APPL-1004
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`APPL-1005
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`U.S. Patent No.: 7,296,121
`
`EXHIBITS
`
`U.S. Patent Number 7,296,121 to Morton et al. (“the ‘121 Pa-
`tent”)
`
`Excerpts from the Prosecution History of the ‘121 Patent (“the
`Prosecution History”)
`
`U.S. Patent Application Publication Number 2002/0053004 to
`Pong (“Pong”)
`
`David Chaiken et al., “Directory-Based Cache Coherence in
`Large-Scale Multiprocessors,” Computer vol. 24, issue 9 (Jun
`1990) (“Chaiken”)
`
`Daniel Lenoski et al., “The Directory-Based Cache Coherence
`Protocol for the DASH Multiprocessor,” ISCA ‘90 Proceedings
`of the 17th annual international symposium on Computer Ar-
`chitecture, pp. 148-159 (May 1990) (“Stanford DASH”)
`
`APPL-1006
`
`U.S. Patent Number 6,490,661 to Keller et al (“Keller”)
`
`APPL-1007
`
`APPL-1008
`
`Excerpts from Jose Duato et al., INTERCONNECTION NETWORKS
`– AN ENGINEERING APPROACH (1997) (“Duato”)
`
`Michael John Sebastian Smith, APPLICATION-SPECIFIC INTE-
`GRATED CIRCUITS (1997) (“Smith”)
`
`APPL-1009
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`U.S. Patent No. 7,698,509 to Koster et al. (“Koster”)
`
`APPL-1010
`
`U.S. Patent No. 7,315,919 to O’Krafka et al. (“O’Krafka”)
`
`APPL-1011
`
`U.S. Patent No. 6,338,122 to Baumgartner et al. (“Baumgart-
`ner”)
`
`iii
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`

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`U.S. Patent No.: 7,296,121
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`APPL-1012
`
`Anant Agarwal et al., “An Evaluation of Directory Schemes for
`Cache Coherence,” Conference Proceedings of 15th Annual In-
`ternational Symposium on Computer Architecture (1988)
`
`APPL-1013
`
`Louis G. Johnson, “Multiprocessors,” ECEN 6253 Lecture
`Notes (April 28, 2003)
`
`APPL-1014
`
`Declaration of Dr. Robert Horst
`
`APPL-1015
`
`APPL-1016
`
`APPL-1017
`
`APPL-1018
`
`APPL-1019
`
`Excerpts from Merriam-Webster's Collegiate Dictionary - 10th
`Ed. (2001)
`
`Redacted Letter of March 28, 2014 from Memory Integrity’s
`Counsel to Samsung’s Counsel in Memory Integrity LLC v.
`Samsung Electronics Co., Ltd. et al., Case No. 1:13-cv-01808-
`GMS, including “Response to Samsung’s Allegation of a Rule
`11 Violation”
`
`Luca Benini and Giovanni De Micheli, “Networks on chips: a
`new SoC paradigm,” Computer vol. 35, issue 1 (Jan. 2002)
`(“Benini”)
`
`“HyperTransport™ Technology I/O Link - A High-Bandwidth
`I/O Architecture” (Jul. 20, 2001) (“HyperTransport”)
`
`U.S. Publication No. 2005/0228952 to Mayhew et al. (“May-
`hew”)
`
`APPL-1020
`
`U.S. Patent No. 6,662,277 to Gaither (“Gaither”)
`
`
`
`
`
`iv
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`

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`U.S. Patent No.: 7,296,121
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`Sony Corp., Sony Electronics Inc., Sony Mobile Communications AB, and
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`Sony Mobile Communications (USA) Inc., (collectively “Sony”) and LG
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`Electronics, Inc., LG Electronics USA, Inc., and LG Electronics Mobilecomm
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`USA, Inc., (collectively “LG”) (collectively “Petitioners”) petition for Inter Partes
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`Review (“IPR”) under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42 of claims 1-3, 8,
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`11, 12,1 and 15-25 (“the Challenged Claims”) of U.S. Patent No. 7,296,121 (“the
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`‘121 Patent”) based on the substantively identical grounds as instituted for the
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`pending IPR Proceeding, IPR2015-00159. For the exact same reasons previously
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`considered by the Board, on the exact same schedule, Petitioners respectfully seek
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`to join IPR2015-00159.
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`In this petition, Petitioners assert substantively identical arguments that the
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`Board has already instituted in IPR2015-00159. This petition does not add to or
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`alter any argument that has already been considered by the Board, and this petition
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`does not seek to expand the grounds of unpatentability that the Board has already
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`instituted or subject to reconsideration. Accordingly, and as explained below, there
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`exists a reasonable likelihood that Petitioners will prevail in demonstrating
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`1 Claim 12 is subject to a Motion for Reconsideration in the Apple IPR. See
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`IPR2015-00159, Paper 14. Petitioners include claim 12 here merely to conform to
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`the Apple IPR petition and current motions.
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`1
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`

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`U.S. Patent No.: 7,296,121
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`unpatentability of at least one Challenged Claim based on teachings set forth in the
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`references presented in this petition.
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`Because this Petition is filed within one month of the institution of IPR2015-
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`00159, and because this Petition is accompanied by a Motion for Joinder, this peti-
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`tion is timely and proper under 35 U.S.C. §315(c).
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`I. MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1)
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`A. Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1)
`Sony Corp., Sony Electronics Inc., Sony Mobile Communications AB, and
`
`
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`Sony Mobile Communications (USA) Inc., (collectively “Sony”) LG Electronics,
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`Inc., LG Electronics USA, Inc., and LG Electronics Mobilecomm USA, Inc., (col-
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`lectively “LG”) are the real parties-in-interest.
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`B. Related Matters Under 37 C.F.R. § 42.8(b)(2)
`Petitioners are not aware of any disclaimers, reexamination certificates or
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`petitions for inter partes review for the ‘121 Patent. The ‘121 Patent is the subject
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`of Civil Action Numbers 1:13-cv- 1795 (Del.), 1:13-cv- 1796 (Del.), 1:13-cv- 1797
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`(Del.), 1:13-cv- 1798 (Del.), 1:13-cv- 1799 (Del.), 1:13-cv- 1800 (Del.), 1:13-cv-
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`1801 (Del.), 1:13-cv- 1802 (Del.), 1:13-cv- 1803 (Del.), 1:13-cv- 1804 (Del.),
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`1:13-cv- 1805 (Del.), 1:13-cv- 1806 (Del.), 1:13-cv- 1807 (Del.), 1:13-cv- 1808
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`(Del.), 1:13-cv- 1809 (Del.), 1:13-cv- 1810 (Del.), 1:13-cv- 1811 (Del.), all filed
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`November 1, 2013; and Civil Action Numbers 1:13-cv- 1981 (Del.), 1:13-cv- 1982
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`2
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`

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`U.S. Patent No.: 7,296,121
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`(Del.), 1:13-cv- 1983 (Del.), 1:13-cv- 1984 (Del.), all filed November 26, 2013.
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`The ‘121 Patent is subject to the following IPR proceedings IPR2015-00158
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`(instituted), IPR2015-00159 (instituted), IPR2015-00161 (not instituted), IPR2015-
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`00163 (instituted), and IPR2015-00172 (not instituted); IPR2015-01353 (pending).
`
`C. Lead And Back-Up Counsel and Service Information
`Pursuant to 37 C.F.R. §§ 42.8(b)(3), (b)(4), and 42.10(a), Petitioners desig-
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`nate the following lead and backup counsel:
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`Lead Counsel:
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`Lewis V. Popovski (Reg. No. 38,139)
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`Backup Counsel for Sony:
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`Backup Counsel for LG:
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`Service information for Sony:
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`Service Information for LG:
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`Zaed M. Billah (Reg. No. 71,418)
`Michael E. Sander (Reg. No. 71,667)
`
`Henry Petri (Reg. No. 33,063)
`Sunwoo Lee (Reg. No. 43,337)
`Ryan Murphy (Reg. No. 66,285)
`Jay Guiliano (Reg. No. 41,810)
`
`Lewis V. Popovski
`Zaed M. Billah
`Michael E. Sander
`Kenyon & Kenyon LLP
`One Broadway
`New York, NY
`Telephone: 212.425.7200
`Fax: 212.425.5288
`Email: MemoryIntegrityv.Sony10760-
`225@kenyon.com
`Email: lpopovski@kenyon.com
`Email: zbillah@kenyon.com
`Email: msander@kenyon.com
`
`Henry Petri
`Sunwoo Lee
`
`3
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`

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`U.S. Patent No.: 7,296,121
`
`Ryan Murphy
`Jay Guiliano
`Novak Druce Connolly Bove + Quigg LLP
`1875 Eye Street, N.W.
`Eleventh Floor
`Washington, D.C. 20006
`Telephone: 202.331.7111
`Fax: 202.293.6229
`Email: henry.petri@novakdruce.com
`Email: sunwoo.lee@novakdruce.com
`Email: ryan.murphy@novakdruce.com
`Email: jay.guiliano@novakdruce.com
`
`PAYMENT OF FEES – 37 C.F.R. § 42.103
`
`II.
`Petitioners authorize the Patent and Trademark Office to charge Deposit Ac-
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`count No. 110600 for the fee set in 37 C.F.R. § 42.15(a) for this Petition and fur-
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`ther authorizes for any additional fees to be charged to this Deposit Account.
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
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`A. Grounds for Standing Under § 42.104(a)
`Petitioners each certify that the ‘121 Patent is available for IPR. The present
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`petition is being filed within one month of institution of IPR2015-00159 along
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`with a Motion for Joinder. Accordingly, none of the Petitioners is barred or es-
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`topped from requesting this review on the below-identified grounds.
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`B. Challenge Under § 42.104(b) and Relief Requested
`Petitioners request IPR of the Challenged Claims on the grounds set forth in
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`the table shown below, and requests that each of the Challenged Claims be found
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`unpatentable. An explanation of unpatentability under the statutory grounds identi-
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`4
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`

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`U.S. Patent No.: 7,296,121
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`fied below is provided in the form of detailed description that follows, indicating
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`where each element can be found in the cited prior art, and the relevance of that
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`prior art. Additional explanation and support for each ground of rejection is set
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`forth in Ex. 1014, Declaration of Dr. Robert Horst.
`
`Basis for Rejection
`‘121 Patent Claims
`Ground
`Ground 1 1-3, 8, 11, 12, 15, 16, 25 §102: Pong
`Ground 2 17-24
`§103: Pong and Smith
`
`The ‘121 Patent issued from U.S. patent application number 10/966,161,
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`which was filed as a continuation-in-part on October 15, 2004, and which includes
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`a claim of priority to U.S. Application No. 10/288,347, filed on November 4, 2002,
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`now Patent No. 7,003,633. Petitioners note that the claims ultimately granted in
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`the ‘121 Patent are not fully supported by the priority application2; the earliest ef-
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`fective filing date for those claims is therefore no earlier than October 15, 2004.
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`Pong qualifies as prior art at least under 35 U.S.C. § 102(a) and (e). Specifi-
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`cally, Pong (Ex. 1003) was filed on November 19, 1999 as application number
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`09/444,173, and was published on May 2, 2002, before even the earliest pro-
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`claimed filing date of the ‘121 Patent. Duato and Smith qualify as prior art under
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`2 For example, the term “probe filtering unit” does not appear anywhere in the pri-
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`ority application, but there is extensive discussion about the probe filtering unit in
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`the ‘121 Patent beginning with the added Figure 18.
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`5
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`

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`U.S. Patent No.: 7,296,121
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`35 U.S.C. § 102(b). Specifically, Duato (Ex. 1007) and Smith (Ex. 1008) were
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`each published in 1997, more than a year before even the earliest proclaimed filing
`
`date of the ‘121 Patent. Gaither qualifies as prior art under 35 U.S.C. § 102(e), be-
`
`cause it was filed on July 31, 2001, before even the earliest proclaimed filing date
`
`of the ‘121 Patent.
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`C. Claim Construction under 37 C.F.R. §§ 42.104(b)(3)
`Each term of a claim subject to IPR is given its “broadest reasonable con-
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`struction in light of the specification of the patent in which it appears.” 3 37 C.F.R.
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`§ 42.100(b). Accordingly, for purposes of this proceeding only, Petitioners submit
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`constructions for the following terms, and submits that all remaining terms should
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`be given their plain meaning.
`
`1. “processing node” (claims 1, 2, 8, 11, 15, 16, 25)
`The ‘121 Patent does not provide an explicit definition for the term “pro-
`
`cessing node.” However, on its face, the word “processing” indicates the presence
`
`of a “processor” and, in modifying the word “node” indicates that the node in-
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`cludes or is otherwise associated with a processor. See Ex. 1014, ¶ 24. The ‘121
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`3 Because the standards of claim interpretation applied in litigation differ from
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`PTO proceedings, any interpretation of claim terms in this IPR is not binding upon
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`Petitioners in any litigation(s) related to the subject patent. See In re Zletz, 13
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`USPQ2d 1320, 1322 (Fed. Cir. 1989).
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`6
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`

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`U.S. Patent No.: 7,296,121
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`Patent supports this notion in its description and usage of the terms “processor”
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`and “node.” In particular, the ‘121 Patent notes that “the terms node and processor
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`are often used interchangeably herein.” Ex. 1001, 6:52-54. “However, it should
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`be understood that, according to various implementations, a node (e.g., processors
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`202a-202d) may comprise multiple sub-units, e.g., CPUs, memory controllers, I/O
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`bridges, etc.” Ex. 1001, 6:54-57. FIG. 19 shows one exemplary implementation of
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`such a processing node. See Ex. 1001, 27:25-28. Based on this example and the
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`aforementioned description of “node” as encompassing, in some implementations,
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`multiple subunits that may be processors (e.g., CPUs), the ‘121 Patent describes a
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`processing node that includes at least one processor. See Ex. 1014, ¶ 24.
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`The ‘121 Patent further describes these processing nodes as end-points with-
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`in a larger interconnected system. Ex. 1001, 27:32-40. Indeed, independent claims
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`1, 16, and 25 recite the plurality of processing nodes as being “interconnected by a
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`first point-to-point architecture” and as being included in “a computer system” and,
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`hence, as being a computer subsystem. See Ex. 1014, ¶ 25.
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`The Baumgartner reference (U.S. Patent No. 6,338,122) (Ex. 1011), which is
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`in the same field of art as the ‘121 Patent, demonstrates common usage of the term
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`“processing node,” and in doing so reveals that persons of skill would have under-
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`stood the term in a manner consistent with the above-noted interpretation: “Pro-
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`cessing nodes 8a-8n may each include M (M ≥ 1) processors 10, a local intercon-
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`7
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`U.S. Patent No.: 7,296,121
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`nect 16, and a system memory 18…” (emphasis added). Ex. 1011, 3:17-19 and
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`Fig. 1. See Ex. 1014, ¶ 26.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “processing
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`node” as broad enough to encompass “an interconnectable computer subsystem
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`comprising at least one processor.” See Ex. 1014, ¶ 23.
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`2. “interconnected by a first point-to-point architecture”
`(claims 1, 16, 25)
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`In a co-pending litigation, the Patent Owner has asserted that the term “in-
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`terconnected by a first point-to-point architecture” reads on any system of proces-
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`sors that uses point-to-point links and they have contrasted this with “a shared-bus
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`architecture.” See Ex. 1016, pp. 1-2. In particular, in response to questions asked
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`about the scope of the claimed point-to-point architecture, the Patent Owner indi-
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`cated that the claimed point-to-point architecture is broad enough to cover Figure
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`1B of the ‘121 Patent by stating:
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`Indeed, this is consistent with what the ‘121 Patent shows in Figure
`1B, which the Patent's specification describes as a point-to-point ar-
`chitecture that can use the techniques of the patented invention. See
`‘121 Patent, Fig. 1B and 6:24-35. Further, the patent notes that the
`use of a switch as shown in Figure 1B is advantageous because it “al-
`lows implementation with fewer point-to-point links.”
`See id. at 2 (emphasis added).
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`8
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`U.S. Patent No.: 7,296,121
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`In view of the Patent Owner’s assertions, for purposes of this proceeding in
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`which the broadest reasonable construction standard applies, it is appropriate to
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`construe the term “interconnected by a first point-to-point architecture” as broad
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`enough to encompass “connected to each other using point-to-point links.”
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`3. “probe” (claims 1-3, 8, 11, 15-17, 19, 20, 22, 24, 25)
`The ‘121 Patent specification defines the term “probe” as a “mechanism for
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`eliciting a response from a node to maintain cache coherency in a system.” Ex.
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`1001, 5:45-47 (“A mechanism for eliciting a response from a node to maintain
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`cache coherency in a system is referred to herein as a probe.”). Consistent with
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`this definition, the ‘121 Patent specification uses the term probe broadly to de-
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`scribe messages used for snooping cache, as well as messages that carry infor-
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`mation for maintaining cache coherency in a system. Ex. 1001, 5:47-48 (“In one
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`example, a mechanism for snooping a cache is referred to as a probe.”) and 11-66-
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`67 (“any message for snooping a cache can be referred to as a probe.”) and 11: 20-
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`23 (“While probes and probe responses carry information for maintaining cache
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`coherency in the system, read responses can carry actual fetched data.”). See Ex.
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`1014, ¶ 27.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “probe” as
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`9
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`U.S. Patent No.: 7,296,121
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`broad enough to encompass “a mechanism that elicits a response from a node to
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`maintain cache coherency in a system.” See Ex. 1014, ¶ 27.
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`4. “probe filtering information” (claims 1, 3, 16, 25)
`The ‘121 Patent defines the term “probe filtering information” as “[a]ny cri-
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`terion that can be used to reduce the number of clusters or nodes probed.” Ex.
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`1001, 14:50-52 (“[a]ny criterion that can be used to reduce the number of clusters
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`or nodes probed is referred to herein as probe filter information.”). The ‘121 Pa-
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`tent uses the term probe filtering information consistent with this definition. For
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`instance, when describing its figures, the ‘121 Patent specification points out that
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`Fig. 8 shows a diagram representing probe filter information, and, consistent with
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`its definition for that term, the ‘121 Patent specification points out that the Fig. 8
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`probe filtering information “can be used to reduce the number of transactions in a
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`multiple or single cluster system.” Ex. 1001, 14:48-50. Similarly, according to
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`claim 3, the probe filtering information may comprise a cache coherence directory
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`which includes entries corresponding to memory lines stored in the selected cache
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`memories. Ex. 1001, 31:12-16. See Ex. 1014, ¶¶ 28-29.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “probe fil-
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`tering information” as broad enough to encompass “any criterion that can be used
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`to reduce the number of clusters or nodes probed.” See Ex. 1014, ¶ 28.
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`10
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`

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`U.S. Patent No.: 7,296,121
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`5. “states associated with selected ones of the cache
`memories” (claims 1, 16, 25)
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`The ‘121 Patent does not provide an explicit definition for the term “states
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`associated with selected ones of the cache memories.” In fact, the ‘121 Patent fails
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`to limit the recited “states” to a specific type of state nor even to a particular group
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`of states, such as standard coherence protocol states. See Ex. 1001, 14:30-36. To
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`illustrate, rather than limiting states to standard coherence protocol states, the ‘121
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`Patent notes that “[t]he techniques of the present invention can be used with a vari-
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`ety of different possible memory line states.” See id.
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`Merriam Webster’s Dictionary defines the word “state” as “mode or condi-
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`tion of being,” which is exemplified by presence. See Ex. 1015, pp. 1145, 919 (de-
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`fining “presence” as “the fact or condition of being present” (emphasis added)).
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`The ‘121 Patent uses the term “state” consistent with this definition. For example,
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`the ‘121 Patent describes that a “directory of shared states . . . indicates where par-
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`ticular memory lines are cached within the cluster.” Ex. 1001, 28:29-34.
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`Furthermore, the Chaiken reference (Ex. 1004), which is in the same field of
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`art as the ‘121 Patent, uses the word “status” to reference state in a manner con-
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`sistent with the above-noted interpretation, and, thus, further supports the assertion
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`that presence is one example of a type of state: “The full-map protocol uses direc-
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`tory entries with one bit per processor and a dirty bit. Each bit represents the status
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`11
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`of the block in the corresponding processor’s cache (present or absent).” Ex. 1004,
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`U.S. Patent No.: 7,296,121
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`p. 50.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “states as-
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`sociated with selected ones of the cache memories” as being broad enough to en-
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`compass “any modes or conditions of selected ones of the cache memories.” See
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`Ex. 1014, ¶¶ 30-32.
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`6. “transmit the probes only to selected ones of the pro-
`cessing nodes” (claims 1 and 16)
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`Independent claims 1 and 16 recite transmitting “probes only to selected
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`ones of the processing nodes.” Applying the broadest reasonable interpretation,
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`this phrase should be construed broadly enough to cover transmission of each
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`probe to one or more selected processing nodes. In particular, claims 1 and 16 re-
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`cite that multiple “probes” are transmitted to “selected ones of the processing
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`nodes.” Because the claims describe the transmission of multiple “probes” instead
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`of a single “probe,” the claim language does not require that a single probe be
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`transmitted to more than one selected processing node, despite the claims’ use of
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`the plural form of “selected ones.” See Ex. 1014, ¶ 34. Rather, each probe could
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`be transmitted to a single selected processing node and still satisfy the require-
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`ments of claims 1 and 16. See id. For example, if probe A is transmitted to a se-
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`lected processing node X and probe B is transmitted to a selected processing node
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`12
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`U.S. Patent No.: 7,296,121
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`Y, probes (i.e., probes A and B) are transmitted to selected ones of the processing
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`nodes (i.e., processing nodes X and Y) despite the distribution of the nodes among
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`plural processing nodes. See id.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “transmit
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`the probes only to selected ones of the processing nodes” as broad enough to en-
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`compass “transmit each of the multiple probes only to one or more selected pro-
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`cessing nodes.” See Ex. 1014, ¶¶ 33-34.
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`7. “cache coherence controller” (claim 3)
`The ‘121 Patent defines the term “cache coherence controller” as any mech-
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`anism or apparatus that can be used to provide communication between multiple
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`processing nodes while maintaining cache coherence. See Ex. 1001, 7:2-6. The
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`‘121 Patent uses the term cache coherence controller consistent with this defini-
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`tion. For instance, the ‘121 Patent specification points out with regard to Fig. 2,
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`which shows a diagram of a multiple processor cluster that includes a cache coher-
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`ence controller, the ‘121 Patent illustrates the cache coherence controller may be
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`connected to processors within the cluster and with other clusters of processors. In
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`such a configuration, “cache coherence controller 230 communicates with both
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`processors 202a-d as well as remote clusters using a point-to-point protocol.” Ex.
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`1001, 7:10-12.
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`13
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`U.S. Patent No.: 7,296,121
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`Though FIGS. 4-12 focus on such inter-cluster communications, the ‘121
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`Patent also describes the use of the cache coherence controller for filtering intra-
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`cluster communications. See Ex. 1001, 25:24-57, 26:36-57; see also Ex. 1014, ¶
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`37. Specifically, the ‘121 Patent specification describes that “the filtering of
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`probes within a cluster, i.e., local probe filtering, may be implemented in systems
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`having multiple clusters as well as systems having a single cluster of processors.”
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`Ex. 1001, 26:36-39. Thus, a cache coherence controller may filter probes between
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`clusters and/or between processors within a cluster. See Ex. 1014, ¶ 37.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “cache co-
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`herence controller” as broad enough to encompass “any mechanism or apparatus
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`that can be used to provide communications between multiple processing nodes
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`while maintaining cache coherence.” See Ex. 1014, ¶¶ 35-37.
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`8. “cache coherence directory” (claim 3)
`The ‘121 Patent does not provide an explicit definition of the term “cache
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`coherence directory,” but does describe that, “according to some embodiments, a
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`cache coherence directory is a mechanism that facilitates the tracking by that cache
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`coherence controller of where particular memory lines within its cluster’s memory
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`are being cached in remote clusters.” Ex. 1001, 18:43-47. The ‘121 Patent uses
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`the term cache coherence directory consistent with this description. See Ex. 1014,
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`14
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`

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`U.S. Patent No.: 7,296,121
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`¶ 38. For example, the ‘121 Patent describes that the cache coherence directory
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`“indicates the existence and location of any remotely cached copies of the
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`memory.” Ex. 1001, 21:7-8.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “cache co-
`
`herence directory” as broad enough to encompass “a mechanism that facilitates the
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`tracking of where particular memory lines are being cached.” See Ex. 1014, ¶ 38.
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`9. “the probes” (claim 8)
`Claim 8 recites that “each of the processing nodes is operable to transmit the
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`probes only to the probe filtering unit” (emphasis added). The term “the probes”
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`employs the definite article “the,” which particularizes the subject “probes” by re-
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`ferring to an antecedent for that term. See NTP, Inc. v. Research in Motion, Ltd.,
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`418 F. 3d 1282, 1306 (Fed. Cir. 2005). The only antecedent for “probes” is recit-
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`ed in independent claim 1, from which claim 8 depends. Claim 1 recites “a probe
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`filtering unit which is operable to receive probes corresponding to memory lines
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`from the processing nodes and to transmit the probes only to selected ones of the
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`processing nodes.4” Ex. 1001, 31:1-5. Thus, the term “the probes” recited in claim
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`4 In interpreting this feature of claim 1, it is worth noting that dependent claim 14
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`of the ‘121 Patent clarifies that “the probes” transmitted to selected ones of the
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`15
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`8 explicitly refers to probes received by the probe filtering unit from the processing
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`U.S. Patent No.: 7,296,121
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`nodes.
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`Notably, this means that claim 8 does not require the processing nodes to be
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`operable to send all probes only to the probe filtering unit. Rather, claim 8 simply
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`requires that those probes received by the probe filtering unit from the processing
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`nodes be transmitted only to the probe filtering unit (as opposed to, for example,
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`the processing nodes broadcasting those probes received by the probe filtering unit
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`to other processing nodes).
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`IV. SUMMARY OF THE ‘121 PATENT
`A. Brief Technology Overview
`A shared-memory multiprocessor is a computer system in which multiple
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`processors share memory. See Ex. 1014, ¶ 12. Memory (and I/O devices) are
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`shared by each of the processors via a local interconnection network. Ex. 1013, p.
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`1. “Each processor has access to its own memory and all the memory of all the
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`other processors.” Id. “Memory becomes a common resource which must be
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`shared between execution threads running simultaneously (really simultaneously,
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`not time shared) on different processors in the multiprocessor system.” Id.
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`processing nodes by the probe filtering unit need not be exact copies of the probes
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`received by the probe filtering unit but rather may instead be modified versions of
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`the probes received by the probe filtering unit.
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`16
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`U.S. Patent No.: 7,296,121
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`One way to increase the speed of a multiprocessor is to associate a cache
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`memory with each processor. See Ex. 1014, ¶ 13. Cache memories are signifi-
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`cantly faster than standard main memory (e.g., RAM and ROM). However, be-
`
`cause cache memories have significantly smaller capacity than main memory, each
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`processor can use a cache memory to store a copy of only a portion of the data
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`stored in main memory (e.g., the portion most recently or most commonly accessed
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`by the processor). See id. Moreover, because threads are executed simultaneously
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`across the processors within the multiprocessor share memory, more than one pro-
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`cessor may store a copy of a particular memory location in its cache. See id.
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`Each of these simultaneously executed threads has the ability to cause its
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`processor to both load the data stored in its cache and store updates to the data
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`back into its cache. See id. at ¶ 14. As such, inconsistencies may arise between
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`copies of data that are stored in different of the cache memories. See id. For ex-
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`ample, in the case where multiple processors store a copy of a memory location in
`
`their respective caches, one of the processors may update the copy stored in its
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`cache, causing the copy within the cache of that processor to become inconsistent
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`or incoherent with respect to non-updated copies of the data that remain in the
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`cache of other of the processors. See