Michael C. Brogioli, Ph.D.
`
`Contact
`
`Information
`
`Michael C. Brogioli, Ph.D.
`Polymathic Consulting
`100 Congress Avenue, Suite 2000
`Austin, TX 78701 USA
`
`Office: (512) 370-4936
`Cell (preferred): (713) 732-0217
`Fax: (512) 469-6306
`E-mail: michael@polymathicconsulting.com
`
`Education
`
`Rice University, Houston, Texas USA
`
`Ph.D., Electrical and Computer Engineering, 2007
`
`• Dissertation Topic: “Reconfigurable Heterogeneous DSP/FPGA Based Embedded Architec-
`tures for Numerically Intensive Embedded Computing Workloads.”
`• Advising Committee: Dr. Joseph R. Cavallaro, Dr. Keith D. Cooper, Dr. Scott Rixner
`
`Rice University, Houston, Texas USA
`
`M.S., Electrical and Computer Engineering, 2003
`
`• Dissertation Topic: “Dynamically Reconfigurable Data Caches in Low Power Computing.”
`• Advising Committee: Dr. Keith D. Cooper, Dr. Scott Rixner, Dr. Robert Jump
`
`Rensselaer Polytechnic Institute, Troy, New York USA
`
`B.S., Electrical Engineering, Cum Laude - 1999
`
`• Advisor: Dr. William Pearlman
`
`Professional
`
`Experience
`
`Polymathic Consulting, Austin, TX USA
`October 2011-Present
`Managing Director
`Founder and managing director at Polymathic Consulting, servicing clients ranging from early stage
`technology start up endeavors to Fortune 100 and beyond. Clients turn to Polymathic for expansive,
`proven engineering, research and development, intellectual property and technical leadership to
`effectively advance their real world business needs.
`
`Scout Island Ventures, Austin, TX USA
`October 2011 - Present
`Managing Director
`Scout Island Ventures holds diversified investments in various stage startup companies, including but
`not limited to enterprises engaging in software, SaaS, PaaS, embedded computing, medical, mobile,
`and education.
`
`Rice University, Houston, TX USA
`July 2009 - Present
`Adjunct Professor, Electrical and Computer Engineering
`Professor of Ph.D. candidate level courses in wireless telecommunications, embedded computing soft-
`ware, embedded computing hardware, and software/hardware optimization in modern computing
`systems utilizing modern high level programming languages. Advisor of senior and graduate stu-
`dent based projects revolving around multi-core heterogeneous systems as they pertain to wireless
`telecommunications, medical and video.
`
`Osmek, Austin, TX USA
`March 2012 - February 2014
`Interim CTO, Advisory Board Member
`Interim CTO and board member advising in the areas of large scale cloud based content management
`software systems. Providing innovative media content management for heterogeneous web enabled
`devices with geolocational services.
`
`Freescale Semiconductor, Austin, TX USA
`
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`PATENT OWNER EX. 2009 - PAGE 1
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`November 2009 - October 2011
`Chief Architect, Senior Member Technicial Staff
`Technical architect of Freescale’s DSP compilers and related technology. Responsible for manage-
`ment of technology, engineering roadmaps, design lead on compiler infrastructure and optimizations
`(high level and low level), next generation ABI definitions and next generation architecture solutions.
`Technical lead on multi-year engagement with processor architects in design of next generation DSP
`cores. Developed software infrastructure for migrating OEM competitor software stacks to Freescale
`solutions, tools generation, software packages, migration strategies and white papers. Technical
`lead on Tier-1 OEM customer relationships, evaluations of 3rd party technologies for potential part-
`nerships and acquisitions, lead various university research collaborations on behalf of Freescale.
`Development and deployment of internal software engineering policies and practices.
`
`Freescale Semiconductor, Austin, TX USA
`Senior Compiler Engineer V
`2008 - 2009
`High Performance Compiler Design, Processor Architecture
`Team leader on compiler engineering effort to provide intuitive, interactive end user experience for
`DSP compiler tool suite. Designed a framework to guide users in achieving highly optimized compiled
`VLIW code. Assembly listing reports for optimization failure advice, porting advice when migrating
`from competitor architectures, advice on code modifications for optimization enablement. Lead
`designer, engineering effort director, project planning and scoping, release schedule, and drafting
`of specification. Development of various compiler optimizations for VLIW processing as well as
`software emulation layers for running competitor software solutions on Freescale silicon.
`
`Advising of next-gen DSP core architecture team in creating a highly orthogonal, compiler targetable
`multi-clustered VLIW based digital signal processor architecture. Work with future basestation
`architecture teams on designing next-gen basestation architecture for 4G LTE incorporating control
`and data plane processing with appropriate programming models.
`
`Method Seven, Boston, MA USA
`Technical Co-Founder
`June 2006 - August 2007
`High Performance Software and Hardware Systems Architecture
`Founded Method Seven, a financial engineering company applying biologically inspired machine
`learning to financial market analysis. Principal software systems architect and hardware systems
`architect for both research and deployment platforms. Lead research and development of platform
`for scans and overlays covering the NASDAQ, NYSE, and AMEX markets using proprietary tech-
`nologies.
`
`Texas Instruments, Stafford, Texas USA
`Advanced Architecture and Chip Technologies
`Jun, 2005 - Sept 2005
`DSP Architecture (Intern)
`System modelling and architectural exploration of DavinciTMsystem-on-chip (SOC) architecture
`designed for embedded video processing. SystemC based simulation models of on–chip crossbars,
`bus arbitration and bridge technology, as well as on–chip and off–chip memory controllers within
`application specific heterogeneous SOC architectures.
`
`Fulbright and Jaworski LLP, Houston, Texas USA
`Intellectual Properties
`January 2005 - August 2007
`Intellectual Property Consultant
`Intellectual property consultant and technology advisor on litigation and prosecution work including,
`but not limited to: CDMA2000 3G wireless standards, wireless communications systems, embedded
`computing, and large scale modular software systems. Reverse engineering of source code varying
`from VHDL to high level object oriented applications, as well at patent prosecution and litigation
`work.
`
`Intel Corporation, Santa Clara, California USA
`
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`PATENT OWNER EX. 2009 - PAGE 2
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`Microprocessor Research Labs
`May, 2000 - Aug, 2000
`Compiler Engineering (Intern)
`Implemented speculative multi–threading support in Intel’s IA–64 compiler. Developed new program
`analysis and back end code generation phases to support speculatively launching threads at runtime.
`Analyzed the performance potentials of SPEC95 benchmarks with respect to speculatively multi–
`threaded execution.
`
`Vicarious Visions, Albany, New York USA
`April, 1999 - Aug, 1999
`Lead Software Engineer (Intern)
`Principal engineer on Activision’s “AMF Extreme Bowling” for Nintendo’s Color Gameboy gaming
`console. Developed PC based audio and graphics development tools suite for use with Color Game-
`boy game production. Coded innovative, highly optimized assembly routines for real time speech
`and full motion video on the console’s limited Zilog Z80 processor resources.
`
`May, 1998 - Aug, 1998
`Stratus Computer, Marlboro, Massachusetts USA
`June, 1997 - Dec, 1997
`Hardware Engineering (Intern)
`Debugged locked step CPU operation and memory management issues in Stratus’ fault tolerant
`UNIX release 3.4. Qualified Hewlett Packard PA–8000 series CPU modules under Stratus’ propri-
`etary OS release, VOS 14.0, during alpha and beta test phases. Wrote C code and UNIX shell scripts
`for recreating documented system failures, and to automate remote kernel updates and OS installs
`as well as data logging.
`
`Rensselaer Polytechnic Institute, Troy, New York USA
`1997 - 1998
`Digital Microelectronics Design (Undergraduate Instructor)
`Undergraduate instructor of undergraduate courses in digital microelectronics and circuit design.
`Instructed weekly lessons, computer design labs, graded exams and problem sets.
`
`Rensselaer Polytechnic Institute, Troy, New York USA
`1995 - 1997
`Rensselaer Electric Motorsports (Undergraduate Hardware and Software Engineer)
`Hardware and software design of embedded operating system and hardware platform for electrical
`vehicle prototypes, running on 16-bit Motorola 68K dual processor platform. Power enginering test
`platform for dynamometers. Project was sponsored by General Motors and Honda.
`
`Books and
`
`Contributed
`
`Chapters
`
`Brogioli, M. C., On Cloud Computing, Data Security, and Medical Devices, Software Development
`for Networking Applications – Expert Guides Series, pp. TBD, Elsevier Publishing, Atlanta, GA,
`2016 (print).
`
`Brogioli, M. C., A Brief History of Wireless Telecommunications Networks, Software Development
`for Networking Applications – Expert Guides Series, pp. TBD, Elsevier Publishing, Atlanta, GA,
`2016 (print).
`
`Brogioli, M. C., Networking Protocols, OSI 7 Layer Model In Networking and Communications
`Protocols for Data, Voice, and Beyond., Software Development for Networking Applications – Expert
`Guides Series, pp. TBD, Elsevier Publishing, Atlanta, GA, 2016 (print).
`
`Brogioli, M. C., Case Study: Mobile Computing, Cloud Computing, and Data Security, Software
`Development for Networking Applications – Expert Guides Series, pp. TBD, Elsevier Publishing,
`Atlanta, GA, 2016 (print).
`
`Wu, Michael and Sun, Yang and Wang, Guohui and Brogioli, M.C. and Cavallaro, J. R., Implemen-
`tation of a High Throughput 3GPP Turbo Decoder on GPU Architectures, Software Development for
`Networking Applications – Expert Guides Series, pp. TBD, Elsevier Publishing, Atlanta, GA, 2016
`(print).
`
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`PATENT OWNER EX. 2009 - PAGE 3
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`Brogioli, M. C., On The C++ Programming Language for Embedded Software, Systems, and Plat-
`forms, Software Engineering for Embedded Systems – Expert Guides Series, Elsevier Publishing,
`Atlanta, GA, 2013.
`
`Brogioli, M. C., Software Optimizations for Memory Performance in Embedded Systems, Software
`Engineering for Embedded Systems – Expert Guides Series, Elsevier Publishing, Atlanta, GA, 2013.
`
`Invited Co-Author, Signal Processing Systems Handbook, Second Edition, Springer Publishing Com-
`pany, 11 West 42nd Street, New York, NY, 2012.
`
`Brogioli, M. C., Software Programmable DSP Architectures, Expert Guide DSP for Embedded and
`Real-Time Systems, pp. 63-75, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C., The DSP Hardware / Software Continuum, Expert Guide DSP for Embedded and
`Real-Time Systems,, pp. 103-113, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C., DSP Optimization - Memory Optimization, Expert Guide DSP for Embedded and
`Real-Time Systems, pp. 217-241, Elsevier Publishing, Atlanta, GA, 2012.
`
`Brogioli, M. C. and Dew, Stephen, Optimizing DSP Software - High level Languages and Program-
`ming Models, Expert Guide DSP for Embedded and Real-Time Systems,, pp. 167-179, Elsevier
`Publishing, Atlanta, GA, 2012.
`
`Sun, Yang, Amiri, Kiarash, Brogioli, Michael, Wang, Guohui, and Cavallaro, Joseph R., DSP Hard-
`ware Accelerator Architectures for Communication Applications, Springer Publishing, New York,
`NY, Spring 2012.
`
`Invited Co-Author, Signal Processing Systems Handbook, First Edition, Springer Publishing Com-
`pany, 11 West 42nd Street, New York, NY, 2010.
`
`Publications
`
`Invited Paper, Arokia I, Brogioli, Michael, Jain, Nitjin and Garg, Umang, LTE Layer 1 Software
`Design on Heterogeneous Multicore DSP Platforms, IEEE 45th Asilomar Conference on Signals,
`Systems and Computers, Pacific Grove, CA, 2011.
`
`Kyriakopoulous, Konstantinos, Brogioli, Michael C., and Zhang, Ruihao, Improving Software Sys-
`tems Quality through Well Defined Development Methodologies, 2011 Test Methodology and Effi-
`ciency Symposium, Freescale Semiconductor, Austin, TX, USA, 2011.
`
`Brogioli, M.C., and Cavallaro, J.R., Compiler Driven Architecture Design Space Exploration for
`Embedded DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration,
`IEEE 43rd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2009.
`
`Brogioli, M.C., and Zhang, Ruihao, Compiler Feedback: Guiding Performance of Compiled C Code,
`Freescale Semiconductor White Paper, Austin, TX, 2009.
`
`Brogioli, M.C., and Cavallaro, J., RISD: A Retargetable Compiler Infrastructure for Scalable Multi-
`Clustered VLIW DSP Architectures, IEEE 5th Dallas Circuits and Systems Workshop, Dallas, TX,
`2007.
`
`Brogioli, M.C., Radosavljevic, P., and Cavallaro, J., A General Hardware/Software Codesign Method-
`ology for Embedded Signal Processing and Multimedia Workloads, IEEE 40th Asilomar Conference
`on Signals, Systems, and Computers, Pacific Grove, CA, 2006.
`
`Brogioli, M.C., Radosavljevic, P., and Cavallaro, J., Hardware/Software Co-design Methodology for
`
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`PATENT OWNER EX. 2009 - PAGE 4
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`DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile
`Receivers, 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto
`Rico, 2006.
`
`Brogioli, M.C., Willmann, P.D., and Rixner, S., Parallelization Strategies for Network Interface
`Firmware, IEEE/ACM 4th Annual Workshop on Optimizations for DSP and Embedded Systems
`(In Conjunction with IEEE/ACM International Symposium on Code Generation and Optimization),
`Manhattan, NY, 2006.
`
`Brogioli, M.C., Gadhiok, M., and Cavallaro, J., Design and Analysis of Heterogeneous DSP/FPGA
`Based Architectures for 3GPP Wireless Systems, IEEE Real-Time and Embedded Technology and
`Applications Symposium Work-in-Progress Sessions, San Jose, CA, 2006.
`
`Brogioli, M.C., and Cavallaro, J., Modelling Heterogeneous DSP-FPGA Based System Partitioning
`with Extensions to the Spinach Simulation Environment, IEEE 39th Asilomar Conference on Signals,
`Systems, and Computers, Pacific Grove, CA, 2005.
`
`Brogioli, M.C., Pai, V.S., Willmann, P.D., Spinach: A Liberty–Based Simulator For Programmable
`Network Interface Architectures, ACM SIGPLAN/SIGBED Conference on Languages Compilers and
`Tools for Embedded Systems, San Diego, CA, 2004.
`
`Brogioli, M.C., Dynamically Reconfigurable Data Caches in Low Power Computing, Masters Thesis,
`Rice University, Houston Texas, 2002.
`
`Patents
`
`Michael C. Brogioli, Ph.D., Cesar Taylor M.D., and Howard Roberts, Location Agnostic Plat-
`form for Medical Condition Monitoring and Prediction and Method of Use Thereof, Patent No:
`147145.010100/US, 2014.
`
`Cesar Taylor M.D., and Michael C. Brogioli Ph.D., and Howard Roberts, System for Holistic Pain
`Monitoring and Prediction and Method of User Thereof, Patent No: 147145.010200/US, 2014.
`
`Cesar Taylor M.D., and Michael C. Brogioli Ph.D., and Howard Roberts, System for Prevention of
`Narcotic Diversion and Method of Use Thereof, Patent No: 147145.010300/US, 2014.
`
`Howard Roberts, Cesar Taylor M.D., and Michael C. Brogioli Ph.D., Magnetometer Breathing Sensor
`and Method of User Thereof, Patent No: 147145.010400/US, 2014.
`
`Corporate
`
`Board
`
`Membership
`
`Southwest Angel Network for Social Impact, TX USA
`October 2015 - Present
`Board of Directors, Co-Founder
`The Southwest Angel Network for Social Impact ( SWAN Impact ) is a community of like-minded
`investors who enjoy working together to Make the world a better place, one company at a time. We
`believe that we can have the most significant impact by funding for-profit start-up companies who
`are building sustainable businesses.
`
`NewCrew, TX USA
`April 2015 - Present
`Advisory Board
`Board member advising in the areas of mobile computing, social computing, and geofencing tech-
`nologies. Business development, marketing, and fund raising.
`
`Joule Enableware, TX USA
`April 2015 - Present
`Advisory Board, Co-Founder
`Board member advising in the areas of Internet of Things technologies, specifically related to product
`developer solutions, programming languages and platforms. Business development, marketing, and
`
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`PATENT OWNER EX. 2009 - PAGE 5
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`fund raising.
`
`AngelSpan, TX USA
`April 2015 - Present
`Advisory Board
`Board member advising in the areas of professional investor relations to startups, resource allocation,
`and a platform for increased efficiency and valuation of early stage companies and venture capital
`portfolios.
`
`Capital Factory, TX USA
`May 2014 - Present
`Mentor
`Mentor, advisor and investor in one of the most successful start-up accelearators in the United
`States.
`
`Student Loan Genius, TX USA
`June 2013 - Present
`Advisory Board
`Board member advising in the areas of financial transactions systems and enterprise software, as
`they pertain to solving the student loan debt crisis for early stage science, technology, engineering
`and medicine (STEM) employees. Technology, recruiting, fund raising.
`
`HealthBits, TX USA
`March 2013 - October 2014
`Board Member, Co-Inventor
`Board member advising in the areas of large scale enterprise software systems, real-time computing
`and medical sensing devices across complex event processing systems.
`
`Incubation Station, TX USA
`January 2013 - April 2014
`Mentor
`Incubation Station is an accelerator that brings together a consortium of Austins notable en-
`trepreneurs, investors and advisors for the purpose of mentoring high-potential, market-validated
`consumer product companies to more effectively manufacture, distribute, market and grow their
`products and services.
`
`Osmek, TX USA
`March 2012 - February 2014
`Interim CTO, Advisory Board
`Interim CTO and board member advising in the areas of large scale cloud based content management
`software systems. Providing innovative media content management for heterogeneous web enabled
`devices with geolocational services, primarily using PHP and Python programming languages.
`
`Rice University, Houston, Texas USA
`2005 - 2009
`DSP Compiler Design
`Developed RISD, a retargetable compiler infrastructure for clustered VLIW DSP architectures. By
`taking pre-existing code schedules and binaries for existing DSP applications, RISD takes a flexible
`machine definition for which the code should be recompiled. Users can specify the number of VLIW
`clusters, functional units per VLIW cluster, functional unit mix per VLIW cluster, register file
`sizes, cluster interconnect topology (point-to-point versus 2d mesh network), multi-cluster scheduling
`algorithms, and inter-cluster cross-register file bandwidth and latencies.
`
`Compiler framework was used to perform compiler driven design space exploration of massively
`multi-clustered VLIW based architectures versus FPGA and ASIP implementations of software
`kernels. RISD was used in studies comparing tradeoffs in computational throughput versus gates
`required to implement programmable DSP cores containing many register files and VLIW compute
`clusters, versus FPGA efficiency when including routing overhead for large scale problems.
`
`Rice University, Houston, Texas USA
`DSP/FPGA Based System-On-Chip Architectural Simulator Design
`
`2004 - 2009
`
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`Academic
`
`Experience
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`PATENT OWNER EX. 2009 - PAGE 6
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`

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`Developed Spinach DSP-FPGA, a modular and composable simulator design infrastructure for pro-
`grammable and reconfigurable embedded SOC architectures. Designed and developed modular and
`composable software modules to bit-true, cycle accurately simulate Texas Instruments C62x and
`C64x DSPs and MIPS style processors. Additionally designed and developed support for SRAM
`and DRAM style memories, heterogeneous memory systems, heterogeneous clock domains, as well
`as runtime reconfigurable Xilinx Virtex II based FPGA computing elements, cache and memory
`controllers, bus arbiters, and on chip interconnect fabric.
`
`System was validated against compiled code DSP firmware from Texas Instruments’ Code Composer
`Studio running on the simulator versus actual hardware benchmarks. Simulation platform was used
`to investigate highly heterogeneous multi-processor DSP based SOC architectures containing one or
`more Xilinx style FPGA based hardware coprocessors. Studies in 3.5G wireless telecommunications
`as well as H.26x video processing were performed to gain insight into overall system bottlenecks,
`hardware and software partitioning strategies, and tradeoffs of overall system design.
`
`Rice University, Houston, Texas USA
`2002 - 2004
`Programmable Network Interface Architecture Simulator Design
`Developed Spinach, a simulator design toolset for modelling programmable network interface archi-
`tectures. Spinach models system components common to all programmable environments (ALUs,
`control and data paths, register files, instruction processing), as well as components specific to em-
`bedded computing (software controlled SRAM scratchpad memory, hardware assists for DMA and
`medium access control). Spinach is a simulator design infrastructure, rather than a simulator per se.
`As such, the same underlying C code framework is used to model a uniprocessor Gigabit network
`interface, a multi-processor Gigabit network interface, or a 10 Gigabit multi-processor network inter-
`face with highly heterogeneous memory system. Only a small number of lines of high level scripting
`language code is required to describe each of the various systems.
`
`Spinach was validated by modeling the Tigon-2 programmable Ethernet controller by Alteon Web-
`systems, running actual compiled code Ethernet processing firmware and by comparing the reported
`results to actual hardware benchmarks. Spinach was also used to obtain new insights into the per-
`formance of Gigabit and 10 Gigabit network interfaces both in terms of hardware architecture and
`firmware parallelization strategies. Public Website: https://sourceforge.net/projects/spinach/
`
`Rice University, Houston, Texas USA
`Jan, 2000 - Sept, 2000
`Software Engineering and Consulting
`Implemented instruction selection and register allocation optimizations in UHFFT, an adaptive and
`portable software library for the Fast Fourier Transform. Performed in depth analysis of register
`pressure, compiler generated spill code, memory hierarchy utilization, and instruction selection for
`non–trivially sized FFT matrices running on commercially available hardware platforms. Utilized
`reverse Cuthill–McKee technique to achieve near optimal computation orderings and minimize live
`data set sizes, as well as optimize register allocation and instruction selection phases of compilation.
`
`Appointed
`
`Conference
`
`Committees and
`
`Organizations
`
`IEEE and ACM Design Automation Conference, USA
`Fall 2014 - Present
`Program Committee, Embedded Systems Software
`Program Committee member responsible for the review, critique, and acceptance of academia and
`industry based publications in the areas of embedded systems, embedded software, and embedded
`system design. Design Automation Conference is an annual technical conference and trade show
`specializing in electronic systems.
`
`IEEE and ACM Design Automation Conference, USA
`Spring 2011 - Present
`Program Committee, Designer and User Track
`Program Committee member responsible for the review, critique, and acceptance of academia and
`industry based publications in the areas of automated system design, both of hardware, software,
`and system analysis. Design Automation Conference is an annual technical conference and trade
`
`VII
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`PATENT OWNER EX. 2009 - PAGE 7
`
`

`
`show specializing in electronic systems.
`
`Rice Alliance for Technology and Entrepreneurship Austin, Texas, USA
`2009 - Present
`Executive Committee Member
`The Rice Alliance for Technology and Entrepreneurship strives to improve the entrepreneurial ecosys-
`tem of Central Texas by: helping entrepreneurs successfully found, fund, grow and exit new compa-
`nies, helping investors suc cessfully identify and engage with promising new ventures, and showcasing
`emerging technologies and business models to further educate and engage the community.
`
`Central Texas Angel Network, Austin, Texas, USA
`November 2013 - Present
`Angel Investor
`Active investor and board member in early stage technology companies within the Central Texas
`area. CTANs mission is to provide quality early-stage investment opportunities for accredited angel
`investors and to provide funding, advice, and networking for bold, early stage entrepreneurs with
`game-changing ideas.
`
`OwlSpark, Houston, Texas, USA
`June 2014 - May 2015
`Mentor
`Mentor and advisor to university based early stage technology companies.
`
`Expert Witness,
`Consultant
`
`Undisclosed Technology Company
`Merger and Acquisition, Asset Monetization, California, USA
`2015 - 2016
`Venture Capital Fund Raising, Portfolio Valuation
`Analyzed patent portfolio of target companies, valued assets, assessed total addressable market size,
`and raised appropriate venture capital.
`
`DTS, Inc., et al. v. Nero AG, et al.
`Glaser Weil Fink Jacobs Howard Avchen & Shapiro, Los Angeles CA, USA
`Expert Witness in Audio and Video Software, Intellectual Property
`Expert witness in the area of software solutions for audio and video codecs.
`
`2015 - 2016
`
`Advanced Silicon Technologies
`Mintz Levin Cohn Ferris Glovsky and Popeo PC, Boston, MA, USA
`2015 - Present
`Expert Witness in Microprocessor Architecture, Intellectual Property
`Expert witness in the area of computer architecture and microprocessor technologies.
`
`Certain Audio Processing Hardware and Software and Products Containing the Same,
`ITC Inv. No. 337-TA-949
`Lenovo (United States), Inc.
`Toshiba Corp
`Akin Gump Strauss Hauer & Feld LLP, Philadelphia, PA, USA
`2015 - 2016
`Expert Witness in Digital Signal Processing, Intellectual Property
`Expert witness in hardware/software based digital signal processing systems tailored for audio pro-
`cessing and noise cancellation technology.
`
`Intel Corporation v. Future Link Systems
`Irell & Manella LLP, Los Angeles, CA USA
`2015 - Present
`Expert Witness in Computer Architecture and System Interconnect Technology
`Expert witness in the areas of computer architecutre, system-on-chip technology, and computer bus
`architecutres.
`
`Advanced Touchscreen and Gesture Technologies, LLC v. Samsung Electronics, Amer-
`ica, Inc., et al.
`Robins Kaplan LLP, Intellectual Property, Minnesota, USA
`
`VIII
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`PATENT OWNER EX. 2009 - PAGE 8
`
`

`
`2015 - Present
`Expert Witness in Software Systems for Mobile Devices and User Interfaces
`Expert witness in the analysis and reverse engineering of software systems pertaining to mobile
`devices, and human computer interfaces.
`
`Intellectual Ventures v. Ericsson et al.
`Dechert LLP, Los Angeles, CA, USA
`Expert Witness in 3GPP standards and LTE Technologies, Intellectual Property 2014 - Present
`Expert witness in 3GPP standards as they pertain to LTE cellular communications networks, in
`addition to system hardware and software design.
`
`Papst Licensing GMBH & Co. KG.
`DiNovo & Price Ellwanger Hardy, Austin, TX USA
`2014-2015
`Consultant in FPGA Technologies, Intellectual Property
`Consultant in FPGA computing platforms and design flow processes, prior art, and infringement
`analysis.
`
`Locata LBS v. Paypal Inc., et al.
`Glaser Weil Fink Jacobs Howard Avchen & Shapiro, Los Angeles, CA, USA
`2014 - 2015
`Expert Witness in Geofencing Systems, Intellectual Property
`Expert witness in geofencing technology, geolocational technology, and systems architecture as it
`pertains to mobile cellular telecommunications and enterprise software systems.
`
`Cell and Network Selection LLC v. AT&T Mobility LLC and MetroPCS Communica-
`tions Inc.
`Pillsbury, Winthrop Shaw & Pittman, San Diego, CA, USA
`2014 - 2015
`Expert Witness in 3G/4G Cellular Handset Technology, Intellectual Property
`Expert witness in technology pertaining to 3G, 3.5G, 3.75G and 4G wireless handset technology.
`Expert report generation, deposition, and tentative trial testimony.
`
`CA Inc. D/B/A CA Technologies v. AppDynamics, Inc.
`Bracewell & Giuliani, Houston, TX, USA
`Holland & Knight, Boston MA USA
`Expert Witness in Computer Application Performance Monitoring, Intellectual Property
`2015
`Expert witness in technology pertaining to dynamic runtime profiling of distributed software appli-
`cations, specifically around Java and C technologies. Expert report generation, source code review,
`deposition testimony, pending trial testimony.
`
`2014 -
`
`M Seven System Limited v. Leap Wireless International, Inc., et al.
`Glaser Weil Fink Jacobs Howard Avchen & Shapiro, Los Angeles, CA, USA
`2014
`Expert Witness in 3G/4G Feature Phone Software Systems, Intellectual Property
`Expert witness in the area of mobile telecommunications technology, particularly cellular telephone
`hardware and software design.
`
`Lunareye v. Gordon Howard Associates, Inc.
`Conley Rose, P.C., Austin, Austin, TX, USA
`2014 -
`Expert Witness in Cellular Communications Software and Hardware Systems
`Technical expert in the area of mobile telecommunications technology, particularly cellular telephone
`hardware and software design.
`
`Certain Wireless Devices With 3G and/or 4G Capabilities and Components Thereof,
`ITC Inv. No. 337-TA-868
`Interdigital, Inc. Wilson, Sonsini, Goodrich & Rosati LLP, Austin, TX, USA
`Expert Witness in 3G/4G Software and Hardware systems, Intellectual Property
`
`2013 - 2015
`
`IX
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`PATENT OWNER EX. 2009 - PAGE 9
`
`

`
`Expert witness in software systems and hardware systems, as they pertain to 3G/4G cellular com-
`munications and standards.
`
`Investment Technology Group v. United States Internal Revenue Services
`Investment Technology Group, New York, NY USA
`2013
`Expert Witness in Financial Services Technology
`Expert witness in the area of high performance software systems targeting financial market services.
`
`Carrier Corporation v. Goodman Manufacturing, et al.
`Baker Botts LLP, Houston, TX USA
`2013 - 2014
`Expert Witness in Software and Hardware Systems, Intellectual Property
`Expert witness in the area of microprocessor based, serial distributed communications systems.
`
`Gametek LLC v. Facebook Inc. et al.
`Collins, Edmonds, Porgorzelski, Schlather & Tower PLLC, Houston, TX USA
`2013
`Expert Witness in Internet Based Gaming Technologies, Intellectual Property
`Expert witness in internet based client-server software systems for mobile and web browser based
`gaming technology.
`
`Ultimate Pointer LLC v. Nintendo Co. LTD et al.
`Conley Rose P.C., Houston, TX USA
`2013 - 2015
`Expert Witness in Console Based Video Game Technology, Intellectual Property
`Expert witness in hardware and software systems for console based video game technology.
`
`Alliantgroup, L.P. v. Tax Point Advisors
`Jeffrey Feingold and Tax Point Advisors, Houston, TX USA
`Expert Witness in Internet Technology
`Expert witness in IP based internet technology, packet spoofing and information systems.
`
`Kerry T. Thibodeaux, M.D. v. American Lifecare Inc.
`Cox, Cox Filo, Camel & Wilson, Lake Charles, LA USA
`Expert Witness in Medical Software Systems
`Expert witness in medical billing and expense recording enterprise software systems.
`
`Opelousas General Hospital Authority et al v. Fairpay Solutions Inc
`Cox, Cox Filo, Camel & Wilson, Lake Charles, LA USA
`Expert Witness in Medical Software Systems
`Expert witness in medical billing and expense recording enterprise software systems.
`
`2013
`
`2013
`
`2013
`
`Wi-LAN USA, Inc. and Wi-LAN, Inc. v. Alcatel-Lucent USA Inc.
`Vinson Elkins LLP, Dallas, TX USA
`2012-13
`Expert Witness in 3GPP LTE Technology, Intellectual Property
`Reverse engineering, analysis and education of counsel in the 3GPP LTE specification, and related
`software and hardware systems.
`
`Wi-LAN USA, Inc. and Wi-LAN, Inc. v. Ericsson Inc., and Telefonaktiebolaget LM
`Ericsson
`Vinson Elkins LLP, Dallas, TX USA
`2012-13
`Expert Witness in 3GPP LTE Technology, Intellectual Property
`Reverse engineering, analysis and education of counsel in the 3GPP LTE specification, and related
`software and hardware systems.
`
`E-Contact Technologies, LLC v. Dell Inc., et al.
`Baker Botts LLP, Houston, TX USA
`
`X
`
`PATENT OWNER EX. 2009 - PAGE 10
`
`

`
`2012
`Expert Witness in Android Operating System and Related Technology, Intellectual Property
`Reverse engineering and analysis of the Android operating system as it pertained to mobile and
`tablet computing devices. Source code reverse engineering, system architecture and related analysis.
`
`CheckFree Corporation and CashEdge, Inc. v. Metavante Corporation and Fidelity
`National Information Services, Inc.
`Paul, Weiss, Rifkind, Wharton & Garrison LLP, New York, NY USA
`2012
`Expert Witness in Banking and Billing Software Systems, Intellectual Property
`Software systems analysis and reverse engineering of large scale software based financial billing
`systems. Source code reverse engineering, claim chart generation, expert report generation and
`testimony.
`
`Realtime Data, LLC v. NASDAQ, Chase Bank, Goldman Sachs et al.
`Proskauer Rose LLP, New York, NY USA
`2012
`Expert Witness High Performance Software Systems, Intellectual Property
`Expert witness for joint defense counsel in the matter of large scale high frequency financial data
`aggregation platforms. Claim chart generation, expert report generation and deposition with testi-
`mony pending.
`
`Re