Trials@uspto.gov
`571-272-7822
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`Paper No. 8
`Filed: December 7, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`SAMSUNG ELECTRONICS COMPANY, LTD.,
`Patent Owner.
`____________
`
`Case IPR2015-01318
`Patent 8,252,675 B2
`____________
`
`
`
`Before JAMESON LEE, PATRICK R. SCANLON, and
`JUSTIN BUSCH, Administrative Patent Judges.
`
`LEE, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
`
`
`
`
`Paper No. 8
`Filed: December 7, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`SAMSUNG ELECTRONICS COMPANY, LTD.,
`Patent Owner.
`____________
`
`Case IPR2015-01318
`Patent 8,252,675 B2
`____________
`
`
`
`Before JAMESON LEE, PATRICK R. SCANLON, and
`JUSTIN BUSCH, Administrative Patent Judges.
`
`LEE, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2015-01318
`Patent 8,252,675 B2
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`A. Background
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`I. INTRODUCTION
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`On June 1, 2015, a Petition (Paper 1, “Pet.”) was filed to institute inter
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`partes review of claims 1–15 of U.S. Patent No. 8,252,675 B2 (Ex. 1001,
`
`“the ’675 patent”). Patent Owner filed a Preliminary Response (Paper 6,
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`“Prelim. Resp.”) on September 10, 2015.
`
`The standard for instituting an inter partes review is set forth in
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`35 U.S.C. § 314(a):
`
`THRESHOLD.—The Director may not authorize an inter
`partes review to be instituted unless the Director determines
`that the information presented in the petition filed under section
`311 and any response filed under section 313 shows that there
`is a reasonable likelihood that the petitioner would prevail with
`respect to at least 1 of the claims challenged in the petition.
`
`Having considered both the Petition and the Preliminary Response, we
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`are not persuaded, under 35 U.S.C. § 314(a), that Petitioner has
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`demonstrated a reasonable likelihood that it would prevail in showing the
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`unpatentability of any of claims 1–15 of the ’675 patent on any alleged
`
`ground. Accordingly, we do not institute an inter partes review of any
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`claim.
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`B. Related Matters
`
`The parties indicate that the ’675 patent is at issue in Samsung
`
`Electronics Co., Ltd. v. NVIDIA Corp., 3:14-cv-00757-REP (E.D. Va).
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`Papers 1, 4.
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`IPR2015-01318
`Patent 8,252,675 B2
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`C. The ’675 Patent
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`The ’675 patent relates to a method of forming an insulated-gate
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`transistor (independent claim 1) and a method of forming an integrated
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`circuit device (independent claim 6). The Background of the Invention
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`portion of the Specification does not articulate any problem with prior art
`
`methods, and the Summary portion of the Specification does not articulate
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`what objective or advantage is achieved by the invention, relative to prior art
`
`methods. The Background of the Invention portion states:
`
`MOS transistors are classified as n-MOS transistors or p-MOS
`transistors in accordance with the channel type which is
`induced beneath the gate electrode. The gate electrodes of the
`n-MOS transistor and the p-MOS transistor may be formed of
`different metals so that the n-MOS transistor and the p-MOS
`transistor have different threshold voltages.
`
`Ex. 1001, 1:24–30. None of the independent claims at issue requires
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`the formation of both an n-MOS and a p-MOS transistor, much less an
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`n-MOS and a p-MOS transistor that have respectively different
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`threshold voltages. Independent claims 1 and 6 each require a metal
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`gate electrode that itself comprises multiple metal layers, and claim 6
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`additionally specifies that the gate electrode is that of a PMOS
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`transistor.
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`
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`Aside from requiring multiple metal layers in the gate electrode,
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`each of claims 1 and 6 requires formation of a dummy gate electrode,
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`removal of the dummy gate electrode, and then the formation of a new
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`metal gate electrode by deposition of multiple additional metal layers.
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`Those additional metal layers are referred to in claim 1 as first metal
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`IPR2015-01318
`Patent 8,252,675 B2
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`layer and second metal layer, and in claim 6 as second metal gate
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`electrode layer and third metal gate electrode layer.
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`
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`Of all the challenged claims, claims 1 and 6 are the only independent
`
`claims. They are reproduced below:
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`1. A method of forming an insulated-gate transistor,
`comprising:
`
`forming a gate insulating layer on a substrate;
`forming a metal buffer gate electrode layer on the gate
`insulating layer;
`
`
`forming a dummy gate electrode layer on the buffer gate
`electrode layer, said dummy gate electrode layer and said
`buffer gate electrode layer comprising different materials;
`
`
`patterning the dummy gate electrode layer and the buffer gate
`electrode layer in sequence to define buffer gate electrode on
`the gate insulating layer and a dummy gate electrode on the
`buffer gate electrode;
`
`
`forming electrically insulating spacers on sidewalls of the
`dummy gate electrode and on sidewalls of the buffer gate
`electrode;
`
`
`covering the spacers and the dummy gate electrode with an
`electrically insulating mold layer;
`
`
`removing an upper portion of the mold layer to expose an upper
`surface of the dummy gate electrode;
`
`
`removing the dummy gate electrode from between the
`spacers by selectively etching back the dummy gate
`electrode using the mold layer and the spacers as an etching
`mask;
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`IPR2015-01318
`Patent 8,252,675 B2
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`depositing a first metal layer onto an upper surface of the
`mold layer and onto inner sidewalls of the spacers and onto
`an upper surface of the buffer gate electrode;
`
`
`filling a space between the inner sidewalls of the spacers by
`depositing a second metal layer onto a portion of the first
`metal layer extending between the inner sidewalls of the
`spacers to thereby define a metal gate electrode
`comprising a composite of the second metal layer, a
`portion of the first metal layer having a U-shaped cross-
`section and the buffer gate electrode.
`
`Id. at 10:59–11:26 (emphasis added).
`
`
`6. A method of forming an integrated circuit device,
`comprising:
`
`forming a gate insulating layer on a substrate;
`
`forming a first metal gate electrode layer on the gate insulating
`layer;
`
`forming a dummy gate electrode layer on the first metal gate
`electrode layer, said dummy gate electrode layer and said first
`metal gate electrode layer comprising different materials;
`
`patterning the dummy gate electrode layer and the first metal
`gate electrode layer in sequence to define a dummy gate
`electrode on the patterned first metal gate electrode layer;
`
`forming electrically insulating spacers on sidewalls of the
`dummy gate electrode and on sidewalls of the patterned first
`metal gate electrode layer;
`
`removing the dummy gate electrode from between the
`spacers by selectively etching back the dummy gate electrode
`using the spacers as an etching mask;
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`IPR2015-01318
`Patent 8,252,675 B2
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`depositing a second metal gate electrode layer onto inner
`sidewalls of the spacers and onto an upper surface of the
`patterned first metal gate electrode layer,
`depositing a third metal gate electrode layer onto the second
`metal gate electrode layer to thereby fill a space between the
`inner sidewalls of the spacers, said second and third metal gate
`electrode layers comprising different materials;
`
`planarizing the third metal gate electrode layer and the second
`metal gate electrode layer to thereby define a composite metal
`gate electrode of a PMOS transistor between the inner
`sidewalls of the spacers, said composite metal gate electrode
`comprising a portion of the third metal gate electrode layer,
`a portion of the second metal gate electrode layer having a
`U-shaped cross-section and the patterned first metal gate
`electrode layer.
`
`Id. at 11:39–12:11 (emphasis added).
`
`
`D. Evidence Relied Upon
`Petitioner relies on the following references:1
`
`
`Reference
`
`Date
`
`Exhibit
`
`Yamakawa U.S. Pub. No. 2009/0065809 A1 Mar. 12, 2009 Ex. 1003
`
`U.S. Patent No. 8,039,381 B2
`
`Ex. 1004
`
`Oct. 18, 2011
`(Filed June 3,
`2009)
`
`
`
`Yeh
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`
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`
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`1 Petitioner also relies on the Declaration of Jack Lee, Ph.D. (Ex. 1006).
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`IPR2015-01318
`Patent 8,252,675 B2
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`E. The Asserted Grounds
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`Petitioner asserts the following grounds of unpatentability:
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`Reference(s)
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`Basis
`
`Claims Challenged
`
`Yamakawa
`
`§ 102(b)
`
`1–8 and 10–15
`
`Yamakawa and Yeh
`
`§ 103(a)
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`9
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`II. ANALYSIS
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`A. Claim Construction
`
`In an inter partes review, claim terms in an unexpired patent are
`
`interpreted according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b);
`
`In re Cuozzo Speed Techs., LLC, 793 F.3d 1268, 1275–79 (Fed. Cir. 2015),
`
`reh’g en banc denied, 793 F.3d 1297 (Fed. Cir. 2015). Even under the rule
`
`of broadest reasonable interpretation, claim terms generally also are given
`
`their ordinary and customary meaning, as would be understood by one of
`
`ordinary skill in the art in the context of the entire disclosure. See In re
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`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`Claims are not interpreted in a vacuum but are a part of and read in
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`light of the specification. See Slimfold Mfg. Co., Inc. v. Kinkead Indus., Inc.,
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`810 F.2d 1113, 1116 (Fed. Cir. 1987). Although it is improper to read a
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`limitation from the specification into the claims, In re Van Geuns, 988 F.2d
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`1181, 1184 (Fed. Cir. 1993), the claims still must be read in view of the
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`specification of which they are a part. See Microsoft Corp. v. Multi-Tech
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`Sys., Inc., 357 F.3d 1340, 1347 (Fed. Cir. 2004).
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`IPR2015-01318
`Patent 8,252,675 B2
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`If a feature is not necessary to give meaning to what the inventor
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`means by a claim term, it would be “extraneous” and should not be read into
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`the claim. Hoganas AB v. Dresser Indus., Inc., 9 F.3d 948, 950 (Fed. Cir.
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`1993); E.I. du Pont de Nemours & Co. v. Phillips Petroleum Co., 849 F.2d
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`1430, 1433 (Fed. Cir. 1988). If the applicant for patent desires to be its own
`
`lexicographer, the purported definition must be set forth in either the
`
`specification or prosecution history. CCS Fitness, Inc. v. Brunswick Corp.,
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`288 F.3d 1359, 1366 (Fed. Cir. 2002). And such a definition must be set
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`forth with reasonable clarity, deliberateness, and precision. Renishaw PLC
`
`v. Marposs Societa’ per Azioni, 158 F.3d 1243, 1249 (Fed. Cir. 1998); In re
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`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`Only terms which are in controversy need to be construed, and only to
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`the extent necessary to resolve the controversy. Wellman, Inc. v. Eastman
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`Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v. Am.
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`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). On the present
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`record, no claim term requires an express construction.
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`B. Alleged Anticipation of Claims 1–8 and 10–15 by Yamakawa
`
`Yamakawa
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`
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`The disclosure of Yamakawa relates to a method for producing a
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`semiconductor device, a field-effect transistor, in particular. Ex. 1003 ¶ 1.
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`According to Yamakawa, it was known to be desirable to increase carrier
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`mobility of a channel in a silicon substrate by applying a stress to the
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`channel. Id. ¶¶ 1, 7. Also according to Yamakawa, the applied stress is
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`weakened by reaction from the gate electrode disposed above the channel,
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`and thus the applied stress is rendered less effective. Id. ¶ 11.
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`IPR2015-01318
`Patent 8,252,675 B2
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`Yamakawa describes solving the problem by introducing two
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`allegedly new techniques to conventional fabrication methods. It forms the
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`stress applying layers and the channel at a location deeper than at the surface
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`of the semiconductor substrate by digging down more into the substrate. Id.
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`¶¶ 14, 15. Additionally, in sequence, it forms a dummy gate electrode, then
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`epitaxially grows the stress applying layers, then removes the dummy gate
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`electrode, and then finally forms a new gate electrode. Id. ¶ 16. According
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`to Yamakawa, by removing the dummy gate electrode after formation of the
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`stress applying layers, the stress from the stress applying layers, applied to
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`the channel, would not be weakened by reason of reaction with the dummy
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`gate electrode. Id. ¶ 17.
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`
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`In the Background Art portion of Yamakawa, it is described that a
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`conventional process that forms an impurity diffused layer such as a source
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`region and a drain region “after” formation of a gate electrode causes
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`problems if the gate electrode is made of certain metallic material, because
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`the metallic material reacts to high temperature heat treatment. Id. ¶ 5.
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`Yamakawa further describes, in its Background Art portion, that to solve
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`such problems, the source and drain regions can be formed in the presence
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`of a dummy gate, and then the dummy gate can be removed and replaced by
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`a new gate electrode. Id. ¶ 6.
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`Discussion
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`
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`To establish anticipation, each and every element in a claim, arranged
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`as recited in the claim, must be found in a single prior art reference.
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`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
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`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
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`IPR2015-01318
`Patent 8,252,675 B2
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`2001). That means for a proper anticipation analysis, one may not pick and
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`choose selectively from different embodiments to satisfy the claimed
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`invention. See In re Arkley, 455 F.2d 586, 587 (CCPA 1972).
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`We have reviewed the Petition filed by Petitioner and the Preliminary
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`Response filed by Patent Owner, and determined that Petitioner has not
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`shown a reasonable likelihood that it would prevail in establishing
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`unpatentability of any of claims 1–8 and 10–15 as anticipated by
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`Yamakawa.
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`1.
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`Independent Claims 1 and 6
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`
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`Initially, we focus on certain limitations of independent claims 1 and 6
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`that are disclosed in Yamakawa.
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`
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`Claim 1 recites what Petitioner refers to as limitations 1(a), 1(b), and
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`1(c): (a) forming a gate insulating layer on a substrate; (b) forming a metal
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`buffer gate electrode layer on the gate insulating layer; and (c) forming a
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`dummy gate electrode layer on the buffer gate electrode layer, said dummy
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`gate electrode layer and said buffer gate electrode layer comprising different
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`materials. Claim 6 recites similar limitations. Petitioner has sufficiently
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`shown that these limitations are present in the embodiment illustrated in
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`Yamakawa Figures 16 and 17.
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`
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`Figure 16(4) of Yamakawa is reproduced below:
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`IPR2015-01318
`Patent 8,252,675 B2
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`Figure 16(4) illustrates a sectional view of an intermediate structure formed
`
`by a process described in Yamakawa. Id. ¶ 36. Citing Yamakawa
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`paragraphs 56, 135 and 136 and Declaration paragraphs 77, 78, and 80 of
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`Dr. Lee, Petitioner explains, in connection with Figure 16(4), how
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`Yamakawa discloses (a) forming a gate insulating layer, i.e., the layer
`
`beneath layer 50 in Figure 16(4), (b) forming a metal buffer gate electrode
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`layer, i.e., layer 50 in Figure 16(4), on the gate insulating layer, and
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`(c) forming a dummy gate electrode layer, i.e., film 27, on the buffer gate
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`electrode layer, where the dummy gate electrode layer and the buffer gate
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`electrode layer comprise different materials. Pet. 27, 28. Specifically, it is
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`explained that cap layer 50, which Petitioner maps to the recited metal buffer
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`gate electrode, is made of titanium nitride (Pet. 27), and that film 27, which
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`Petitioner maps to the recited dummy gate electrode layer, is made of
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`polysilicon or amorphous silicon (Pet. 28).
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`Claim 1 further recites what Petitioner refers to as limitations 1(d),
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`1(e), and 1(h): (d) patterning the dummy gate electrode layer and the buffer
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`gate electrode layer in sequence to define a buffer gate electrode on the gate
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`insulating layer and a dummy gate electrode on the buffer gate electrode;
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`(e) forming electrically insulating spacers on sidewalls of the dummy gate
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`electrode and on sidewalls of the buffer gate electrode; and (h) removing the
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`dummy gate electrode from between the spacers by selectively etching back
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`the dummy gate electrode using the mold layer and the spacers as an etching
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`mask. Claim 6 recites similar limitations. Petitioner has sufficiently shown
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`that these limitations are present in the embodiment of Yamakawa Figures
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`11
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`16 and 17.
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`IPR2015-01318
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`With regard to limitation 1(d), we reproduce Yamakawa Figure 16(5):
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`
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`Figure 16(5) illustrates a cross-section of an intermediate structure formed
`
`by the process that formed the structure shown in Figure 16(4). Id. ¶ 36.
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`Citing Yamakawa paragraph 137 and Declaration paragraph 81 of Dr. Lee,
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`Petitioner explains how Yamakawa discloses patterning the dummy gate
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`electrode layer and the buffer gate electrode layer in sequence to define a
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`buffer gate electrode on the gate insulating layer and a dummy gate
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`electrode on the buffer gate electrode. Pet. 29. In particular, Petitioner cites
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`the following text in Yamakawa (Pet. 29):
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`The dummy gate electrode film 27 is then patterned into a
`dummy gate electrode 27a by etching from over the patterned
`hard mask layer 29. In addition, following the etching of the
`dummy gate electrode film 27, the cap film 50 is etched, and
`then the gate insulating film is etched. Thereby, the gate
`insulating film 5 is left only under a dummy gate structure A.
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`Ex. 1003 ¶ 137.
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`With regard to limitation 1(e), we reproduce Yamakawa Figure 17(1):
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`Figure 17(1) illustrates a cross-section of an intermediate structure formed
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`by the process that formed the structure of Figure 16(5). Id. ¶ 37. Citing
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`Yamakawa paragraphs 104, and 108, and 139, and Declaration paragraphs
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`83 and 84 of Dr. Lee, Petitioner explains how Yamakawa discloses forming
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`insulating spacers 11-1 and 11-2 on the sidewalls of dummy gate electrode
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`27a and the sidewalls of buffer gate electrode (cap film 50). Pet. 30.
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`Petitioner identifies numeral 13 as designating an insulating mold layer
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`comprising silicon oxide, citing Yamakawa paragraph 110 and Declaration
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`paragraph 86 of Dr. Lee. Pet. 31.
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`With regard to limitation 1(h), we reproduce Yamakawa Figure 17(2):
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`
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`Figure 17(2) illustrates a cross-section of an intermediate structure formed
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`by the process that formed the structure shown in Figure 17(1). Id. ¶ 37.
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`Citing Yamakawa paragraphs 140 and 141 and Declaration paragraph 88 of
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`Dr. Lee, Petitioner explains, in conjunction with Figure 17(2), how
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`Yamakawa discloses removing the dummy gate electrode from between the
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`spacers by selectively etching back the dummy gate electrode using the mold
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`layer and the spacers as an etching mask. Pet. 32–33. In particular,
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`Petitioner refers to Yamakawa’s description in paragraph 141 that groove
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`pattern 15 is obtained by removing dummy gate structure A. Pet. 32.
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`The Figure reproduced by Petitioner on page 32 of the Petition, in
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`connection with the discussion and analysis with respect to limitation 1(h), is
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`taken from Yamakawa Figure 18(2), rather than from Yamakawa Figure
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`17(2) as identified and referenced in the corresponding text in the Petition.
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`In a joint conference call with the Board held on September 28, 2015,
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`counsel for Petitioner identified that error and explained that the illustration
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`should have been taken from Yamakawa Figure 17(2) as referred to in the
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`corresponding text, and not from Yamakawa Figure 18(2) as the illustration
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`now appears in the Petition in connection with limitation 1(h). Paper 7. In
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`the same conference call, counsel for Petitioner expressly retracted any
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`perceived reliance on Yamakawa’s Figure 18(2) and confirms reliance on
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`Yamakawa’s Figure 17(2), consistent with the text in the Petition. Id.
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`Petitioner has not, however, sufficiently identified disclosure in
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`Yamakawa for what it regards as limitation 1(i): “depositing a first metal
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`layer onto an upper surface of the mold layer and onto inner sidewalls of the
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`spacers and onto an upper surface of the buffer gate electrode.” Claim 6 has
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`a similar limitation, which for the same reasons also is not adequately
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`accounted for by Petitioner. This deficiency stems from the requirement that
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`the first metal layer must be deposited onto the upper surface of the buffer
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`gate electrode.
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`To account for limitation 1(i) and the similar limitation in claim 6,
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`Petitioner cites to and discusses an illustration taken from Yamakawa
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`Figure 18(4). Pet. 33–34. Yamakawa’s Figure 18(4) is reproduced below:
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`Figure 18(4) illustrates a cross-sectional view of an intermediate structure
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`formed by a process disclosed in Yamakawa. Id. ¶ 38. Figure 18(4)
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`includes two depictions, placed side-by-side. The one on the left is that of
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`an nMOS region on the semiconductor substrate and the one on the right is
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`that of a pMOS region on the semiconductor substrate.2 Citing Yamakawa
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`paragraph 154 and Declaration paragraphs 91 and 92, Petitioner explains
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`that working function controlling layer 53 is a first metal layer deposited
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`onto the upper surface of mold layer 13, the inner sidewalls of the spacers,
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`and an upper surface of buffer gate electrode 50. Pet. 33–34. It is evident
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`that Petitioner is referring to the right-side depiction or the pMOS region of
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`the semiconductor device as shown in Figure 18(4). The reference numeral
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`50 is absent in the depiction, but buffer gate electrode 50 is that layer
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`directly under work function controlling layer 53 in groove 15.
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`
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`Patent Owner correctly notes that Yamakawa’s Figure 18 embodiment
`
`is not the same as the embodiment illustrated in and discussed in connection
`
`with Yamakawa’s Figures 16–17. Prelim. Resp. 6–7. Petitioner has relied
`
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`2 Figure 18 in Yamakawa includes 5 sub-figures (1) through (5), and
`includes the caption “nMOS REGION” above the left depiction in all the
`sub-figures and the caption “pMOS REGION” above the right depiction in
`all the sub-figures.
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`on the embodiment of Yamakawa’s Figures 16–17 to account for what it
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`refers to as limitations 1(a), 1(b), 1(c), 1(d), 1(e), 1(h), and corresponding
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`limitations in claim 6, and seeks to rely on the embodiment of Yamakawa’s
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`Figure 18 to account for what it refers to as limitation 1(i) and the
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`corresponding limitation in claim 6. Patent Owner explains that Petitioner’s
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`mid-claim switch from Yamakawa’s embodiment of Figures 16–17 to
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`Yamakawa’s embodiment of Figure 18 is significant because although
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`limitation 1(i) requires depositing a first metal layer on the buffer gate
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`electrode, in the Yamakawa embodiment of Figures 16–17, the buffer gate
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`electrode layer 50 (cap film 50) is removed prior to depositing the first metal
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`layer. Prelim. Resp. 5–7. In that regard, Yamakawa states:
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`Next, as shown in (2) of FIG. 17, the dummy gate
`
`electrode 27a of polysilicon or amorphous silicon is removed
`by dry etching. At this time, the cap film 50 is used as an
`etching stopper . . . . Thereafter, the cap film 50 is selectively
`removed by wet etching or dry etching that causes little etching
`damage to the foundation.
`
`Ex. 1003 ¶ 140 (emphasis added). Indeed, Figure 17(2), reproduced above,
`
`shows such removal of cap film or buffer electrode layer 50. There is no
`
`such removal in the pMOS region of the device shown in Figure 18(2), the
`
`portion relied on by Petitioner, as discussed above, to satisfy limitation 1(i).
`
`
`
`Yamakawa’s Figure 18(4) is based on Yamakawa’s Figure 18(2), not
`
`Figure 17(2). We note further that, as discussed above, in a conference call
`
`held on September 28, 2015, Petitioner withdrew any perceived reliance on
`
`Yamakawa’s Figure 18(2) in connection with limitation 1(h). Paper 7.
`
`Petitioner has not adequately explained how, in an anticipation analysis, it
`
`
`
`16
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`IPR2015-01318
`Patent 8,252,675 B2
`
`
`properly can rely on Yamakawa’s embodiment of Figure 18 to account for
`
`limitation 1(i) when it has relied on Yamakawa’s embodiment of Figures
`
`16–17 to account for limitations 1(a), 1(b), 1(c), 1(d), 1(e), and 1(h).
`
`
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`Patent Owner persuasively asserts that “Petitioner provides no
`
`explanation on the relationship between these two embodiments and how
`
`they somehow relate to the same process and involve the same features
`
`required to support the anticipation ground presented in the Petition.”
`
`Prelim. Resp. 9–10. On this record, Petitioner has picked selectively from
`
`two separate embodiments to account for all the limitations of claim 1 and
`
`claim 6. Yamakawa itself does not appear to make clear what process steps
`
`are common between its embodiment of Figure 18 and its embodiment of
`
`Figures 16–17, and Petitioner has not provided an adequate explanation.
`
`
`
`Claim 1 finally recites:
`
`filling a space between the inner sidewalls of the spacers by
`depositing a second metal layer onto a portion of the first metal
`layer extending between the inner sidewalls of the spacers to
`thereby define a metal gate electrode comprising a composite of
`the second metal layer, a portion of the first metal layer having
`a U-shaped cross-section and the buffer gate electrode.
`
`Ex. 1001, 11:20–26. As in the case of limitation 1(i), this final limitation
`
`requires the presence of the buffer gate electrode which is removed in the
`
`embodiment of Yamakawa Figures 16–17. To satisfy this limitation,
`
`Petitioner relies on Yamakawa’s Figure 18 embodiment. Pet. 34–36. A
`
`similar limitation exists in claim 6, for which Petitioner also relies on
`
`Yamakawa’s Figure 18 embodiment. Thus, Petitioner’s analysis for this
`
`limitation and the corresponding limitation in claim 6 is also improper.
`
`
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`17
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`IPR2015-01318
`Patent 8,252,675 B2
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`For the foregoing reasons, we determine that Petitioner has not shown
`
`a reasonable likelihood that it would prevail in establishing unpatentability
`
`of either claim 1 or claim 6 as anticipated by Yamakawa.
`
`2.
`
`Dependent Claims 2–5, 7, 8, and 10–15
`
`
`
`Claims 2–5 each depend directly from claim 1. Claims 7, 8, and 10–
`
`15 each depend, directly or indirectly, from claim 6. The deficiency
`
`discussed above with respect to independent claims 1 and 6 similarly
`
`negatively affects Petitioner’s analysis of these dependent claims.
`
`Accordingly, we determine that Petitioner has not shown a reasonable
`
`likelihood that it would prevail in establishing unpatentability of any of
`
`claims 2–5, 7, 8, and 10–15 as anticipated by Yamakawa.
`
`C. Alleged Obviousness of Claims 9 over Yamakawa and Yeh
`
`
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`Claim 9 depends from claim 8, and claim 8 depends from claim 6.
`
`Petitioner relies on Yeh to account for the limitation specifically added by
`
`claim 9 relative to base claims 8 and 6. Petitioner’s application of Yeh does
`
`not eliminate the above-discussed deficiencies of Yamakawa as applied to
`
`base claim 6. Accordingly, we determine that Petitioner has not shown a
`
`reasonable likelihood that it would prevail in establishing unpatentability of
`
`claim 9 as obvious over Yamakawa and Yeh.
`
`III. CONCLUSION
`
`
`
`Petitioner has not demonstrated a reasonable likelihood that it would
`
`prevail in establishing that any of claims 1–15 is unpatentable. We do not
`
`institute an inter partes review of any claim of the ’675 patent.
`
`
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`18
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`IPR2015-01318
`Patent 8,252,675 B2
`
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`It is
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`IV. ORDER
`
`ORDERED that the Petition is denied, and that we do not institute an
`
`inter partes review of any claim of the ’675 patent.
`
`
`
`For PETITIONER:
`
`Robert Steinberg
`Julie Holloway
`Clement Naples
`bob.steinberg@lw.com
`julie.holloway@lw.com
`clement.naples@lw.com
`
`
`For PATENT OWNER:
`
`Naveen Modi
`Joseph Palys
`nVidia-Samsung-IPR@paulhastings.com
`
`
`
`
`19
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