Petition for Inter Partes Review of USP 8,252,675
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`In re Inter Partes Review of:
`U.S. Patent No. 8,252,675
`Issued: August 28, 2012
`Application No.: 12/942,763
`Filing Date: November 9, 2010
`
`For: Methods of Forming CMOS Transistors with High Conductivity Gate
`Electrodes
`
`
`FILED VIA PRPS
`
`
`DECLARATION OF JACK LEE IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,252,675
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`For ease of reference, Dr. Lee refers to this declaration as being in support of “the
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`’675 Petition” challenging all claims of the ’675 patent.
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`NVIDIA Corp.
`Exhibit 1006
`Page 001
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`Petition for Inter Partes Review of USP 8,252,675
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`TABLE OF CONTENTS
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`I.
`
`II.
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`INTRODUCTION AND QUALIFICATIONS ............................................... 1
`
`UNDERSTANDING OF THE GOVERNING LAW ..................................... 4
`
`A.
`B.
`C.
`D.
`
`Invalidity By Anticipation Or Obviousness .......................................... 4
`Interpreting Claims Before The Patent Office ...................................... 5
`Relevant Time Period For The Obviousness Analysis ......................... 6
`Basis For My Opinion ........................................................................... 6
`
`III. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME .................................................................................................. 6
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`IV. PERSPECTIVE APPLIED IN THIS DECLARATION ................................. 7
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`V. OVERVIEW OF THE ’675 PATENT ............................................................ 7
`
`A.
`B.
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`Technology Background ....................................................................... 7
`Forming the Gate Electrodes ............................................................... 11
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`VI. OVERVIEW OF THE PRIOR ART ............................................................. 19
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`A. U.S. Pub. No. 2009/0065809 (“Yamakawa”) ..................................... 19
`B.
`U.S. Patent No. 8,039,381 (“Yeh”) ..................................................... 27
`C.
`’675 Patent Prosecution History .......................................................... 32
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`VII. MOTIVATIONS TO COMBINE THE PRIOR ART REFERENCES ......... 34
`
`A. Motivation To Combine Yamakawa with Yeh ................................... 34
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`VIII. YAMAKAWA GLOSSARY ........................................................................ 36
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`IX. CLAIM CONSTRUCTIONS ........................................................................ 37
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`A.
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`Legal Standard ..................................................................................... 37
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`X.
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`SUMMARY OF OPINIONS ......................................................................... 38
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`XI. FIRST GROUND OF INVALIDITY ............................................................ 38
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`i
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`NVIDIA Corp.
`Exhibit 1006
`Page 002
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`Petition for Inter Partes Review of USP 8,252,675
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`A.
`Claim 1 ................................................................................................ 38
`Claim 2 ................................................................................................ 52
`B.
`Claim 3 ................................................................................................ 54
`C.
`Claim 4 ................................................................................................ 55
`D.
`Claim 5 ................................................................................................ 55
`E.
`Claim 6 ................................................................................................ 55
`F.
`Claim 7 ................................................................................................ 62
`G.
`Claim 8 ................................................................................................ 64
`H.
`Claim 10 .............................................................................................. 64
`I.
`Claim 11 .............................................................................................. 67
`J.
`Claim 12 .............................................................................................. 69
`K.
`Claim 13 .............................................................................................. 74
`L.
`M. Claim 14 .............................................................................................. 77
`N.
`Claim 15 .............................................................................................. 78
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`XII. SECOND GROUND OF INVALIDITY ....................................................... 79
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`Claim 9 ................................................................................................ 79
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`A.
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`ii
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`NVIDIA Corp.
`Exhibit 1006
`Page 003
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`Petition for Inter Partes Review of USP 8,252,675
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`I, Jack Lee, Professor of the Electrical and Computer Engineering
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`Department at The University of Texas at Austin, hereby declare as follows:
`
`I.
`
`INTRODUCTION AND QUALIFICATIONS
`1.
`
`I have been retained by NVIDIA Corporation (“NVIDIA”) to provide
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`my opinion concerning the validity of U.S. Patent No. 8,252,675 (Ex. 1001, “the
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`’675 patent”) in support of its Petition for Inter Partes Review of U.S. Patent No.
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`8,252,675 (“Petition”).
`
`2.
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`I am an expert in the field of semiconductor process technology and
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`semiconductor design. I have over 30 years of first-hand experience as a
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`researcher, educator, and consultant in this field.
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`3.
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`I received a B.S. degree in Electrical Engineering, with highest
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`honors, in 1980, and an M.S. degree in Electrical Engineering in 1981, both from
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`University of California, Los Angeles. I received a Ph.D. degree in Electrical
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`Engineering in 1988 from University of California, Berkeley (“UC Berkeley”).
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`TRW Microelectronics Center, in the High‐Speed Bipolar Device Program.
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`4.
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`From 1979 to 1984, I was a Member of Technical Staff at the
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`I worked on bipolar device/circuit design, fabrication, and testing. I was promoted
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`to Engineering Group Leader level in 1983.
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`5.
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`I received several academic honors while at UC Berkeley.
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`For example, I won the Best Paper Award from the Institute of Electrical and
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`1
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`NVIDIA Corp.
`Exhibit 1006
`Page 004
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`Electronics Engineers (“IEEE”) International Reliability Physics Symposium in
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`1988. I was also awarded a Lectureship with my own teaching assistant from UC
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`Berkeley.
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`6.
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`After receiving my Ph.D. in August 1988, I joined the faculty at The
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`University of Texas at Austin (“UT Austin”). As a faculty member, I have taught
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`numerous courses in semiconductor device fabrication and design, at both the
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`undergraduate and graduate levels. I have supervised 40 students who received a
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`doctoral degree under my guidance. I am currently the Cullen Trust for Higher
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`and Computer Engineering at UT Austin.
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`Education Endowed Professor in Engineering #4 in the Department of Electrical
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`7. My current research interests include: high‐K gate dielectrics and
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`metal gate
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`electrodes
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`in
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`semiconductor devices
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`(CMOS/MOSFETs);
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`semiconductor device fabrication processes, characterization and modeling;
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`dielectric processes, characterization and reliability; and alternative transistor
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`channel materials. My research has been partially supported by grants from the
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`National Science Foundation, the Texas Advanced Research Program, the
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`Semiconductor Research Corporation (SRC), SEMATECH, Texas Emerging
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`Technology Funds, and others.
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`8.
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`I have authored over 500 journal publications and conference
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`proceeding papers, and have coauthored one book and two book chapters on
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`2
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`NVIDIA Corp.
`Exhibit 1006
`Page 005
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`Petition for Inter Partes Review of USP 8,252,675
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`semiconductor devices. Much of my research and publications since ~1998 focus
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`on the topic of gate stacks, including high-K gate dielectrics and gate-first vs. gate-
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`last processes. I am a named inventor of several U.S. patents, including:
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`• U.S. Patent No. 6,013,546 (“Semiconductor Device Having a
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`PMOS Device with a Source/Drain Region Formed Using a Heavy
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`Atom p-Type Implant and Method of Manufacture Thereof”)
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`• U.S. Patent No. 6,057,584 (“Semiconductor Device Having a
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`Tri-Layer Gate Insulating Dielectric”)
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`• U.S. Patent No. 6,146,934
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`(“Semiconductor Device with
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`Asymmetric PMOS Source/Drain
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`Implant and Method of
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`Manufacture Thereof”)
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`• U.S. Patent No. 6,306,742 (“Method for Forming a High Dielectric
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`Constant Insulator in the Fabrication of an Integrated Circuit”)
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`• U.S. Patent No. 5,891,798 (“Method for Forming a High Dielectric
`
`Constant Insulator in the Fabrication of an Integrated Circuit”)
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`9.
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`I have also earned many research awards including the prestigious
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`SRC Inventor Recognition Award from Semiconductor Research Corporation for
`
`my work on dielectric technology and characterization.
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`understanding and development of ultra‐thin dielectrics and their application to
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`10.
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`In 2002, I became an IEEE fellow for my “contributions to the
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`3
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`NVIDIA Corp.
`Exhibit 1006
`Page 006
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`Petition for Inter Partes Review of USP 8,252,675
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`silicon devices.” I am also an IEEE Electron Devices Society Distinguished
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`Lecturer.
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`11.
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`I have served in various technology consulting and business advisor
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`roles. For example, I have taught short courses on semiconductor device physics
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`and
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`technologies at various semiconductor companies and consortiums
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`(e.g., SEMATECH). I have also organized several international conferences and
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`have given lectures at numerous conferences and symposia, including the
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`International Symposium on VLSI Technologies, the IEEE Symposia on
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`VLSI Technology, and the IEEE International Electron Devices Meeting. These
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`conferences are some of the most prestigious in the field.
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`12. My Curriculum Vitae is provided as Ex. 1005.
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`13. My work in this matter is being billed at a rate of $475 per hour, with
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`reimbursement for necessary and reasonable expenses. My compensation is not in
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`any way contingent upon the outcome of this Inter Partes Review. I have no
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`interest in the outcome of this proceeding or any related litigation.
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`II. UNDERSTANDING OF THE GOVERNING LAW
`
`A.
`14.
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`Invalidity By Anticipation Or Obviousness
`
`I understand that a claim is invalid if it is anticipated or obvious. I
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`understand that anticipation of a claim requires that every element of a claim is
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`disclosed expressly or inherently in a single prior art reference, arranged as in the
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`4
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`NVIDIA Corp.
`Exhibit 1006
`Page 007
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`claim.
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`Petition for Inter Partes Review of USP 8,252,675
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`15.
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`I further understand that obviousness of a claim requires that the claim
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`be obvious from the perspective of a person of ordinary skill in the relevant art, at
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`the time the invention was made. In analyzing obviousness, I understand that it is
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`important to understand the scope of the claims, the level of skill in the relevant
`
`art, the scope and content of the prior art, the differences between the prior art and
`
`the claims, and any secondary considerations. I also understand that if a technique
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`has been used to improve one device, and a person of ordinary skill in the art
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`would recognize that it would improve similar devices in the same way, using the
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`technique is obvious unless its actual application is beyond his or her skill. There
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`may also be a specific teaching, suggestion or motivation to combine any first prior
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`art reference with a second prior art reference. Such a teaching, suggestion, or
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`motivation to combine the first prior art reference with the second prior art
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`reference can be explicit or implicit in the first or second prior art references.
`
`B.
`16.
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`Interpreting Claims Before The Patent Office
`I understand that “Inter Partes Review” is a proceeding before the
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`United States Patent & Trademark Office (“Patent Office”) for evaluating the
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`validity of an issued patent claim. Claims in an Inter Partes Review are given
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`their broadest reasonable interpretation that is consistent with the patent
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`specification. I understand that a patent’s “specification” includes all the figures,
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`5
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`NVIDIA Corp.
`Exhibit 1006
`Page 008
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`discussion, and claims within the patent document. I understand that the Patent
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`Office will look to the specification to see if there is a definition for a claim term,
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`and if not, will apply the broadest reasonable interpretation from the perspective of
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`a person of ordinary skill in the art.
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`C. Relevant Time Period For The Obviousness Analysis
`17.
`I also understand that the earliest patent application filing leading to
`
`the ’675 patent was made in November 9, 2010, and that the patentee has claimed
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`priority back to December 8, 2009. I have therefore analyzed obviousness as of
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`approximately late 2009 or slightly before, understanding that as time passes, the
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`knowledge of a person of ordinary skill in the art will increase.
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`D. Basis For My Opinion
`18.
`In forming my opinion, I have relied on the ’675 patent claims,
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`disclosure and prosecution history, the prior art exhibits to the Petition for Inter
`
`Partes Review of the ’675 patent, and my own experience, expertise and
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`knowledge of a person of ordinary skill in the relevant art in the relevant
`
`timeframe.
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`III. LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
`19.
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`In 2009, I believe that a relevant person of ordinary skill in the art
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`would have had an undergraduate degree in electrical engineering (or equivalent
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`subject) together with three to four years of post-graduate experience designing
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`NVIDIA Corp.
`Exhibit 1006
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`semiconductor devices and fabrication processes, or a master’s degree in electrical
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`engineering (or equivalent subject) together with one to two years of post-graduate
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`experience in designing semiconductor devices and fabrication processes. A
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`person of ordinary skill also would have been familiar with the gate-last (or gate
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`replacement) technique of forming metal gate electrodes. This description is
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`approximate, and a higher level of education or skill might make up for less
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`experience, and vice-versa.
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`20.
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` I believe that I would qualify as at least a person of ordinary skill in
`
`the art in 2009, and that I have a sufficient level of knowledge, experience and
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`education to provide an opinion in the field of the ’675 patent. In 2009, I was
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`familiar with the general subject material in the cited prior art in this Declaration.
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`IV. PERSPECTIVE APPLIED IN THIS DECLARATION
`21. My testimony in this declaration is given from the perspective of a
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`person of ordinary skill in the art at the time of the filing of the ’675 patent, and for
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`some time before then, unless otherwise specifically indicated. This is true even if
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`the testimony is given in the present tense. Each of the statements below is my
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`opinion based on my review of the ’675 patent and its claims, as well as the prior
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`art cited in this declaration and the prosecution history of the ’675 patent.
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`V. OVERVIEW OF THE ’675 PATENT
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`A. Technology Background
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`7
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`NVIDIA Corp.
`Exhibit 1006
`Page 010
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`Petition for Inter Partes Review of USP 8,252,675
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`NMOS and PMOS Transistors
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`1.
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`22. There are two basic types of metal-oxide-semiconductor (MOS)
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`transistors, in accordance with the channel type which is induced beneath the gate
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`electrode: NMOS transistors and PMOS transistors. ’675 patent at 1:24-26.
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`CMOS is a common design technique that uses complementary and matching pairs
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`of NMOS and PMOS transistors. See id. at 2:4-8. NMOS transistors contain n-
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`type source and drain regions that are separated by a p-type body region.
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`PMOS transistors contain p-type source and drain regions that are separated by an
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`n-type body region. The n-type regions contain an excess of negative charge
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`carriers (electrons), whereas the p-type regions contain an excess of positive
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`charge carriers (holes). A threshold voltage is the minimum gate-to-source voltage
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`differential required to form the channel, or induce the corresponding flow of
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`charge carriers, beneath the PMOS and NMOS transistors.
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`23. While conventional MOS transistors used a gate electrode formed of
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`polysilicon, the ’675 patent focused on the use of metal materials to form the MOS
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`gates. It had been known for some time that metal materials could be used to form
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`gate electrodes which provided superior electric conductivity to the polysilicon
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`material. Id. at 1:20-24. Further, the gate electrodes of the NMOS and PMOS
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`transistors may be formed of different metals so that the NMOS transistor and the
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`8
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`NVIDIA Corp.
`Exhibit 1006
`Page 011
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`PMOS transistor have different threshold voltages. The operating voltages of
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`NMOS and PMOS transistors may also be different. Id. at 1:27-30, 6:24-25.
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`2. Gate-First versus Gate-Last
`24. MOS transistors are fabricated on a semiconductor substrate, using
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`numerous material deposition and etching processes. Multiple layers are deposited
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`on a substrate, before the individual gates are patterned using a mask and etch-back
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`process. Various processes are used to form other basic structures on the
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`semiconductor device, such as spacers on the gates, contact holes and vias to
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`provide interconnection, field oxide layers to provide isolation between active
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`regions, diffusion regions, etc. Metal layers provide interconnection throughout
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`the device.
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`25. For many generations, MOS transistors were fabricated with the gate-
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`first approach. In a gate-first process, the layers of a gate electrode are formed and
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`patterned. Spacers are formed on the sides of the patterned gate stacks. The gate
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`stack and spacers then serve as a mask for source and drain ion implantation on the
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`active region of the substrate—this is a self-aligning process to ensure the source
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`and drain form just outside the edges of the gate electrode. After the source/drain
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`implant, a high-temperature anneal is applied to activate the dopants and repair the
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`damage done during implantation.
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`26. With a high-K metal gate stack, the gate-last process (aka the
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`9
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`Exhibit 1006
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`replacement gate process) is considered because the high-temperature source/drain
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`anneal step can negatively impact the long-term integrity of the gate stack. In a
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`gate-last process, first dummy gates (aka sacrificial gates) using material such as
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`polysilicon are formed through the patterning process. Just as in the gate-first
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`process, a source/drain implantation and high-temperature anneal follows using the
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`dummy gates as masks—but this time, the actual metal gate has not yet been
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`formed, and thus is not subject to the high temperature process. Instead, once
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`anneal is complete, the dummy gates are removed, forming a trench where
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`subsequent metal layers are deposited to form the actual gate electrode. This is the
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`“gate-last” approach, where a dummy gate acts as a placeholder until the metal
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`layers are ready to be deposited. The advantage of the gate-last process is that the
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`gate stacks do not suffer from the detrimental high-temperature source/drain
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`formation processes, while still maintaining the benefits of using the gate stacks for
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`self-alignment.
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`27. However, the gate-last process also poses challenges. For example,
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`the gate-last process requires polishing steps (CMP). If there were wide spaces
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`between gates, the surface would be polished down faster, resulting in “dishing”
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`effects. Furthermore, filling of the trenches results in U-shape gate-electrode
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`structure, which in turn results in non-uniform characteristics along the channel
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`regions and uncontrollable threshold voltage as devices scales down.
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`10
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`NVIDIA Corp.
`Exhibit 1006
`Page 013
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`28. Before the ’675 patent was filed, companies had known of these
`
`particular steps for replacing a dummy gate with metal layers. The ’675 patent
`
`describes basic and well-known fabrication techniques for creating a PMOS and
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`NMOS transistor using the gate-last process.
`
`B.
`Forming the Gate Electrodes
`29. The ’675 patent describes a method for fabricating metal PMOS and
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`NMOS gate electrodes of a CMOS device. The ’675 patent relies on well-known
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`techniques of forming gates with spacers on a substrate, for example:
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`• Layers comprising the gate, such as dielectric, dummy polysilicon, or metal
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`layers are deposited using a method such as chemical vapor deposition
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`(CVD), physical vapor deposition (PVD), atomic layer deposition (ALD),
`
`etc.;
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`• Spacers are formed on the sidewalls of gates;
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`• Layers are planarized using chemical mechanical polishing (CMP) after a
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`fill-in layer is deposited or mold layer is formed, to expose the top of the
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`gate or a particular layer of the gate;
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`• Photo resist patterns are used to mask and selectively etch gate stacks or
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`remove dummy poly
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`The fabrication steps are described in more detail below.
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`30. First, the initial layers for forming a dummy gate electrode are
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`Exhibit 1006
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`deposited on a substrate 10. Starting from the bottom, a gate insulating layer 18, a
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`buffer gate electrode 20, and a dummy gate electrode 22 are formed and stacked on
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`the substrate 10, as shown in Fig. 2:
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`
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`Id. at Fig. 2, 3:28-30.
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`31. A photo-lithography process and etching process are then performed
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`to pattern dummy gate stacks, from layers 18, 20, and 22. Id. at 3:45-47. In a
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`photo-lithography process, a first photo resist pattern is formed on the dummy gate
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`electrode 22. Id. at 3:48-50. The dummy gate electrode 22, the buffer gate
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`electrode 20, and the gate insulating layer 18 are etched in succession to define a
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`gate stack according to the photo resist pattern. Id. at 3:50-53. Fig. 3 shows two
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`patterned gate stacks:
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`12
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`Exhibit 1006
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`Id. at Fig. 3.
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`32. Following formation of the dummy gate stacks,1 spacers 28 are
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`formed on a sidewall of the stacks, as shown in Fig. 6:
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`
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`
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`Id. at Fig. 6. Spacers are formed through a process depositing a silicon nitride
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`layer conformally on the gate stacks and substrate, through a chemical vapor
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`deposition process. Id. at 4:9-12. The silicon nitride layer is anisotropically
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`etched, so that only the spacers 28 remain on the sidewalls of the gate stacks. Id. at
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`4:14-16.
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`1 While the ’675 patent discusses forming of source/drain regions in the
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`specification, those processes are not claimed and thus are not described here.
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`13
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`Exhibit 1006
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`33. After the source/drain regions are formed, a mold insulating layer 32
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`is deposited using a vapor deposition process to cover the substrate and the dummy
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`gate stacks. Id. at 4:47-49. The mold insulating layer comprises an insulating
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`material, such as silicon oxide. Id. at 4:49-50. The mold insulating layer 32 is
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`then planarized to the top of the dummy gate electrode 22, as shown in Fig. 9:
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`
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`Id. at Fig. 9, 4:53-54. Planarization may be performed by “chemical mechanical
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`polishing (CMP) or etch-back.” Id. at 4:54-57.
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`34.
`
`In the first phase described above, the dummy gate stacks are formed,
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`and spacers placed along their sides. In a subsequent phase as described below, the
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`dummy gate stacks are replaced with metal layers with appropriate work functions,
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`to form the gate electrodes for the transistors. The following figures show an
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`embodiment where PMOS (on the right) and NMOS (on the left) gates are formed
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`in separate processes with different layers, to vary the metal composition between
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`the PMOS and NMOS.
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`35.
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` Fig. 10 shows selective removal of dummy gate electrode 22 (shown
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`in Fig. 9) by forming a photo resist pattern 34 to cover the second active region,
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`and etching the dummy gate electrode 22 in a dry or wet etching process:
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`
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`Id. at Fig. 10, 4:58-64. The photo resist pattern 34, mold layer 32, spacers 28, and
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`buffer gate electrode 20 are used as an etch mask in the etching process to remove
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`the dummy gate. Id. at 4:64-67. The removal of the dummy gate forms a trench
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`35. Id. at 4:58-60.
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`36. With the dummy gate 22 remaining on the left side, and a trench 35
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`etched out on the right side, a first metal layer 36 is formed on the entire surface of
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`the substrate through a chemical vapor deposition or atomic layer deposition
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`process. Id. at 5:4-5.
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`
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`Id. at Fig. 11, 5:4-5. The first metal layer may comprise titanium nitride, for
`
`example. Id. at 5:5-8.
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`37. When the first metal layer 36 is formed, the ’675 patent expresses a
`
`concern that an “overhang” in the metal 36 may form at the top of the trench, as
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`shown in annotated Fig. 11:
`
`Id. at Fig. 11, 5:11-15. The overhang, if severe enough, would result in the
`
`formation of a “void” in the trench. Id. This is more clearly illustrated in Fig. 4 of
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`U.S. Patent No. 8,039,381 (“Yeh”), cited in the prosecution history of the ’675
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`16
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`NVIDIA Corp.
`Exhibit 1006
`Page 019
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`patent for the formation of an overhang 404 and void 408:
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`Petition for Inter Partes Review of USP 8,252,675
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`
`
`
`(Ex. 1004, Yeh at Fig. 4, 5:1-15.) Such formations may lead to deterioration in the
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`operation characteristic of the transistor. Id. at 6:36-41.
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`38. To alleviate the risk of forming a void, a method of forming a second
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`dummy filler layer into the trench 50, and then planarizing the dummy filler layer
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`while removing an upper portion of the first metal layer 36 is performed,
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`represented by Figs. 12-14 in the ’675 patent. In Fig. 15, the dummy filler layers
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`have been removed, leaving the recessed first metal layer 36 in a trench 40 on the
`
`right side, and a trench 43 with no metal layers on the left side:
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`17
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`NVIDIA Corp.
`Exhibit 1006
`Page 020
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`Id. at Fig. 15, 5:45-49.
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`39. A second metal layer 42 is deposited on the entire surface to fill the
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`trenches 40 and 43, as shown in Fig. 16:
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`
`
`
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`Id. at Fig. 16, 5:63-66. The second metal 42 may comprise aluminum, tungsten,
`
`titanium, or tantalum. Id. at 5:66-6:1. Because the second metal 42 fills in on top
`
`of the first metal layer, it is formed without a void in the trench 40. Id. at 6:2-3.
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`40. Finally, the second metal layer 42 is planarized to expose the mold
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`insulating layer 32, defining PMOS gate 46 and NMOS gate 48 on the active
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`regions, as shown in Fig. 17:
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`18
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`NVIDIA Corp.
`Exhibit 1006
`Page 021
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`Petition for Inter Partes Review of USP 8,252,675
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`Id. at Fig. 17, 6:4-8. Using selective processes, the PMOS and NMOS gates
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`
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`comprise different compositions of metals.
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`VI. OVERVIEW OF THE PRIOR ART
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`A. U.S. Pub. No. 2009/0065809 (“Yamakawa”)
`41. The ’675 patent describes a combination of steps for forming metal
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`gate electrodes, using a dummy gate replacement process (known as “gate last”).
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`These steps were disclosed by Sony Corporation in U.S. Patent Application
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`Publication No. 2009/0065809 (“Yamakawa”), listing Shinya Yamakawa as an
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`inventor and titled “Semiconductor Device and Method of Manufacturing
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`Semiconductor Memory Device.” (Ex. 1003.) Yamakawa was published on
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`March 12, 2009. Yamakawa is thus prior art to the ’675 patent under 35 U.S.C. §
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`102(b) and was not before the examiner during prosecution of the ’675 patent.
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`42. Yamakawa discloses a manufacturing method for a semiconductor
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`device made of metallic materials. Yamakawa at [0001]. Yamakawa discusses an
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`inherent problem of forming a metallic gate stack first, before forming the source
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`Exhibit 1006
`Page 022
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`and drain regions. Id. In a conventional “gate-first” process, the metal gate stack
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`is created first, and a high temperature heat treatment is subsequently applied for
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`impurity activation. Id. A negative consequence of forming the metal gate stack
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`first is that the heat treatment causes the metallic materials in the gate to react with
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`the adjacent gate insulating film. Id.
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`43. To solve this problem, Yamakawa discloses a gate process forming
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`the metal layers of the gate electrode after forming the source and drain regions.
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`Id. at [0006]. This is known as a “gate-last” process, or a “gate-replacement”
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`process, because the actual metal gate stack is formed last. First, a dummy gate is
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`formed as a placeholder, with sidewall spacers. Id. The heat treatment for
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`impurity activation in the source/drain is applied, while the gate stack still
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`comprises a dummy material. After the heat treatment, the dummy gate is
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`removed and replaced with the actual metal gate stack, using deposition of layers.
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`Id. Because the source/drain region was previously formed, no additional high
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`heat treatment is required. Id.
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`44. As discussed below, Yamakawa discloses the basic steps for the gate-
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`last process, which are identical to the steps claimed in the ’675 patent. While
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`Yamakawa further adds various improvements to the process, for example forming
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`in one embodiment a slight recess in the substrate to apply stress to the channel,
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`Yamakawa provides the same conventional steps of the gate-last process as
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`20
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`NVIDIA Corp.
`Exhibit 1006
`Page 023
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`disclosed in the ’675 patent. See, e.g., id. at [0005], [0018].
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`Petition for Inter Partes Review of USP 8,252,675
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`45. First, a gate insulating film 5 made of a high dielectric constant
`
`material is formed on the surface of a semiconductor substrate 3. Id. at [0134],
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`[0135]. A metal titanium nitride layer, called a “cap film” 50 is formed on the gate
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`insulating layer by a deposition method, as shown in Fig. 16(3):
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`
`
`Id. at Fig. 16(3), [0135]. Yamakawa shows in its figures a recess 3a in the
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`substrate, an improvement to apply stress to the channel. But Yamakawa
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`recognizes that in a different embodiment, as well as in other prior art, a recess is
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`not formed and the gate insulating layer and cap layer are deposited on a planar
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`substrate surface. See id. at Figs. 2-4, 20-21.
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`46. Then, a dummy gate electrode layer 27 of polysilicon or amorphous
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`silicon is formed on the cap layer 50, as shown in Fig. 16(4):
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`21
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`Exhibit 1006
`Page 024
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`Id. at Fig. 16(4), [0136]. The dummy gate electrode layer 27, metal layer cap film
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`50, and insulating film 5 are then patterned in sequence, by etching from over the
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`patterned hard mask layer 29, as shown in Fig. 16(5):
`
`
`
`a
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`Id. at Fig. 16(5), [0137].
`
`47. Yamakawa then discloses applying a conventional method for
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`forming sidewalls on both sides of the dummy gate structure A, described step by
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`step in an earlier disclosed embodiment in Figs. 10, 11, and 12 and accompanying
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`text [0104] to [0109]. Id. at [0139] (“After the above [process of Figure 16], the
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`process described with reference to FIG. 11 and FIG. 12 is performed …”). First,
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`insulative side walls 11-1 are formed, as shown in Fig. 10(5):
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`22
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`NVIDIA Corp.
`Exhibit 1006
`Page 025
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`Petition for Inter Partes Review of USP 8,252,675
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`Id. at Fig. 10(5), [0104]. A second set of insulative side walls 11-2 are formed on
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`the outside of the first side walls 11-1:
`
`a
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`
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`Id. at Fig. 12(1), [0109]. As further shown in Fig. 12(1), an impurity ion
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`implantation is then performed, with a heat treatment to activate the impurity. As
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`discussed by Yamakawa, the heat treatment has no effect on the eventual metal gate
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`stack, which has not been formed yet.
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`48. Then, an interlayer insulating film 13 is formed over the source/drain
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`region and the dummy gate structure A, as shown in Fig. 12(3):
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`23
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`NVIDIA Corp.
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