111111
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`1111111111111111111111111111111111111111111111111111111111111
`US008039381B2
`
`c12) United States Patent
`Yeh et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,039,381 B2
`Oct. 18, 2011
`
`(54) PHOTORESIST ETCH BACK METHOD FOR
`GATE LAST PROCESS
`
`(75)
`
`Inventors: Chiung-Han Yeh, Tainan (TW);
`Chen-Pin Hsu, Taoyuan (TW);
`Ming-Yuan Wu, Hsinchu (TW);
`Kong-Beng Thei, Hsinchu Country
`(TW); Harry Chuang, Hsinchu (TW)
`
`(73) Assignee: Taiwan Semiconductor Manufacturing
`Company, Ltd., Hsin-Chu (TW)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 60 days.
`
`(21) Appl. No.: 12/477,618
`
`(22) Filed:
`
`Jun.3,2009
`
`(65)
`
`Prior Publication Data
`
`US 2010/0065926 AI
`
`Mar. 18, 2010
`
`Related U.S. Application Data
`
`(60) Provisional application No. 61/096,633, filed on Sep.
`12, 2008, provisional application No. 61/109,317,
`filed on Oct. 29, 2008.
`
`(51)
`
`Int. Cl.
`HOJL 2114763
`(2006.01)
`HOJL 2113205
`(2006.01)
`(52) U.S. Cl. ................ 438/595; 438/183; 257/E21.626;
`257/E21.64
`(58) Field of Classification Search .................. 438/703,
`438/757, 595, 785, 183; 216/108, 109;
`257/E21.626, E21.64, E21.593, E21.636,
`257/E21.522, E21.635, E21.621
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,895,261 A * 4/1999 Schinella et a!.
`............. 438/586
`6,376,888 B1 * 4/2002 Tsunashima et a!. ......... 257/407
`3/2005 Ngo eta!.
`6,861,350 B1
`7,745,889 B2 * 6/2010 Lin eta!. ....................... 257/412
`2003/0227092 A1 * 12/2003 Liu eta!. ....................... 257/774
`2006/0035425 A1 * 2/2006 Carter et al.
`.................. 438/199
`3/2006 Doczy eta!.
`2006/0051880 A1
`2006/0166447 A1 * 7/2006 Doczy eta!. .................. 438/287
`2007/0262451 A1 * 1112007 Rachmady et a!.
`........... 257/758
`2008/0179714 A1 * 7/2008 Chou et al . .................... 257/635
`2009/0142899 A1 * 6/2009 Jensen eta!. .................. 438/287
`2009/0280631 A1 * 1112009 Gambino et a!.
`............. 438/588
`2010/0140717 A1 * 6/2010 Lavoie et al.
`................. 257/369
`FOREIGN PATENT DOCUMENTS
`2001267561
`9/2001
`
`JP
`
`OTHER PUBLICATIONS
`
`Chinese Patent Office, Office Action dated Mar. 29, 20ll, Applica(cid:173)
`tion No. 200910169144.9,9 pages.
`* cited by examiner
`
`Primary Examiner- Caridad Everhart
`(74) Attorney, Agent, or Firm- Haynes and Boone, LLP
`
`ABSTRACT
`(57)
`A method is provided for fabricating a semiconductor device.
`The method includes providing a substrate including a
`dummy gate structure formed thereon, removing the dummy
`gate structure to form a trench, forming a first metal layer over
`the substrate to fill a portion of the trench, forming a protec(cid:173)
`tion layer in a remaining portion of the trench, removing a
`unprotected portion of the first metal layer, removing the
`protection layer from the trench, and forming a second metal
`layer over the substrate to fill the trench.
`
`14 Claims, 7 Drawing Sheets
`
`NVIDIA Corp.
`Exhibit 1004
`Page 001
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 1 of7
`
`US 8,039,381 B2
`
`100
`\
`
`Fig. 1
`
`200
`\
`
`114
`
`Fig. 2
`
`NVIDIA Corp.
`Exhibit 1004
`Page 002
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 2 of7
`
`US 8,039,381 B2
`
`300
`\
`
`114
`
`117
`
`406
`402
`
`102
`
`Fig. 3
`
`114
`
`Fig. 4
`
`NVIDIA Corp.
`Exhibit 1004
`Page 003
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 3 of7
`
`US 8,039,381 B2
`
`600 \.,...
`
`Fig. 5
`
`FORM A DUMMY GATE STRUCTURE ON A SUBSTRATE
`+
`PERFORM A CHEMICAL MECHANICAL POLISHING (CMP)
`+
`REMOVE THE DUMMY GATE STRUCTURE TO FORM A TRENCH
`+
`DEPOSIT A FIRST METAL TO PARTIALLY FILL IN THE TRENCH
`+
`FORM PHOTORESIST LAYER OVER FIRST METAL LAYER
`+
`PERFORM AN ETCH BACK PROCESS ON THE PHOTORESIST LAYER
`+
`REMOVE A PORTION OF THE FIRST METAL LAYER
`+
`REMOVE THE PHOTORESIST FROM THE TRENCH
`t
`DEPOSIT A SECOND METAL LAYER TO FILL
`IN THE REMAINDER OF THE TRENCH
`+
`PERFORM A CHEMICAL MECHANICAL POLISHING (CMP)
`
`602
`
`604
`
`606
`
`608
`
`610
`
`612
`
`614
`
`616
`
`""-618
`
`620
`
`Fig. 6
`
`NVIDIA Corp.
`Exhibit 1004
`Page 004
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 4 of7
`
`US 8,039,381 B2
`
`700
`\
`
`Fig. 7
`
`700
`\
`
`114
`
`Fig. 8
`
`NVIDIA Corp.
`Exhibit 1004
`Page 005
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 5 of7
`
`US 8,039,381 B2
`
`702
`
`700
`\
`
`710
`
`702
`
`704
`
`114
`
`Fig. 9
`
`Fig. 10
`
`Fig. 11
`
`NVIDIA Corp.
`Exhibit 1004
`Page 006
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 6 of7
`
`US 8,039,381 B2
`
`700
`\
`
`702
`
`704 712
`
`114
`
`700
`\
`
`106
`
`106
`
`102
`
`Fig. 12
`
`102
`
`Fig. 13
`
`NVIDIA Corp.
`Exhibit 1004
`Page 007
`
`

`

`U.S. Patent
`
`Oct. 18, 2011
`
`Sheet 7 of7
`
`US 8,039,381 B2
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`700
`\
`
`740
`
`114
`
`Fig. 14
`
`Fig. 15
`
`NVIDIA Corp.
`Exhibit 1004
`Page 008
`
`

`

`2
`of the sidewalls of the gate structure and where the second
`metal layer is formed on another portion of the sidewalls of
`the gate structure.
`Yet another one of the broader forms of an embodiment of
`the invention involves a method for fabricating a semicon(cid:173)
`ductor device. The method includes providing a semiconduc(cid:173)
`tor substrate, forming a gate structure on the semiconductor
`substrate, the gate structure including a high-k dielectric and
`a dummy polysilicon gate, removing the durmny polysilicon
`10 gate to provide a trench in the gate structure, depositing a first
`metal layer over the substrate to partially fill the trench, form(cid:173)
`ing a photoresist layer on the first metal layer to fill a remain(cid:173)
`der of the trench, etching back the photoresist layer such that
`a portion of the photoresist layer protects the metal layer
`15 within the trench, removing the unprotected portion of the
`first metal layer, removing the portion of the photoresist layer
`from the trench, and depositing a second metal layer over the
`substrate to fill the trench.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Aspects of the present disclosure are best understood from
`the following detailed description when read with the accom(cid:173)
`panying figures. It is emphasized that, in accordance with the
`standard practice in the industry, various features are not
`drawn to scale. In fact, the dimensions of the various features
`may be arbitrarily increased or reduced for clarity of discus(cid:173)
`Sion.
`FIGS. 1-3 are cross-sectional views of a semiconductor
`30 device at various stages of fabrication in an embodiment of a
`gate last process.
`FIGS. 4 and 5 are cross-sectional views of a semiconductor
`device during metal deposition processes of an embodiment
`of a gate last process.
`FIG. 6 is a flowchart of an embodiment of a method of
`forming a gate including a gate last process according to
`various aspects of the present disclosure.
`FIGS. 7-15 are cross-sectional views of a semiconductor
`device of at various stages of fabrication according to the
`40 method of FIG. 6.
`
`DETAILED DESCRIPTION
`
`The present disclosure relates generally a semiconductor
`device and, more particularly, to a gate structure and method
`of forming a gate structure of a semiconductor device.
`As technology nodes shrink, in some IC designs, there has
`been a desire to replace the typically polysilicon gate elec- 20
`trade with a metal gate electrode to improve device perfor(cid:173)
`mance with the decreased feature sizes. Providing metal gate
`structures (e.g., including a metal gate electrode rather than
`polysilicon) offers one solution. One process of forming a
`metal gate stack is termed "gate last" process in which the 25
`final gate stack is fabricated "last" which allows for reduced
`number of subsequent processes, including high temperature
`processing, that must be performed after formation of the
`gate. Additionally, as the dimensions of transistors decrease,
`the thickness of the gate oxide must be reduced to maintain
`performance with the decreased gate length. In order to
`reduce gate leakage, high dielectric constant (high-k) gate
`insulator layers are also used which allow greater physical
`thicknesses while maintaining the same effective thickness as
`would be provided by a typical gate oxide used in larger 35
`technology nodes.
`There are challenges to implementing such features and
`processes in CMOS fabrication however. As the gate lengths
`decrease, these problems are exacerbated. For example, in a
`"gate last" fabrication process, voiding can occur when
`depositing a metal film into a trench to from the metal gate
`electrode. As gate lengths decrease, the trench also decreases
`in size, and depositing metal into the trench becomes increas(cid:173)
`ingly difficult, and increasingly likely to form a void.
`
`US 8,039,381 B2
`
`1
`PHOTORESIST ETCH BACK METHOD FOR
`GATE LAST PROCESS
`
`PRIORITY DATA
`
`This application claims priority to Provisional Application
`Ser. No. 61/096,633 filed on Sep. 12, 2008, entitled "Photo(cid:173)
`resist Etch Back Method For Gate Last Process," and to
`Provisional Application Ser. No. 61/109,317 filed on Oct. 29,
`2008, entitled "Photoresist Etch Back Method For Gate Last
`Process," both entire disclosures of which are incorporated
`herein by reference.
`
`BACKGROUND
`
`SUMMARY
`
`One of the broader forms of an embodiment of the inven(cid:173)
`tion involves a method for fabricating a semiconductor
`device. The method includes providing a substrate including
`a dummy gate structure formed thereon, removing the
`dummy gate structure to form a trench, forming a first metal
`layer over the substrate to fill a portion of the trench, forming
`a protection layer in a remaining portion of the trench, remov(cid:173)
`ing an unprotected portion of the first metal layer, removing
`the protection layer from the trench, and forming a second
`metal layer over the substrate to fill the remainder trench.
`Another one of the broader forms of an embodiment of the
`invention involves a semiconductor device. The semiconduc(cid:173)
`tor device includes a semiconductor substrate, a source and a
`drain region formed on the semiconductor substrate, and a
`gate structure disposed on the substrate between the source
`and drain regions. The gate structure includes an interfacial
`layer formed over the substrate, a high-k dielectric formed
`over the interfacial layer, and a metal gate formed over the
`high-k dielectric that includes a first metal layer and a second
`metal layer, where the first metal layer is formed on a portion
`
`The present disclosure relates generally to forming an inte-
`45 grated circuit device on a substrate and, more particularly, to
`fabricating a gate structure as part of an integrated circuit
`(including FET devices). It is understood, however, that the
`following disclosure provides many different embodiments,
`or examples, for implementing different features of the inven-
`50 tion. Specific examples of components and arrangements are
`described below to simplifY the present disclosure. These are,
`of course, merely examples and are not intended to be limit(cid:173)
`ing. In addition, the present disclosure may repeat reference
`numerals and/or letters in the various examples. This repeti-
`55 tion is for the purpose of simplicity and clarity and does not in
`itself dictate a relationship between the various embodiments
`and/or configurations discussed. In addition, the present dis(cid:173)
`closure provides examples of a "gate last" metal gate process,
`however one skilled in the art may recognize applicability to
`60 other processes and/or use of other materials.
`Referring to FIGS. 1, 2, and 3 illustrated are cross-sectional
`views of a semiconductor device at various stages of fabrica(cid:173)
`tion in a gate last process. The various stages of the device are
`illustrated as device 100, 200, and 300 respectively. One or
`65 more features, for example of the device 100, may be
`included in the devices 200 and 300 and remain substantially
`unchanged except as noted herein. The devices 100, 200, and
`
`NVIDIA Corp.
`Exhibit 1004
`Page 009
`
`

`

`US 8,039,381 B2
`
`3
`300 may be intermediate devices fabricated during process(cid:173)
`ing of an integrated circuit, or portion thereof, that may com(cid:173)
`prise static random access memory (SRAM) and/or other
`logic circuits, passive components such as resistors, capaci(cid:173)
`tors, and inductors, and active components such as P-channel
`field effect transistors (PFET), N-channel FET (NFET),
`metal-oxide semiconductor field effect transistors (MOS(cid:173)
`FET), complementary metal-oxide semiconductor (CMOS)
`transistors, bipolar transistors, high voltage transistors, high
`frequency transistors, other memory cells, and combinations
`thereof.
`The semiconductor device 100 includes a substrate 102.
`Formed on the substrate 102 are shallow trench isolation
`(STI) structures 104, source/drain regions 106 (including
`source/drain extension regions 108), a gate dielectric 110,
`contacts 112, a contact etch stop layer (CESL) 114, spacers
`116, a dummy gate pattern 118, hard mask layer 120, and a
`dielectric layer 122.
`In an embodiment, the substrate 102 includes a silicon
`substrate (e.g., wafer) in crystalline structure. The substrate
`102 may include various doping configurations depending on
`design requirements as is known in the art (e.g., p-type sub(cid:173)
`strate or n-type substrate) Other examples of the substrate 102
`may also include other elementary semiconductors such as
`germanium and diamond. Alternatively, the substrate 102
`may include a compound semiconductor such as, silicon car(cid:173)
`bide, gallium arsenide, indium arsenide, or indium phos(cid:173)
`phide. Further, the substrate 102 may optionally include an
`epitaxial layer (epi layer), may be strained for performance
`enhancement, and/or may include a silicon-on-insulator
`(SOl) structure.
`The shallow trench isolation (STI) features 104 formed in
`the substrate 102 may isolate one or more devices from each
`other. The STI features 104 may include silicon oxide, silicon
`nitride, silicon oxynitride, fluoride-doped silicate glass
`(FSG), and/or a low k dielectric material. Other isolation
`methods and/or features are possible in lieu of or in addition
`to STI. The STI features 104 may be formed using processes
`such as reactive ion etch (RIE) of the substrate 102 to form
`trenches which are then filled with insulator material using
`deposition processes followed by CMP process.
`The gate structure formed using the dummy gate pattern
`118 may be configured asP-channel or N -channel as is known
`in the art. The dummy gate pattern 118 is a sacrificial layer.
`The dummy gate pattern 118 may include polysilicon. In an
`embodiment, the dummy gate pattern 118 includes amor(cid:173)
`phous silicon. The dummy gate pattern 118 may be formed by
`MOS technology processing such as polysilicon deposition,
`photolithography, etching, and/or other suitable methods.
`The gate dielectric 110 may include a high dielectric con(cid:173)
`stant (high-k) material. In an embodiment, the high-k dielec(cid:173)
`tric material includes hafnium oxide (HfD2 ). Other examples
`ofhigh-k dielectrics include hafnium silicon oxide (HfSiO),
`hafnium silicon oxynitride (HfSiON), hafnium tantalum
`oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium
`zirconium oxide (HfZrO), combinations thereof, and/or other
`suitable materials. The semiconductor device 100 may fur(cid:173)
`ther include, various other dielectric and/or conductive lay(cid:173)
`ers, for example, interfacial layers and/or capping layers
`underlying the dummy gate pattern 118. In an embodiment, a
`capping layer (e.g., dielectric layer) is formed on the gate
`dielectric 110. The capping layer may adjust the work func(cid:173)
`tion of the subsequently formed metal gate. The capping layer
`may include a metal oxide (LaOx, MgOx, AlOx), metal
`alloyed oxide (BaTiOx, SrTiOx, PbZrTiOx), a combination
`thereof, and/or other suitable materials. In another embodi-
`
`4
`ment, a metal layer is formed on the gate dielectric layer. The
`overlying metal layer may adjust the work function of the
`subsequently formed gate.
`The spacers 116 may be formed on both sidewalls of the
`dummy gate structure 118. The spacers 116 may be formed of
`silicon oxide, silicon nitride, silicon oxynitride, silicon car(cid:173)
`bide, fluoride-doped silicate glass (FSG), a low k dielectric
`material, combinations thereof, and/or other suitable mate(cid:173)
`rial. The spacers 116 may have a multiple layer structure, for
`10 example, including one or more liner layers such as liner layer
`117. The liner layer 117 may include a dielectric material
`such as silicon oxide, silicon nitride, and/or other suitable
`materials. The spacers 116 may be formed by methods
`15 including deposition of suitable dielectric material and aniso(cid:173)
`tropically etching the material to form the spacer 116 profile.
`The hard mask layer 120 may include silicon nitride, sili(cid:173)
`con oxynitride, silicon carbide, and/or other suitable materi(cid:173)
`als. The hard mask layer 120 may be formed using methods
`20 such as chemical vapor deposition (CVD), physical vapor
`deposition (PVD), or atomic layer deposition (ALD). In an
`embodiment, the hard mask layer 120 is between approxi(cid:173)
`mately 100 and 500 angstroms in thickness.
`The source/drain regions 106 including lightly doped
`25 source/drain regions shown as regions 108 and heavy doped
`source/drain regions, are formed on the substrate 102. The
`source/drain regions 106 may be formed by implanting
`p-type or n-type dopants or impurities into the substrate 102
`depending on the desired transistor configuration. The
`30 source/drain features 106 may be formed by methods includ(cid:173)
`ing photolithography, ion implantation, diffusion, and/or
`other suitable processes. The contact features 112, coupled to
`the source/drain regions 106, may include silicide. The con(cid:173)
`tact features 112 may be formed on the source/drain regions
`35 106 by a salicide (self-aligned silicide) process. The contacts
`112 may include nickel silicide, cobalt silicide, tungsten sili(cid:173)
`cide, tantalum silicide, titanium silicide, platinum silicide,
`erbium silicide, palladium silicide, or combinations thereof.
`The contact etch stop layer (CESL) 114 may be formed of
`40 silicon nitride, silicon oxynitride, and/or other suitable mate(cid:173)
`rials. The CESL 114 composition may be selected based upon
`etching selectivity to one or more additional features of the
`semiconductor device 100.
`A dielectric layer 122 such as an inter-layer (or level)
`45 dielectric (ILD) layer may be formed overlying the CESL 114
`by chemical vapor deposition (CVD), high density plasma
`CVD, spin-on, sputtering, or other suitable methods. The
`dielectric layer 122 may include silicon oxide, silicon oxyni(cid:173)
`tride, or a low k material. In an embodiment, the dielectric
`so layer 122 is a high density plasma (HDP) dielectric.
`In a gate last process, the dummy gate structure 118 may be
`removed so that a resulting metal gate structure may be
`formed in place of the dummy gate structure 118. Accord(cid:173)
`ingly, the dielectric layer 122 may be planarized by a chemi-
`55 cal mechanical polishing (CMP) process until a top portion of
`the dummy gate structure 118 is reached as illustrated by the
`device 200 ofF I G. 2. Fallowing the planarization, the dummy
`gate structure 118 may be removed, providing the device 300
`of FIG. 3. For example, polysilicon is selectively etched
`60 removing the dummy gate structure 118. The selective
`removal of the dummy gate structure 118 provides a trench
`302 within which a metal gate may be formed. The dummy
`gate structure 118 may be removed using a wet etch and/or a
`dry etch. In an embodiment, a wet etch process includes
`65 exposure to a hydroxide containing solution (e.g., monium
`hydroxide), deionized water, and/or other suitable etchant
`solutions.
`
`NVIDIA Corp.
`Exhibit 1004
`Page 010
`
`

`

`US 8,039,381 B2
`
`5
`Referring now to FIGS. 4 and 5, an embodiment of forma(cid:173)
`tion of a metal gate is illustrated. FIG. 4 illustrates a device
`400 including metal gate materials deposited into the trench
`302. The metal gate materials may include one or more layers
`of material such as, liners, materials to provide appropriate 5
`work function of the gate, gate electrode materials, and/or
`other suitable materials. However, it has been observed that
`deposition of one or more layers required for the metal gate
`formation may provide incomplete filling of the trench 302.
`For example, a deposition of a first metal402 such as a metal 10
`liner and/or work function metal may provide an overhang
`404 at the aperture of the trench 302. The overhang 404 may
`result from the difficulties in filling a high aspect ratio trench.
`The subsequent deposition of metal layer 406 may form one
`or more voids such as, void 408, in the trench 302.
`Referring now to FIG. 5, a chemical mechanical polish
`(CMP) process is performed on the device 400 to provide the
`device 500 and form the metal gate 502. The device 500
`illustrates the metal gate 502 formed with the void 408.
`Accordingly, the void may increase a resistance (e.g. Rs) of 20
`the device. Though further CMP processing may reduce the
`void 408, for example, by reducing the gate height, this may
`cause other issues such as decrease of stress on the channel
`(e.g., disadvantageous reduction of stress for a strained
`device) and/or the performance of the transistor may be 25
`degraded. Therefore, FIGS. 4 and 5 illustrate disadvantages
`of a gate last process where the aspect ratio of a resultant
`trench provides for difficult deposition of material to partially
`or completely fill the trench.
`Referring now to FIG. 6, illustrated is a method 600 for 30
`fabricating a semiconductor device including the formation
`of a metal gate by a "gate last" process. Referring also to
`FIGS. 7-15 illustrated are cross-sectional views of a semi con-
`ductor device 700 at various stages of fabrication according to
`the method 600 FIG. 6. The semiconductor device 700 is 35
`similar to the semiconductor devices 100, 200, 300 of FIGS.
`1-3. Accordingly, similar features in FIGS. 1-3 and 7-15 are
`numbered the same for the sake of simplicity and clarity.
`The method 600 begins at step 602 where a semiconductor
`device including a transistor structure is formed. The transis(cid:173)
`tor structure includes a d=y gate structure 118. The
`dummy gate structure 118 may include a dummy polysilicon
`gate structure. In FIG. 7, the semiconductor device 700
`formed may be substantially similar to the device 100,
`described above with reference to FIG. 1.
`The gate dielectric 110 may include a high dielectric con(cid:173)
`stant (high-k) material. In an embodiment, the high-k dielec(cid:173)
`tric material includes hafnium oxide (HfD2 ). Other examples
`of HK dielectrics include hafnium silicon oxide (HfSiO),
`hafnium silicon oxynitride (HfSiON), hafnium tantalum
`oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium
`zirconium oxide (HfZrO), combinations thereof, and/or other
`suitable materials. The semiconductor device 100 may fur(cid:173)
`ther include, various other dielectric and/or conductive lay(cid:173)
`ers, for example, interfacial layers and/or capping layers 55
`underlying the dummy gate pattern 118.
`The method 600 proceeds to step 604 where a chemical
`mechanical polishing (CMP) process is performed. In FIG. 8,
`the CMP process may planarize the device 700 and expose the
`dummy gate structure 118. The resultant device 700 may be 60
`substantially similar to the device 200, illustrated above with
`reference to FIG. 2.
`The method 600 proceeds to step 606 where the d=y
`gate structure is removed. In FIG. 9, the removal of the
`dummy gate structure 118 may provide for a trench 302 (e.g.,
`aperture in the substrate) within which a metal gate may be
`formed. The sidewalls and bottom of the trench 302 may be
`
`6
`coated with a liner layer 117. In an embodiment, the liner
`layer 117 may be Si02 , SiN, SiON, and/or other suitable
`material. The liner layer 117 may be included in a spacer
`feature.
`The method 600 proceeds to step 608 where a first metal
`layer is deposited to partially fill in the trench. In FIG.10, the
`metal layer 702 deposited may be any metal material suitable
`for forming a metal gate or portion thereof, including work
`function layers, liner layers, interface layers, seed layers,
`adhesion layers, barrier layers, etc. The metal layer 702 may
`include one or more layers including Ti, TiN, TaN, Ta, TaC,
`TaSiN, W, WN, MoN, MoON, and/or other suitable materi(cid:173)
`als. The metal layer 702 may be formed by PVD or other
`suitable processes. Examples of metals that may be deposited
`15 include P-type metal materials and N-type metal materials.
`P-type metal materials may include compositions such as
`ruthenium, palladium, platinum, cobalt, nickel, and conduc(cid:173)
`tive metal oxides, and/or other suitable materials. N-type
`metal materials may include compositions such as hafnium,
`zirconium, titanium, tantalum, aluminum, metal carbides
`(e.g., hafnium carbide, zirconium carbide, titanium carbide,
`aluminum carbide), aluminides, and/or other suitable mate(cid:173)
`rials. The deposition of the metal layer 702 may provide an
`overhang 704 at the aperture of the trench 302. The overhang
`704 may result from the difficulties in filling a high aspect
`ratio trench.
`The method 600 proceeds to step 610 where a photoresist
`layer is formed over the first metal layer. In FIG. 11, the
`photoresist layer 710 may be formed on the metal layer 702
`by a spin-coating process. Accordingly, the photoresist layer
`710 is able to fill in the remainder of the trench 302 even with
`the presence of the overhang 704. Further, a soft-bake process
`may be performed on the photoresist layer 710 to evaporate
`the solvent from the photoresist layer 710.
`The method 600 proceeds to step 612 where an etch back
`process is performed on the photoresist layer. In FIG. 12, a
`photoresist etch back process may be performed to remove a
`portion of the photoresist layer 710 and the process may stop
`at the metal layer 702. Accordingly, a photoresist layer 712
`40 still remains in the trench 302 to protect the metal layer 702
`within the trench. It should be noted that the photoresist layer
`710 is not patterned by exposure but used for the etch back
`process.
`The method 600 proceeds to step 614 where an etch pro-
`45 cess is performed to remove a portion of the first metal layer.
`In FIG. 13, the etch process may include a wet etch process
`that selectively removes portions of the metal layer 702 (e.g.,
`work function metal pull back) that are not protected by the
`photoresist layer 712. The overhang 704 and portions 720,
`50 722 of the metal layer 702 at the aperture of the trench 302
`may be removed the etch process. Thus, a metal layer 730
`(work function metal) still remains at the bottom and on part
`of the sidewalls of the trench 302.
`The method 600 proceeds to step 616 where the photoresist
`layer is removed from the trench 302. The photoresist layer
`712 remaining in the trench 302 may be removed by an etch
`process or other suitable process. For example, a developer
`may be used to remove the photoresist layer 712 since the
`photoresist layer (e.g., negative type photoresist) has not been
`exposed, and thus can be dissolved by the developer.
`The method 600 proceeds to step 618 where a second metal
`layer is deposited to fill in the remainder of the trench. In FIG.
`14, a fill metal layer 740 may be deposited to substantially or
`completely fill in the remainder of the trench 302 including
`65 the work function metal 730. The fill metal layer 740 may
`include, tungsten (W), aluminum (AI), titanium (Ti), titanium
`nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt
`
`NVIDIA Corp.
`Exhibit 1004
`Page 011
`
`

`

`US 8,039,381 B2
`
`8
`plated that other polymeric materials may be used since an
`exposure process is not required for the etch back process.
`Therefore, the claims should be interpreted in a broad man(cid:173)
`ner, consistent with the present disclosure.
`
`20
`
`7
`(Co), copper (Cu), nickel (Ni), combinations thereof, and/or
`other suitable materials. The fill metal layer 740 may be
`deposited using CVD, PVD, plating, and/or other suitable
`processes. It should be noted that some of the fill metal layer
`7 40 may be formed on the sidewall of the trench 3 02 at the top
`surface. Accordingly, the metal gate structure may include a
`length (measured along the channel length) that is greater at a
`top surface (away from the substrate) as compared to a length
`at a bottom surface (near the substrate).
`The method 600 then proceeds to step 620 where a chemi- 10
`cal mechanical polish (CMP) process is performed. In FIG.
`15, the CMP process planarizes the semiconductor device
`700. The planarization may remove the fill metal layer 740
`deposited outside of the trench structure 302. The CMP pro(cid:173)
`cess provides the semiconductor device 700 with a metal gate 15
`structure 750. Further, the metal gate structure 750 may be
`substantially free of voids. The gate structure may include the
`work function metal 712, the gate fill metal material740, and
`the gate dielectric layer 110 (including an interfacial layer and
`capping layer).
`In embodiments, the method 600 may continue to include
`process steps such as deposition of passivation layers, forma(cid:173)
`tion of contacts, interconnect structures (e.g., lines and vias,
`metal layers, and interlayer dielectric that provide electrical
`interconnection to the device including the formed metal 25
`gate).
`Thus, the method 600 and the semiconductor device 700
`illustrated in FIGS. 7-15 may provide for improved formation
`of the metal gate for example, including minimizing and/or
`eliminating the formation of voids such as provided by the 30
`semiconductor devices 400 and 500 illustrated in FIGS. 4 and
`5 respectively. Accordingly, device performance and reliabil-
`ity is improved with the method 600.
`In summary, a gate last process may be implemented to
`form metal gate structures. Problems with forming the metal 35
`gate structure may be reduced by removing the overhang of a
`metal film at the aperture (e.g., top opening) of the trench
`prior to depositing a metal filler layer in the trench. In par(cid:173)
`ticular, a photoresist etch back process may be performed to
`protect the underlying metal film in the trench. The overhang 40
`and other portions of the metal film that are not protected by
`the photoresist may be removed by a etch process. Accord(cid:173)
`ingly, a subsequent metal filler layer that is deposited may
`easily fill in the trench completely to form the metal gate
`structure. Thus, the risk of forming voids in the metal gate 45
`structure is reduced and/or eliminated even as device features
`continue to shrink in advanced technology nodes (e.g., 45 nm
`and below). Further, a height of the gate is precisely con(cid:173)
`trolled by the methods disclosed herein without having to
`overpolish (by CMP) to remove the overhang and decrease 50
`the poly gate height. It is understood that the embodiments
`disclosed herein offer different advantages, and that no par(cid:173)
`ticular advantage is necessarily required for all embodiments.
`Accordingly, the present disclosure provides a device and
`method that includes a modified trench structure that prevents 55
`or reduces the risk of incomplete formation of a metal gate in
`a gate-last process. While the preceding description shows
`and describes one or more embodiments, it will be understood
`by those skilled in the art that various changes in form and
`detail may be made therein without departing from the spirit
`and scope of the present disclosure. For example, although
`the methods implements a "gate last" approach, the methods
`disclosed herein may be used in a hybrid process in which one
`type of metal gate is formed in a "gate first" process and the
`other type of metal gate is formed in a "gate last" process. 65
`Further, although a photoresist material is disclosed herein to
`protect the bottom metal in the trench, it has been contem-
`
`What is claimed is:
`1. A method of fabricating a semiconductor device, com(cid:173)
`prising:
`providing a substrate including a dummy gate structure
`formed thereon;
`removing the dummy gate structure to form a trench;
`forming a first metal layer over the substrate to fill a portion
`of the trench, wherein the first metal layer includes an
`overhang at an aperture of the trench;
`forming a protection layer in a remaining portion of the
`trench, wherein the protection layer fills the remaining
`portion of the trench, and wherein the forming the pro(cid:173)