Raytheon2026R-0001
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`Sony Corp. v. Raytheon Co.
`IPR2015-01201
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`Library of Congress Cataloging-in-Publication Data
`Silicon VLSI technology
`p.
`cm.
`ISBN 0—13~085037—3
`1. Integrated circuits—Very large scale integration—-Design and
`construction.
`2. Silicon.
`3. Silicon oxide films,
`4. Metal oxide
`semiconductors.
`5. Silicon technology.
`TK7874.75.S54
`2000
`621.39'5—dc21
`
`99-42745
`CIP
`
`Publisher: Tom Robbins
`Associate Editor: Alice Dworkin
`Editorial/Production Supervision: Rose Kernan
`Vice President and Editorial Director, ECS: Marcia Horton
`Vice President of Production and Manufacturing: David W. Riccardi
`Executive Managing Editor: Vince O’Brien
`Marketing Manager: Danny Hoyt
`Managing Editor: David A. George
`Manufacturing Buyer: Pat Brown
`Manufacturing Manager: Trudy Pisciotti
`Art Director: Jayne Conte
`Cover Design: Bruce Kenselaar
`Editorial Assistant: Jesse Power
`Copy Editor: Martha Williams
`Composition: D&G Limited, LLC
`
`©2000 by Prentice Hall, Inc.
`Prent}iIceH
`/_“\ Upper Saddle River, New Jersey 07458
`
`All rights reserved. No part of this book may be
`reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`The author and publisher of this book have used their best efforts in preparing this book. These efforts include the
`development, research, and testing of the theories and programs to determine their effectiveness. The author and
`publisher make no warranty of any kind, expressed or implied, with regard to these programs or the documentation
`contained in this book. The author and publisher shall not be liable in any event for incidental or consequential damages
`in connection with, or arising out of, the furnishing, performance, or use of these programs.
`
`Printed in the United States of America
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`ISBN U-1:3-EIBEDB7-3
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`Prentice Hall International (UK) Limited, London
`Prentice Hall of Australia Pty. Limited, Sydney
`Prentice Hall Canada Inc., Toronto
`Prentice Hall Hispanoamericana, S.A., Mexico
`Prentice Hall of India Private Limited, New Delhi
`Prentice Hall of Japan, Inc., Tokyo
`Pearson Education Pte., Ltd. ,Singnpore
`Editora Prentice? Hall do Brasil, Ltda., Rio de Janeiro
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`2.2 cuos Process Flow
`1VmtypicaICMOScirmilsateshowninF|gurc2-1.1hcsimplcinvenctdrafit
`-
`ld'twasdescn'bodinChaptctl.'hneNORgateonthcIightillIntraleshow -
`'
`NMOSandPwlosdevioescanbeaddedlotheinvenetcixuxittorealizemomc
`Iognc
`
`implemcntsthe NOR
`thalcanintcgnIcNMOSandPMOSdcvioesonIhesamcch.ip.Infacl,many
`technologiesalsoimplemcnt vnflounstypcsofresistorxcnpacitoruhhnfilm
`andperhapsmhertypesofdevicesaswcllwcwiflfimitomdisassionhetctothe
`basicdcvioesanddcsm'beawdmologytobuildthem.Ex1ensionsolthist -_..
`include other oomponentsarereasonably straiglnforwanlandwcwillsecsome
`‘
`plesofsuchenensionsinlawrduptem
`TheendtvesultoftheprocessflowwcwilldiscnsisshowninFnguxe2—2.1‘ofa '
`aslructurclikethisxwcv/illtindthal16photoIilhographystcpsandwellover100'_
`vidua1pmoessstcpsarerequiIed.1hcfinalintegra1edcircuiImnyconlain --'
`~
`oomponcntslikethoscs|1owninthc6guze.cacholwhichmus1wortoonectly.
`11:crearetwoac(ivedcvicetypesshownin\hefigmve.ou1espoodingloIhose
`quitedtoimplementthecircuitsinF1gure2-l.1'hcindividua|soumc,dnin.andgue_
`'
`oftheNMOSandPMOSdevioesareidenIifiableinthecmsssection.ln
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`parts of the structure provide multiple wiring levels above the active devices to inter-
`connect them to perform particular circuit functions. Finally. some regions are included
`simply to improve the performance of the individual devices by doc:-using parasitic re-
`sistances or improving voltage ratings As we proceed through the steps required to
`build this chip. we will discus each of these points in greater detail.
`
`‘me Beg’nniag—(:hooaing a Substrate
`Before we begin actual water tnbrication,we must of course choose the starting wafers.
`In general this means specifying type (N or P).resistivity (doping level),crystal orienta-
`tion. waler ze. and a number ofother parameters having to do with water flatness. trace
`impurity levels, and so on.The major choices are the type. resistivity, and orientation.
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`Figure 2-2 indicates that the final structure has a P-type
`tegratedcireuiu.the substrate has a moderately high resistivity (25-50 flcm) which
`o
`to a doping level on the
`
`‘
`
`p
`
`-_
`cm" near the wafer surface. In order to
`are on the order of 10" -
`manufacture such wells. the background doping (the substrate doping in this -
`needs tobe signifiatntly lessthan thewell dopingllhtsthe substrate dopingisn -
`chosen to be on the order oi 10"‘ em".
`'lheobservantreadermightnoticethattheNMOSdeviceoouldaetuallybebv
`rectlyinthePsubstratewithoutaddingthePwellnearthesurfacelnfactthisis --
`the way the structure was sketched in figure 1
`cuits are actually built this way today,
`'
`much more common because the dopi
`plantation) is much better controlled in man
`Also,since the Pwelland N well doping coneentra'
`icr to start with a much more lightly doped substrate and tailor the wells for the
`and PMOS devices individually.
`‘lhe observant reader might also note in Figin-e 1-34 that a substrate consisting
`Player on a P‘ substrate was illustrated.'Ihis is one of the technology options we
`consider later in Section 2.25.
`a
`The only other major parameter we need to speeily in the starting substrate -
`crystal orientation. We will discuss crystal structure in more detail in Chapter 3.
`‘_
`ever. virtually all modern silicon integrated circuits are manufactured today '
`wafers with a (100) surface orientationflhe principal reason for this is that the
`ties ot the Silsioz interface are significantly better when a (too) crystal
`used.We
`discuss the reasons for this in detail in Chapter 6, but the key idea is that the e -~
`'
`'
`terface are intimately connected with the atomi
`'
`when an Si02 layer is thermally grown on Si. It is f :4
`perimcntally that there are fewer imperfections (unsatisfied bonds) on a (lw)
`~
`thanisthecaseon othersilieonsurfaceaPrirnarilyforthisrveason.wewill
`(100) surface orientation for our starting wafers
`We will akodiscusin Chapter4sotnepl7ocesingwhich ‘soften doneonthe
`ing substrates before any actual device fabrication is begun.’lhis procesing is - '
`. M
`minimizing the sensitivity ofthe wafers totrace contaminants that can be in . .
`I
`the wafers during the many manufacturingsteps they go through to build circuits.
`preliminary proctming steps are called gettering and the most common process --
`is known as “intrinsic gettcring." Since these steps are not essential to the device »
`cation process, we will deter disctmion of them to Chapter 4.
`
`4
`
`2.2.2 Active legion Formation
`Modern CMOS chips integrate millions of active devices (NMOS and PMOS) '-
`side ina common silicon substrate. Cireuitsaredasignedwith these devices to‘
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`Generally this deposition is done below atmospheric pressure because this -
`better uniformity over larger wafer lots in the deposited films. Pumps are normally V
`on the furnace exhaust to reduce the pressure. Systems in which such depositions
`done are usually called Low-Pressure Chemical Vapor Deposition (LPCVD) :
`~
`-
`We will discuss them in more detail in Chapter 9.
`Thenitride layersdepositedbysueh macltinrsarenormally highlystreseiwith
`Si;N. under tensile stre$.'lhis produces a large compressive stress in the unde
`~
`substrate which can lead to detect generation ifit isnot carefully controlled In
`-
`major purpose of the Si0z layer under the Sla.Ne '3 to help relieve this sues. SiO:
`are under compressive stress when they are thermally grown on Si and if the -
`nessesottheSi0;andSi;N.layersareproperlychosen.thestressesinthetwo
`can partially compensate each other. reducing the stresses in the Si substrate.'Ihe -
`nesses chosen above do this
`The final step in Figure 2-3 is the deposition of a photoremst layer in prepara ' - =
`masking. Since photoresists are liquids at room temperature, they are normally :~
`-
`spun onto the wafers. The resist vbcosity and the spin speed determine the final
`thicknesstwhich is typiatlly about I run (Note that the dimensions in all the dra "
`in this book are not exactly to sale. since the photoresist layer in Figure 2-3 is —
`more than l0 times the thickness of the oxide or nitride layers. and the substrate is
`ieally 500 times as thick as the photoresist |ayer.'lhe liberties we talte with sale in v
`drawings are intended to improve clarity.)
`After the photoresist is spun onto the water. it is usually baked at about l00°C in
`der to drive off solvents from the layer.'lhe resist is then exposed using a mask. *'
`defines the pattern for the LOCOS regionsflhe photolithography process is both - T
`plex and expensive and was illustrated conceptually in Figure l—9. We will describe A
`much greater detail in Chapter 5.'lhe machines which aceomplhh the exposure .
`-
`ten called "steppers" becatse they usually expose only a small area of the water -
`~
`each exposure and then “step” to the next adjacent field to expose. Such machines -
`be capable today of printing lines on the order of 150 nm (0.25 pm) and placing ‘A
`patterns on the water with an accuracy which is < 1!!) nm.‘lhey typically cost ’
`million dollars
`n
`The photoresists themselves are complex hydrocarbon mixtures. The actual
`violet (UV) lightsensitive part ol the resist is only a portion of the total mixture. In
`case of a positive resist. which is the most common type today. the molecule in - ,
`sist which is sensitive to light. absorbs UV photons and changes its chemical .
`-«
`in response to the light.'lhe result is that the molecule and the resist itself then - '
`in the developing solution. Negative resists also respond to UV light but become :-
`uble in the regions in which they are exposed. Figure 2-4 shows our CMOS wafer
`the resist has been exposed and developed.
`An additional step is also ilhtstrated in Figure 24. After the pattern is defined in
`resist. the Si.xN. is etched using dry etching. with the resist as a ma.slt.'l1tis is usually
`complished in a fluorine plums. We will discuss dry etching in Giapter 10. but a
`cal reaction might involve the generation of F atoms in a plasma. using a CF. or NH‘
`source and a reaction of the following type:
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`AswasthecaseintheL0O0Sprooes.thefunctionoftheniuidelayeristob --
`oxidationlmmoecuning wherever the SisN.'spresent.'Ihe underlying oxideand _,
`liefproblem Poly-buffered L 0
`
`polysilieon layer permits these changes
`which would otherwise cause defects to form in the silicon substrate during the
`oxidation. The polysilicon is deposited in an LPCVD machine similar to the -u «
`scribed for SixN4 in connection with Eq. (2.1). except that only one reactant gs -
`tnining silicon is used (Si!-I4 or SiHzClz. for example). A poly thickness ofabout 1 v
`2 _
`
`moredetailinChapter6and use numerical simulation tools tostudytheexaet ‘
`‘
`more carefully.The oxidation extends under the nitride edge because the oxidant
`candiffutcsidewaysaswellasvertianllythroughthepadoatidelayentoreachthe '
`surface where it reacts togrow $02. In fact.the nitride layerwill bend upan oxide _
`I
`
`that '5 lost to this encroachment
`The answer to the question we posed then is that the combination ot a thi - «
`tride. a thinner pad oxide which provides & of a pathway for lateral oxidant - ' -
`--
`and a polysilieon layer which itselfcan oxidize along its edges during LOCOS pr -
`a much sharper transition between the oxidized and unoxidinod regionsflhis all -
`tighter design rules and higher device density.
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`allows physically smaller isolation regions to be formed.
`The process begins the same wa
`thermally grown and
`'
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`problems later in oxidizing very sharp cor-
`ners and to avoid electrical effects usocialed with very sharp comer: Thus the etch
`
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`SiISiOz interface
`theprooessvrillalsohelpto round
`interface results from the lower electrical charge deties that themul oxi «-
`produce. The corner rounding results from the Viscoelastic [low properties at"
`high temperatures. We will discuss these ‘ssues in Chapter 6.
`The next step. illustrated in Figure 2-8. is the deposition of a thiclt SiO:
`chemical vapor deposition. It is important here that the filling process not leave‘
`voids in the trenchcsvdiich could happen ilthe deposition closed the top
`trench before the bottom pans were completely filled.A number of deposition _
`exist which do a good job of filling stnictures like this. One example is a
`Plasma or HDP system. which could be used in this application. We will
`systems in (ltapter 10.
`The final step in the ST! proces '3 illustrated in figure 2-9. This involves 1
`polishing the excess Si0; off the top surface ofthe wafer. leaving a planar
`Si0; filled trenches. 'lhis polishing process uses a technique known as I-
`Mcchanical Polkhing or CMP. which we will discuss in Chapter II since the
`t-
`tnon use of CM!’ today is in baclt—eud procesing, In this process. the wafer is
`face down in a polishing machine and the upper surface is literally polished flat _
`high-pH silica slurry. While this proces sounds crude compared to the sop ~
`procesing techniques generally used to fabricate chips. CMP has been found
`extremely well and it has found widespread application. he nitride layer -
`polishingstopandoncetheCMPopcration iscornpletc,the Siublacanbee
`moved as in the LOCOS process described earlier.
`At this stage, the wafers are ready for device fabrication in the active
`comparison ol Figures 2-5 and 2-9 illustrates both the similarities and the di
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`ht‘.-‘awn
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`in LOCOS and STI. Bolh proocsmes produce thick SiO: regions laterally
`jaocnt device structures. However the STI process produces more
`because there is very little lalcral c
`active regions
`
`gions compared to LOCOS.
`that when device geomcui
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`m Cluplcrzflnthnoloslcdlnolon
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`ellectsassodatedwithdtecomcrsofutetrencheswhichatnatfectdeyioe'
`These ksues have now been largely solved with new processes and new rnanufn --
`equipmcnnwiththeresultthatS’I'lisnowbcginningtoheusedinmanufacturing.
`hcrent density advantage over LOCOS suggests that S’l‘l will dominate in the
`
`x
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`2.2.4 N and P Well Formation
`We now return to our CMOS process now and we will pick up the LOCOS ' o
`technology wherewelelt it in Figure2—5. lfSTlwereusedasthe isolationproom
`steps below would be largely unchanged. We would simply use the cross section in .
`ure 2,-9 rather than Figure 2-5 as our starting point to continue the process flow.
`In thefinaldevioe crossection inl-'rgur'e2-zaheactivedevicesare shownin P-
`.
`N-type wells.'l‘hese wells tailor the substrate doping locally to provide optimum -
`~ ’
`characteristics The well doping affects device characteristics such as the MOS
`tor threshold voltage and I-V characteristics and PN junction capacitanccs. For -— ~’
`ple. recall in Chapter l.Eqs (1.23) — (l.25) which describe the elearieal -
`- » ‘
`PNdiodesand notioethcpresenoeolthedopinglevelsNnandN.4inthesee u w»
`'lhc steps required to form the P and N wells are illustrated in Figures 2-10 to 2- —
`In l’-‘tgure 2-10. photoresist isspun onto the wafer and mask 2 is used to expose
`resist andtodelinethe regionswherve Pwcllsarctobeformed.'l‘hePrvegionsare-
`ntcd by a process known as ion implantatiomwhieh we willdiscusin Chapter8.
`machines which perform this step are really small linear accelerators. A source cl
`ion to be implanted (boron in this use) is provided, tsually from a gas.
`'-<-
`charged ions (B‘) are formed byexposingthc source gastoan an-cdischarge.'l1te'
`
`_
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`Once the boron implant is complete, we are finished with the photoresist and
`thenstrippedeitherchemieallyorinanOzplasma.l'hotoresistandmzsk3are
`teed as shown '11: Figure 2-11 to define the regions where N wells will be placed ‘a’
`silioon.'llte process is identical to that just desenhed for the P wells except that in
`case an N-type dopant, phosphorus is implanted.'lhe energy of the phosphorus ' »
`- -v
`is again chosen to penetrate the oxide layers but not the photoresist. Phosphonis
`heavier atom than boron (atomic mas - 31 versus I l),so a higher energy is req
`to obtain an implant to the same depth into the silicon. In this situation an en
`3(l)—4(I)keVwouldbedtosen.Thedoseolthephosphorusimplantwou1dt -vi» '
`
`’
`
`stepintheprooessistodifiusethePandNwellstoajunctiondepthoftypically~
`microns. as illustrated in Figure 2-12. Boron and phosphorus have esentially ma
`dilfusion coefiicientsandsotheywill produce wells with about thesamejunction ~
`when they are simultaneously diffused. 'll:e other N-type dopants, arsenic and
`many. both have much smaller diffusion ooellicients and so for the prone: - -«~-
`here, the N well would be much shallower than the P well. which is not desired it
`want matched NMOS and PMOS characteristics. Another issue with arsenic and
`mony in the particular step in the process is that they are much heavier atoms
`phosphorus and hence would require much higher implant energies
`After the phosphorus implant, the photoresist is removed and the wafers
`cleaned.1'hey are next placed in a drive-in furnace. which diffuses the wells to a 't
`lion depth 01 2-3 microns (Figure 2-12). (Actually the depths they reach in this step
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`the well difiusion occurs dur-
`typical thermal cycle mightbe4to6hoursat l0(X)to
`ll00°C. Dillusion coellicients increase exponentially with temperature as we will see in
`
`3 point. The well drive-in step also repairs
`the damage from the implants. restoring the substrate crystallinity.
`
`7!r-ocessoptionsforarxivelegionadwelllionnaion
`At this point we have completed the
`the active devices. There are nun
`
`generalwewillnotcomiderverymanyolthae
`there aresimplytoo manytoconsiderina 6nitcchap-
`ter. Also our purpose here is not to explore all options but simply to give the reader a
`sense of what an integrated proces now looks like. However in addition to the STI op-
`tion we considered earlier. there are several other options that are very commonly used
`in industrial manufacturing which will be useful for the reader to understand before
`reading later chapters Two such options are explored briefly in this section before we
`return to our CMOS prom flow as it is shown in Figure 2-12.
`
`I: field Implants nrler LOCOS ltefions
`The firs: procem option relates to the field oxide or LOCOS regions which provide lat-
`eral eleetrical isolation between adjacent devices. In the process now we have described
`to this point. the implant energies of the P and N wells were
`trate through the thick field oxide so that the substrate doping was increased under the
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`LOCOS reybnslnprlctioethisisnotas
`anednracterizedbyarangedistn'butionnot
`stoppingprocess'$statisticalinnature.weshottldexpectsuch
`_
`8exploresthisideainmoredetail.butlorourpurposesheteweneedonlyto
`‘V
`standthattheenfireimphntdosecannmbepheedinthesifioonundetthefield -
`in Figures2—10and2-ll.lfwe triedtodothimheimplantenergywouldhavetobe '
`encased significantly to make certain that the shallowest ions went far enough to _
`throughthefie|doadde.Btntheproblemwouldthenbethatthedeepestions V
`-~
`likely penetrate thnoughthe masking photonesist lnyensotheptoeesas illustnted
`Figures 2-10 and 2-11 is somewhat sensitive to layer thicknesses and to implant
`« - '
`Thisdoesnotmeantlutitistoosensitivetobeusedinmanufneturingmutitdoes -I '
`that alternatives are olten used.
`Oneoommon alternative isillustnled in Figure: 2-13 to 2-lS.In thisptoees I j
`the field region dopingisaceomplishecl fight afietthe stepsshown in 1'-"tgure2-4.bef
`theLO0OSoxideisgrown.1husnlow-enetgybomnimplnntcanbettsedwhidiis -~
`V
`'slISi3NJSi0z stack.This is illustrated in Figure 2-13. '
`-
`.mostoltheborondiflmesaheadotthegrowingSiO:._
`ating the P regions shown in Figurez-14. Some ofthc boron is actually I» --
`--A ~-
`intothcgtowingsiozandisthercfoue“lost"tromthesilieon.1hcfractiono(the
`:~
`thatislosteanbeeasilyca|culated.aswewi1lseeinlaterdupters.Forol:vious
`theimplnntinfigure 2-13-isofien mlledthe field implant. It incneasesthel’-type - '
`inginthesuhsuatevrherewedonotwanttobuildactivedevicuAtypieal6eld'
`- ‘
`tnightbel ><10"‘un"B' at50keV.1'hisimplantenetgywouldeasilypmthmngh"
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`fimblfitshtfl‘ bI1l'n1|lyu's.AIIB‘ filudoputhedllconloallg.
`
`Thepmoesstepsneededtoinooc-potateburicdla)-ersareshowninF‘tgures2—
`2-Zlflttesestepsaneincorponted althcvcI'ybeginningoftheprocessf|ow,for «-
`thatwillbecomeobviousshonly.
`WebeginwiththestmctureinFigurez-3.‘lhefirstmaskisusedasshownin -,
`2—16lodefinetheregionswltet'eanN’buriedlayerwillbeformed.AnAs'im M
`then petfonnedsinoe the purpose hen: is to create a low-resistance negionmvc
`went the N‘ layettobefairly hcavilydopedandsoahigh-doseitnphnlonthe o
`10”cIn"wouldbeuscd.'Iheenet'yisnotailicalsolongasitissufficicntto
`ate the As’ through the thin SiO; layer. A reasonable enety would be 50 keV.
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`-
`--
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`otwhoccllw
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`(when we are finished).
`typedopant that diffuses
`thcrcouldbcused,butAs
`
`Installed in Figure 2—l7.Fust.itdrivcsin thc N‘
`u.m.Soeond.partofthcdrive-ixfsdoncinan
`-
`'
`ttnicksiozlayeroutbewalcrsurfaoahmonly
`ingprovidedbytheSi;N.laycr.WcwillsecthatusingaLOCOSprooessinthisappli-
`and?’ bnricdlaycrstobedcfinedwithasinglemask,andit
`
`’
`
`.
`
`'
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`the silicon surface at the edges
`silioou.‘l'his step in the surface
`
`strippedfflte next step is ion
`implantation ofthe P‘ buried layer,illustrated in figure 2-18. Here theself-aligning fea-
`ture in the two buried layers becomes:
`ers blocks the P‘
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`btiedaIaiqrmIl''lIyeu.‘lheP‘lnlledhyu'is
`
`Iayenlnthe P’ buriedlayercase,alowerdoseisusuallyused,becauseboronhasa -~
`higherdiffrsivitythanarsenicandinordertokeepitfromdiflusingtoofarduring -_
`sequentprocessingthebomneoneenu-ationnecdstobekeptlowerthanthe
`~
`concentration.Adoseolabout l0"crn" rnightbetypical.Afterthe P‘ irnplant,a -.
`temperaturedrive-inwonldbedonetoditfnsetheboron(andthearsenic)deeperT
`dIesubarueNoaddifiomloxidafionismqtd:edatthispointwflndrive-inmufl,
`doneinaninerl(N;orAr)ambicnLAtypialfumaceqclcItthispoinlmightbe _
`era] hours at 1000- 1l00°C. resulting in the structure shown in figure 2-19.
`The active devices need to be fabricated in much more lightly doped wells -
`providcdbythese buried layer regionsinorderto have the correct electrical
`-
`tiesAs a result.we require moderately doped Pand N regions above theburied
`ers. These more lightly doped layers reduce the junction capacitance: in the - - . "
`transistorsandarealsoimportantinsettingdeviceparameterssuchasflost _
`old or turn-on voltage. In principle we could counterdope the surface regions of
`buried layers with opposite type dopants to produce these regions. but this is » :
`manufacturable technique.This is easy tosee ifwe imagine trying tocoun « -
`- --
`1.0 x10"cm"N‘buried|ayertolorntal.0 X l0“an"Nlayer.'lhiswould
`v
`0.999 x 10" an" P-type counter doping. No doping technique available today ~
`vides this degree of precision.
`Fortunately there is an alter-native.a process called epitaxy.'lhe oxide layeron
`surfaceolthewaferinFIgtn'e2—l9islirststrippedinanI-lFsolution/Ihisacidis '_
`sclectivetoSiO:merSLAfierckanhg.thewafersuethenplacedmmmepita:dal
`actorwhich heatsthe waferstoternpcratures on theorderof800- l000°Cand
`them toagasambientcontainingsi andannallconcentrationofdoparmsiflg
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`_
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`hyerlsa"qrpedollIku\':i:radaep'tIIHl1)u'ls§uip-nun
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`largely inert ambient because no additional surface oxidation is needed at this - -
`Note that the incorporation of the buried and epitaxial layers into the structure ’
`only required one additional mask (but many process steps! ). As was the case in
`2-12, the substrate as shown in Figure 2-2] is now ready for aaive device fabrica '
`The step in the surface shown in Figure 2-20 would still be present in Figure 2-21 ‘
`is not explicitly shown.
`Finally. the structure shown in Figure I-34 is yet another variation on these
`steps structure incorporates a P‘ epitaxial layer and an N well using steps -1 -r
`to those described above.1he process flow in thiscase is left asan exercise tor
`reader. (Sec Problem 2.1.)
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`_ Gfillortnation
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`Olmhneuflw
`
`wenowreturntothemainpmcessflorwandFigure2—l2.lfeitheroftheprocessoptions
`describedaboveweretobe usedthesuhstratewouldappearasshownin Figurez-15
`or2-2l.buttheprocessflowfromthispointonwouldbesuhstantiallythesamesofor
`simplicitymnewilleontinue the prooessdeseriptionwithF1gure2—l2.
`Thenextseveralstepashownin l'-'igures2—22to2—26aredesigned tofortnelitieal
`pansofdIeMOSdevicesPtohablythesingkmostimponantparametermboththe
`NMOSandPMOSdevioesthemm-onorthresho|dvolmge,di:eussedin(1:apterl
`andusually called Vm.Vminits simplest fotmisgiven by
`
`V” _ V" + 2*’ + \/2: C1:x(24»)
`
`(13)
`
`where Vn is the gate voltage required to oompensate forwork lunnion differences be-
`tween lhegateandsubstratqandforanydeariealchargesthat maybepresentinthe
`gateoxide.d>,isthepositionoftheRrmilevelinthebulltwithrespecttotheintrinsic
`leveIande,thepermittivityofsilieon.Forourpresentpurpooes.the twotennsthat
`areimportanlarethedopingoonoentrationinlhesilioon NA andtheoxidecapacitanoe
`C... Since C. is inversely proportional to the gate oxide thickness. it is clear that we
`must control this thicknes in ondertooontrol Vru.
`In writing the above expresion. we have assumed that the doping in the silicon im-
`derthe MOSgateiseonstantatN...'l1:u'sis tsuallynotthecaseinmoderndevioesbe-
`cause ion implantation is used to adjust the threshold voltage and this results in a
`nonuniform dopingprofile.Again totirstordeizwecan include the effect of theimplant
`on Vm in the following way:
`
`v,,,-v,,+z¢,+—é1——-L”2‘(_N*(2“’)+-4-9
`OX
`COX
`
`(2.4)
`
`where Q: is the implant dose.in atoms per cm‘.1'his equation assuins that the entire
`implantdoeeisloeatedinlhenearsurfaceregion.insidetheMOSehanneldepletion re-
`gion.1his isoften a remonable approximation.
`We are now ready to adjust the threshold voltages of both N- and P-channel MOS
`devices In modern CMOS circuits. the target threshold voltage is generally around
`0.5-0.8 volts for both the NMOS and PMOS devices. (1he threshold voltage is positive
`lorthe NMOSdevioesand negativeforthe PMOSdevieessothat both trambtorsare
`normally off, enhancement mode devices) figure 2-22 illustrates the masking to adjust
`theNMOS Vm.PIiotoresistisappIiedand mask4isusedtoopentheareaswhexe
`NMOS devices are located. After developing, a boron implant is used to adjust V-m. A
`tloseofl-5 X l0"‘an"atanenergyof50-75 keV mightbeused.We oouldestimate
`the newcsarydoseusingl.-Zq.(2.4)whereN,.isthedopinginthel’wellatthesurfaoebe-
`fore the impIant.andQ:isthedoserequiredtoachieveagiven Vm.'n:eenergyischo-
`sen tobehigh enough togettheimplantdosethmugh thethinoxide,but lowenough
`tokeeptheboronnearthesiliconsinfaee.
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`Chapter2 Mohlflllfiledltoloy
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`WW 1.‘ ‘
`
`‘
`
`ii;}3'2¥ii'TiE}"s;a'£i'i;pnom-«sumac-iu.mst4sunan.esaemeuuos
`tranaiaaarxhboronirrflarndlathefl-dimdl‘m
`
`Figure 2-23 illustrates the same process sequence now applied to the PMOS -A
`Mask 5 is used. The required implant could be either N- or P-type depending on
`dopinglevel in the N well and the required PMOS Vm.An N-type impl
`'
`'
`1 n
`in Figure 2—23.‘l‘his would typically be arsenic with a dose of l—S X 10'’ cm“.
`u _
`ergy would be somewhat higher than the NMOS channel implant in figure 2-22
`cause of the heavier mass of arsenic.
`If a P-type implant were needed.boron would be used with a dose and energy ~
`same range as for the NMOS device in Figure 2-27. In some cases. it might be --=
`to use only one mask to adjust both NMOS and PMOS Vm il both require P
`ants One pomible process might be to implant boron unmasked into both
`the smaller of the two doses required for the MOS devices A mask would then be
`alongwithaseeondirnplanttoincreuethedoseinthedevice reqttiringmorc --
`Figure 2-24 illustrates the next steps We are now ready to grow the gate oxi ~
`the MOS tr-ansistorsflhe thinoiddemhichispreeent overthe active areas ofeaeh»
`sistonistirststripped inadilutefll-‘solution.HFisahighlyseleetive ctehantand
`stop etching when the underlyingsilieonisreaehed.Notehoweverthat wewill --
`small portion ofthe field oxide duringlhisstepbecausethe l-[Fetch isunmaslted.
`we arcetehingonly l0or20nmofoxide.this isusually not a problem.allhoughthe-
`needstobetimedsothatitdoesnotetchtoomuchofthefieldoxide
`11tereasonthatthethinoxideissu-ippedandthenregmwntoformthe MOS
`oxideisthattheoxideonthesiliconsurfacepriortostrippingistoothielr toserve
`device gate oxide. Stripping and reg:-owing this oxide results in a well-controlled
`
`'
`.
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`v
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`can out In hue sum, me game one isyou hr
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`-....._;§.s...;.;;;.._..
`deportnootnllavlydopetllepnly
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`k
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`very critical here,provided the phosphorus or arsenic do not penetrate through the n
`and into the underlying gate oxide and substrate. Both dopants rapidly redistn
`j
`poly at elevated temperatures because diffusion is rapid along the grain
`poly.so uniform dopingofthe polywill oecurlaterintheprooesswhen the wafers
`next heated in a furnace.'lheN‘ dose is not critical for the MOS gates othetthan
`fact thatwewould likeittobeashighaspossibleinordertoobtainlowpolysheet
`sistivityandheneelawgateresistanoe.AdoseofaboutS X l0"cm"wouldbet '
`In some polysilicon deposition systems. the poly can be doped while it is being
`posited.’lhis is referred to as “in situ" doped poly. In this use. the ion implantation '_
`ing step would not be neeesary.
`The final step. illustrated in Figure 2-26 uses resist and mask 6 to etch the poly ~
`in region where it is not needed. Photoresist is spun onto the wafer,baked.and then '
`posed and developed. The poly etching would again be done in a plasma eteher.
`i
`cally a ehlorine- or bromine-based plasma chemistry would be used in order to -.
`
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`pcnseofsclectivityandviccvc
`tradaolfbctwecnthctwothatcnnbe
`I.heseisucsinChaplcrl0.
`
`2.2.7 ‘lip or Extension (IDD) Formation
`The next several sums are illustrated in Figures 2-27 to 2-30. Our objective in
`stepsistwofold.Firsl.wewanllointxoducclheN‘ and?‘ ilnplantsshowninthe =_
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`CIIap0cI’2Horlu'ncM06'&aoIog
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`1
`
`.
`
`exponentianyontheeleetricfieldmodestrveductionsinthefieldsuength
`throughtheLDDsuuctm'ecanmakeasignificantdifferenoeh1devicerelinbilit3L_
`AfinalpointregardingtheseN‘andP’ implantsisalsoimportanttomalte. -V
`vice geometries have become smaller. “short channel elleets” have become
`—
`portantinMOSuansistms.11Ieseefiectsresultwhcnthedraine|ectficfie1d-au--
`throngh the channel region and begins to affect the potential barrier -
`—-
`somoeandehannelregionsflheresultisdr-aincurrentthatisnotoontrolledeff
`bythegate.Anirnportantstrategyforminimizingtheseetfectsktheuseot
`--
`junctionssudnjunetions arelesssusceptibletoshonchanncl eflectsmentially »-~
`their geometry-minimizesthejur\<:aionameasadjaoenttothechannel.The LDD _
`tnrealsoprovidestheseshallowjunctionswhidrinthisoontextareotlen ».
`--
`“tip"or"extension" regionssincetheymustbecombinedwithdeepersoureeand ’
`'
`'onsawaytmmthechannelinordertomakereliableoontactstothe
`'
`N‘andP'implantsinFigures2-27and2—28andthesidewallspaoersinfigure
`usedtooonst:uctthesetiporextensionorLDDregions
`InFrgurez-2'7,photoresistissptmonthewaferandmask7isthenusedto
`allthedevieesexeepttheNMOSuansistm:Aphosphorusimplantisdoneto -
`N‘ region.’IhedoseandtheenergyareearefulIyeontrolledinthisimtplantto un-
`produoe thedesiredgradeddrainjunaion.TypicalIy,adoseofnbout5 X 10“ to
`cm"ataIowenergymightbersed.Asirnilarseqneneeofsteps'3used «--
`‘
`'
`LDDrcgioIBinthesedcv'Ices.A :-
`hnphmwouldbcpedommdalthoughboronwouldbemedinthiscase.[nsome_
`em MOS device structures. the “LDD” implants my aetuallyconsist of »
`«
`_
`plantsatdiflerventenergiesanddosessomeoftheseinrphntsmayevenbc