Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`Paper No. ________
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`Sony Corporation
`
`Petitioner
`v.
`
`Raytheon Company
`(record) Patent Owner
`
`Patent No. 5,591,678
`
`
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET. SEQ.
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`TABLE OF CONTENTS
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`TABLE OF CONTENTS .................................................................................................... ii
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`NOTICE OF LEAD AND BACKUP COUNSEL ......................................................... 1
`
`NOTICE OF THE REAL-PARTIES-IN-INTEREST ................................................... 1
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`NOTICE OF RELATED MATTERS ............................................................................... 1
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`NOTICE OF SERVICE INFORMATION ...................................................................... 1
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`GROUNDS FOR STANDING .......................................................................................... 2
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`STATEMENT OF PRECISE RELIEF REQUESTED .................................................. 2
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`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW ......................... 2
`
`I.
`
`II.
`
`A.
`
`B.
`
`INTRODUCTION TO THE SUBJECT MATTER ............................... 2
`
`INTRODUCTION TO THE PRIOR ART ............................................. 7
`
`Overview of Bertin ........................................................................................ 8
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`Overview of Morimoto ............................................................................... 12
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`III.
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`CLAIM CONSTRUCTION ...................................................................... 16
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`A.
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`B.
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`C.
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`IV.
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`A.
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`B.
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`C.
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`Claims 1, 3, 6-7, 11, 13, 15—“Microelectronic Circuit Element” ......... 17
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`Claims 1, 11, 13—“Etching,” “Etchable Layer” and “Etch Stop Layer.”
` ........................................................................................................................ 17
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`Claims 1, 3-5, 11-13, 15-18—“Wafer” ...................................................... 18
`
`DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY............................................................................... 18
`
` Claims 1, 6, 7, 10, and 11 are unpatentable under 35 U.S.C. § 102(e)
`over Bertin. ................................................................................................... 18
`
` Claims 5 and 12-13 are obvious as in Ground 1 in view of Morimoto. 29
`
`Overview of the Combination ................................................................... 29
`
`Level of skill in the art. ................................................................................ 29
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`Element-by-element analysis of claims 5 and 12-13 ................................ 30
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` Claim 9 is obvious over Bertin, in further view of Ying. ........................ 34
`
` Claims 1-2, 4-5, 10, 13-14 and 16-17 are unpatentable under 35 U.S.C. §
`103(a) over Morimoto in view of the CMP / Etching references. ........ 35
`
`D.
`
`Overview of the Ground ............................................................................ 36
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`E.
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`Element-by-element analysis of claims 1-2, 4-5, 10, 13-14 and 16-17. . 37
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`(i)
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`It was obvious to use “etching” within a CMP process. .......................... 42
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`It would also have been obvious to use only etching (without polishing),
`(ii)
`because etching was a known alternative to CMP .............................................. 44
`
` Claims 8 and 18 are invalid under 35 U.S.C. § 103(a) as in Ground 4, in
`further view of Oldham. ............................................................................. 57
`
` Claims 3 and 15 are obvious as in Ground 4, in further view of Bertin. ..
` ........................................................................................................................ 58
`
`V.
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`CONCLUSION ........................................................................................... 60
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`CERTIFICATE OF SERVICE ......................................................................................... 61
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`TABLE OF EXHIBITS
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`
`Description
`U.S. Patent No. 5,591,678 (“the ’678 patent”).
`Declaration of Dr. Blanchard.
`Hamaguchi, et al. “Novel SOI Technology Using Preferential
`Polishing”, NEC Research Notes 1480 (70), 1987.
`Certified Translation of Hamaguchi.
`Japanese Unexamined Patent Application Publication No. 64-
`18248, published January 23, 1989 (“Morimoto”).
`Certified translation of Morimoto.
`U.S. Pat. No. 5,244,534 (“Yu”).
`U.S. Pat. No. 4,910,155 (“Cote”).
`U.S. Pat. No. 5,064,683 (“Poon”).
`U.S. Pat. No. 5,069,002 (“Sandhu”).
`U.S. Pat. No. 5,189,500 (“Kusunoki”).
`U.S. Pat. No. 5,066,993 (“Miura”).
`U.S. Pat. No. 5,080,730 (“Wittkower”).
`U.S. Pat. No. 4,681,718 (“Oldham”).
`Excerpt from Dictionary of Electronics, Harper-Collins, 2004 (p. 152).
`U.S. Pat. No. 4,982,266 (“Ying”).
`U.S. Pat. No. 5,202,754 (“Bertin”).
`U.S. Pat. App. Ser. No. 07/760,041 (“Bertin App.”), filed Sept. 13,
`1991.
`U.S. Pat. App. Ser. No. 08/006,120, Amendment of June 16, 1994.
`Independent claim comparison for the ’678 patent.
`U.S. Pat. App. Ser. No. 08/006,120 (application with claims).
`
`Exhibit No.
`1001
`1002
`1003
`
`1004
`1005
`
`1006
`1007
`1008
`1009
`1010
`1011
`1012
`1013
`1014
`1015
`1016
`1017
`1018
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`1019
`1020
`1021
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`NOTICE OF LEAD AND BACKUP COUNSEL
`
`Lead Counsel: Matthew A. Smith (Reg. No. 49,003); Tel: 650.265.6109
`
`Backup Counsel: Zhuanjia Gu (Reg. No. 51,758); Tel: 650.529.4752
`
`Backup Counsel: Robert Hails (Reg. No. 39,702); Tel. 202.220.4235
`
`Address of lead counsel: Turner Boyd LLP, 702 Marshall St., Ste. 640
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`Redwood City, CA 94063. FAX: 650.521.5931.
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`NOTICE OF THE REAL-PARTIES-IN-INTEREST
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`The real-parties-in-interest for this petition are Sony Corporation, Sony
`
`Corporation of America, Sony Semiconductor Corporation, Sony EMCS Corporation,
`
`Sony Electronics, Inc., Sony Mobile Communications, Inc., Sony Mobile
`
`Communications AB and Sony Mobile Communications (USA), Inc.
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`NOTICE OF RELATED MATTERS
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`The ’678 patent has been asserted in the cases styled Raytheon Company v. Sony
`
`Corporation, et al., C.A. No. 2:15-cv-342, (E.D. Tex.) and Raytheon Company v. Samsung
`
`Electronics Co., Ltd. et al., C.A. No. 2-15-cv-00341 (E.D. Tex.). Both cases were filed
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`March 6, 2015 and remain pending.
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`NOTICE OF SERVICE INFORMATION
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`Please address all correspondence to the lead counsel at the addresses shown
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`above. Petitioners consent to electronic service by email at the following addresses:
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`smith@turnerboyd.com, docketing@turnerboyd.com, gu@turnerboyd.com.
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`Petition for inter partes review
`U.S. Pat. No. 5,591,678
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`GROUNDS FOR STANDING
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`Petitioner hereby certifies that the patent for which review is sought is available for
`
`inter partes review and that the Petitioner is not barred or estopped from requesting
`
`an inter partes review on the grounds identified in the petition.
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`STATEMENT OF PRECISE RELIEF REQUESTED
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`Petitioner respectfully requests that claims 1-18 of U.S. Patent No. 5,591,678 (“the
`
`’678 patent”) (Ex. 1001) be canceled based on the following grounds:
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`Ground 1: Claims 1, 6, 7, 10, and 11 are anticipated by Bertin.
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`Ground 2: Claims 5 and 12-13 are obvious as in Ground 1 in view of Morimoto.
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`Ground 3: Claim 9 is obvious over Bertin as in Ground 1 in further view of Ying.
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`Ground 4: Claims 1-2, 4-5, 10, 13-14 and 16-17 are obvious over Morimoto in view
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`of the CMP / Etching references.
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`
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`Ground 5: Claims 8 and 18 are obvious as in Ground 4 in view of Oldham.
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`Ground 6: Claims 3 and 15 are obvious as in Ground 4 in view of Bertin.
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`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW
`
`This petition presents “a reasonable likelihood that the Petitioners would prevail
`
`with respect to at least one of the claims challenged in the petition”, 35 U.S.C.
`
`§ 314(a), as shown in the Grounds explained below.
`
`I.
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`INTRODUCTION TO THE SUBJECT MATTER
`
`At a high level, the ’678 patent involves the manufacture of stacked integrated
`
`circuits, or “chips”. (Ex. 1001, 1:65 – 2:2; 7:60-65). When chips are used in a system,
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`they are often mounted adjacent to each other on a circuit board, as shown in the
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`drawing at right (looking down onto a flat board). Circuit boards are generally a
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`rectangle of material, and may have to fit into a computer or
`
`other device having a compact housing. Because of the spatial
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`limits of the housing, circuit boards often have a limited area.
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`This limited area can sometimes constrain the number and size
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`of chips that can be wired to the board. (Ex. 1002, ¶35).
`
`One way to increase the number of chips on a circuit board
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`
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`is to stack the chips, as shown in the drawing at right. Two stacked chips take up
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`approximately the same circuit board area as a single chip. When stacked, the
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`electrical contacts on each chip need to be wired to
`
`the circuit board. (Ex. 1001, 1:51-57). In the
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`relevant timeframe, there was an active industry
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`designing stacked chips. (Ex. 1002, ¶35)(Ex. 1006, p. 1-3)(Ex. 1017, 1:29-33).
`
`In the disclosure of the ’678 patent, stacks are made by manipulating and stacking
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`semiconductor-based building blocks called “substrates”. Each substrate begins as
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`three layers: an “etchable layer”, an “etch-stop” layer and a “wafer”, as shown in the
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`relevant portion of Fig. 1 below (highlighting added). There, substrate 40 has a top
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`“wafer” 46 (highlighted yellow), a bottom etchable layer 42 (blue), and a middle etch-
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`stop layer 44 (green). (Ex. 1001, 3:64-4:2)(Ex. 1002, ¶37). The top wafer 46 contains
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`integrated circuit elements, such as transistors. (Ex. 1002, ¶37). The bottom
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`“etchable layer” 42 is a layer that dissolves readily when exposed to an etchant. In
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`contrast, the middle “etch-stop” layer 44 does not
`
`dissolve readily when exposed to the etchant.
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`Because of this, an etching process stops when the
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`etchant reaches the “etch-stop” layer, after having
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`dissolved the etchable layer 42. (Ex. 1002, ¶37).
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`’678 Pat., FIG. 1
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`The thick etchable layer 42 on each substrate provides mechanical stability.
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`Without such an etchable layer, according to the ’678 patent, the overall substrate
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`might be too thin, and therefore too fragile to handle. (Ex. 1001, 1:58-65) (Ex. 1002,
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`¶45). The ’678 patent states:
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`“The circuit element usually is fabricated with a relatively thick first
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`substrate that provides support during initial fabrication and
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`handling.” (Ex. 1001, 2:59-64)(emphasis added)(Ex. 1002, ¶45).
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`To form a stack of chips, one could stack several of the three-layer substrates, each
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`of which contains its own integrated circuit in layer 46. Once a stack of chips is
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`formed, the chips need to be electrically connected. Connections to the chips are
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`made at the contacts on each chip. These contacts can connected using wires that run
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`from the contacts down the sides of the chip stack to the circuit board. According to
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`the ’678 patent, however, this method is “clumsy, space consuming, and impossible to
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`do for the case of highly complex circuitry”. (Ex. 1001, 1:51-57)(Ex. 1002, ¶46-47).
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`Another way to connect the contacts of chips in a stack would be to form
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`through-holes (or “vias”) through the etchable layer 42 and the etch-stop layer 44.
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`This would allow a chip that is lower in the stack to connect to the underside of a
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`chip higher in the stack. The ’678 patent states, however, that it is difficult to form
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`electrical connections that go all the way through the thick etchable layer 42:
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`“[I]t is difficult to achieve electrical connections through such a thick
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`substrate, because of the difficulty in locating deep, through-support vias
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`precisely at the required point, the difficulty in insulating the walls of
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`deep vias, and the difficulty in filling a deep via with conducting
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`material.” (Ex. 1001, 2:64-3:5)(Ex. 1002, ¶47).
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`One could remove the thick etchable layer to make the formation of vias easier.
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`However, the ’678 patent states that the etchable layer “cannot simply be removed to
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`permit access to the bottom side of the electrical circuit element, as the assembly
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`could not be handled in that very thin form.” (Ex. 1001, 3:2-5)(Ex. 1002, ¶47).
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`Therefore, the ’678 patent discloses another method: attaching the three-layer
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`substrate shown in Fig. 1 to a different, “support” structure. The ’678 patent states:
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`“[i]n the present approach, after initial circuit element fabrication on a first substrate
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`structure, the electrical circuit element is transferred to a second substrate structure.”
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`(Ex. 1001, 3:7-8)(Ex. 1002, ¶47). Once the substrate is supported by the new support
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`structure, the ’678 patent discloses removing the etchable layer 42. For example,
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`claim 1 of the ’678 patent recites:
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` “1. A method of fabricating a microelectronic device, comprising the
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`steps of:
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`furnishing a first substrate having an etchable layer, an etch-stop layer
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`overlying the etchable layer, and a wafer overlying the etch-stop layer;
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`forming a microelectronic circuit element in the exposed side of the
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`wafer of the first substrate opposite to the side overlying the etch-stop
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`layer;
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`attaching the wafer of the first substrate to a second substrate; and
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`etching away the etchable layer of the first substrate down to the etch-
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`stop layer.” (Ex. 1001, 8:5-16).
`
`The process of the ’678 patent is explained in more detail in reference to Fig. 1 of
`
`the ’678 patent, which shows a series of steps. The first step 20 involves providing
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`the substrate with three layers (Ex. 1001, 3:66-4:2) (Ex. 1002, ¶37). The ’678 patent
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`admits that this three-layer substrate is not novel, stating “[s]uch substrates can be
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`purchased commercially.” (Ex. 1001, 4:2)(Ex. 1002, ¶37).
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`The second step 22 in the ’678 patent is the formation of a “microelectronic
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`circuit”. (Ex. 1002, ¶38). This step is recited in independent claims 1, 11 and 13 as
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`“forming a microelectronic circuit element”. A “microelectronic circuit element” is
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`defined broadly in the specification. (Ex.
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`1001, 4:43-52); see § III.A, below.
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`The next step 24 (shown in relevant
`
`excerpt from Fig. 1, at right, with highlighting
`
`added) involves attaching to the top of the
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` ’678 Pat., FIG. 1
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`first microelectronic element to a second substrate 58 (orange) (Ex. 1002, ¶39). The
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`second substrate 58 can include its own microelectronic circuit element. (Ex. 1001,
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`5:20-21) (Ex. 1002, ¶39). The second substrate and wafer are bonded using (e.g.)
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`epoxy. (Ex. 1001, 5:15-44)(Ex. 1002, ¶39).
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`The second substrate is then itself mounted to a sapphire support 62 by a layer of
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`wax 64. (Ex. 1001, 5:47-49)(Ex. 1002, ¶40). The support 62 (brown) is shown in the
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`excerpt from Fig. 1, at right, with coloring added.
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`In the figure, an etching step has also been applied
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`after the mounting step to remove etchable layer
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`42. The etching step involved exposing the layer
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` ’678 Pat., FIG. 1
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`42 to a liquid etchant. The ’678 patent notes that:
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`“The etchant is chosen so that it attacks the etchable layer 42 relatively
`
`rapidly, but the etch-stop layer 44 relatively slowly or not at all. The terms
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`'etchable' and 'etch-stop' indicate a relative relation to each other in a
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`particular etchant, as used herein.” (Ex. 1001, 5:52-57)(Ex. 1002, ¶40).
`
`II.
`
`INTRODUCTION TO THE PRIOR ART
`
`U.S. Patent No. 5,202,754 (“Bertin”)(Ex. 1017) and Japanese Unexamined Patent
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`Application Publication No. 64-18248 (“Morimoto”)(Ex. 1005) are the most
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`significant references for purposes of this Petition. Bertin is prior art under pre-AIA
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`§ 102(e), because its application was filed in 1991, and the patent issued in 1993. The
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`content of the application leading to the Bertin patent (Ex. 1018) supports the
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`relevant content of the issued patent. (Ex. 1002, ¶80). Morimoto was published on
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`Jan. 23, 1989, and is thus prior art under pre-AIA § 102(b). A certified translation is
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`provided as Ex. 1006.
`
`A. Overview of Bertin
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`Bertin discloses a process whereby “multiple layers of integrated circuit chips …
`
`can be vertically interconnected”. (Ex. 1017, 6:6-9). Bertin’s process is essentially the
`
`same process described in the ’678 patent: making chips separately on thick
`
`substrates that also have an etchable layer and an etch-stop layer, transferring the
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`chips to a support structure, and removing the etchable layer. (Ex. 1002, ¶¶65-79).
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`Like the ’678 patent, Bertin starts with
`
`a substrate (or “device” 50) shown in Fig.
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`3a at right. The device has an etchable
`
`Bertin, FIG. 3a
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`layer 52 (highlighted blue), an etch-stop layer 53 (green), and a wafer (the portion of
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`the substrate above the etch-stop 53), which includes an “active layer” 54 (yellow) in
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`which circuit elements are formed. (Ex. 1017, 3:50-54, 4:4-6)(Ex. 1002, ¶72). The
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`specification explains that “processing begins with a semiconductor device 50
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`(preferably comprising a wafer) having a substrate 52 and an active layer 54”, where
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`the wafer “is modified during manufacture by placing a burred [sic: buried] etch stop
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`53 below the surface of the substrate”. (Ex. 1017, 3:50-52; 4:4-6)(Ex. 1002, ¶¶73-74).
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`Bertin next forms circuit structures in his wafer. Bertin describes that active layer
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`54 (yellow) includes active devices,
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`transistor circuitry of conventional
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`bipolar, CMOS, NMOS, or PMOS types.
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`Bertin, FIG. 3e
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`(Ex. 1002, 4:1-3)(Ex. 1002, ¶75). The layer 54 can be diffused into the substrate or
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`built on the substrate using semiconductor techniques. (Ex. 1017, 3:50-57)(Ex. 1002,
`
`¶76). Bertin also forms microelectronic circuit elements in the form of insulating
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`layers, wiring and metallized vias and contacts. (Ex. 1017, 3:67-4:1; 4:13-14; 4:34-40;
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`4:48-53; 5:30-38; claims 1-4)(Ex. 1002, ¶¶76-88).
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`After the circuit elements are formed, the substrate is bonded to a second or
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`“supporting” substrate, called a “carrier 70” (Fig. 3f,
`
`shown at right, with the carrier 70 highlighted orange).
`
`The carrier 70 is the “second substrate” of the ’678
`
`patent. Bertin explains:
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`“Assuming that the chips are separated, the first
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`Bertin, FIG. 3f
`
`integrated circuit chip 50 to be incorporated into the multi-chip package
`
`is flipped over and bonded to a suitable carrier 70 such that the
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`protective surface 63 of the chip 50 is disposed adjacent to the upper
`
`surface 71 of the carrier 70 (see Fig. 3f). Chip 50 is adhesively bonded to
`
`carrier 70 by use of a suitable adhesive material 73, such as a polyimide.”
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`(Ex. 1017, 4:63-5:2)(Emph. added)(Ex. 1002, ¶77).
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`In Bertin, the support substrate (carrier 70) can also be another integrated circuit
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`constructed in the same manner as the first integrated circuit:
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`“As an alternative to carrier 70, chip 50 could be bonded to a base
`
`integrated circuit chip (not shown) which would have contacts mirroring
`
`the positions of pads 68 of device 50 and a thickness sufficient to
`
`support the package, at least during assembly joining of integrated circuit
`
`chip 50 to such a base chip could be by Au to Au thermal compression
`
`bonding or other suitable means.” (Ex. 1017, 5:2-9)(Ex. 1002, ¶77).
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`Either way, after the supporting substrate is added, the etching step is performed.
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`The etching stops at the etch-stop layer:
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`“Next, the exposed second surface 58 of the chip 50 (FIG.3f) is etched
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`in a suitable chemical etch such as ethylenediamine, pyrocatechol, water
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`solution, or 200:1 nitric acid/HF solution. … The chemical etch is
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`selective so that etching ceases when etch stop layer 53 is reached
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`(FIG.3g)….The chemical etch removes only the silicon wafer down to
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`etch stop 53 (see FIG. 3g).” (Ex. 1017, 5:10-22)(Emph. added)(Ex.
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`1002, ¶¶78-79).
`
`Figure 3f shows the chip with the first substrate 52, the second substrate 70, and etch
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`stop layer 53, while in Figure 3g, the first substrate has been etched to the etch stop.
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`(Ex. 1002, ¶79).
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`Figure 3g: Bertin After Etching
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`Once the etching has occurred, contact pads 68 are built upon metalized trenches
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`66 and another integrated circuit structure is joined to the first. (Ex. 1017, ¶5:30-
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`38)(Ex. 1002, ¶79). The stacking process occurs “by the respective addition of
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`integrated circuit devices … one on top of another, each having this active layer
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`positioned adjacent to the last thinned exposed surface of the stack with contact pads
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`68 contacting at least some of the exposed metallized trenches 66 therein”. (Ex. 1017,
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`5:22-36)(Ex. 1002, ¶93). This is shown, e.g., in Fig. 3i where the structure of Fig. 3h
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`becomes a base (support substrate) for a new unit 50 (Fig. 3e) that is attached to the
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`top of the 3h structure (with an adhesive layer 73 in the middle). (Ex. 1002, ¶93).
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`Bertin, FIG. 3h
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`Bertin, FIG. 3i
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`Bertin states that this basic process can be repeated until a package is complete or
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`when further stacking becomes uneconomical. (Ex. 1017, 5:39-44)(Ex. 1002, ¶93).
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`Bertin thus describes what the named inventors of the ’678 patent represented
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`(Ex. 1019, pp. 5-6) was inventive: starting with a three-layer unit having a wafer, an
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`etch-stop layer and a support substrate, forming a microelectronic circuit element in
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`the exposed side of the wafer, attaching a second, support substrate to the exposed
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`side, removing the first substrate to access the back side of the circuit element, and
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`then forming connections to the back side of the device. (Ex. 1002, ¶¶65-79).
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`B. Overview of Morimoto
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`Morimoto’s disclosure is very similar to that of both the ’678 patent and Bertin.
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`(Ex. 1002, ¶¶107-123). Like the ’678 patent, Morimoto addresses the formation of
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`stacked integrated circuit products:
`
`“The present invention relates to a method for manufacturing
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`semiconductor devices, in particular, to a method for manufacturing
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`semiconductor devices having a structure where active or passive
`
`elements, or both, are stacked in multiple layers.” (Ex. 1006, p. 1)(Ex.
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`1002, ¶107).
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`Like Bertin, Morimoto uses the same method as the ’678 patent: making chips on
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`substrates having an etchable layer and an embedded etch-stop layer, transferring the
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`chips to another substrate, and removing the etchable layer. (Ex. 1002, ¶108).
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`Morimoto’s substrate has a wafer (top), an etch-stop layer (middle) and an etchable
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`layer (bottom). A comparison between Fig. 1(a) of Morimoto and Fig. 1 of the ’678
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`patent is shown below, with highlighting added (Ex. 1002, ¶109):
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`Morimoto, Fig. 1(a)
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`’678 patent, Fig. 1
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`Morimoto’s layer 11 is an etchable silicon layer (highlighted blue), which
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`corresponds to the ’678 patent's etchable silicon layer 42 (blue). Morimoto’s layer 12
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`is an SiO2 etch-stop layer (green), and corresponds to the ’678 patent’s SiO2 etch-stop
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`layer 44 (green). (Ex. 1002, ¶¶109-110). The top portion of Morimoto’s diagram is a
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`silicon wafer layer (yellow) in which microelectronic circuit elements (such as MOS
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`transistor 13) are formed. This corresponds to the wafer 46 (yellow) of the ’678
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`patent, where microelectronic circuit elements are formed. (Ex. 1002, ¶¶109-110).
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`Morimoto states that the Fig. 1(a) substrate is created as follows:
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`“As shown in FIG. 1(a), a buried oxide layer 12 comprised of a silicon
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`oxide film is formed by implanting oxygen ions at a dose of 2 x 1018
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`cm-2 across the entire surface of a p-type silicon substrate 11 at an
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`accelerating voltage of 150 keV, followed by annealing at about 1,200°C.
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`Then, an n-channel MOS transistor 13, wiring 14, and an insulating
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`film 15 comprised of a silicon oxide film are formed thereon.” (Ex.
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`1006, p. 2)(Emph. added)(Ex. 1002, ¶111).
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`Morimoto’s process begins with a semiconductor substrate 11, shown below on
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`the left side. (Ex. 1006, p. 2)(Ex. 1002, ¶112). The drawings below were created for
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`this proceeding from Fig. 1(a) of Morimoto, by removing the internal markings, in
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`order to show the start of the process. (Ex. 1002, ¶¶112-113).
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`Morimoto’s initial substrate
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`Morimoto’s substrate after ion
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`13
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`implantation and heating.
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`Morimoto teaches forming an etch-stop layer 12 (green) in the middle of block 11.
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`This is also shown above (right side), which has been adapted from Fig. 1(a) of
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`Morimoto by removing the microelectronic circuit elements. (Ex. 1002, ¶113). The
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`etch-stop layer 12 is formed by oxygen ion implantation and heating. (Ex. 1006, p.
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`2)(Ex. 1002, ¶114). In that process, oxygen ions are implanted. The ions penetrate to
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`a certain depth depending on their energy (in this case, the depth is the eventual depth
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`of layer 12). In Morimoto, the ion energy is 150 keV, which would have signified to a
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`person of skill an average depth of about 2850 Å. (Ex. 1002, ¶114). Upon heating,
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`the implanted ions will react with the Si semiconductor material to form SiO2. (Ex.
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`1002, ¶79). This has the effect of dividing the thick semiconductor into a three-layer
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`substrate just like the one in the ’678 patent. (Ex. 1002, ¶114). Specifically, the three-
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`layer structure in Fig. 1(a) of Morimoto has a bottom etchable layer (blue, which
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`Morimoto continues to label “11” in Fig. 1(a)), a middle etch-stop layer 12 (green,
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`formed by ion implantation) and a top Si layer (yellow), in which microelectronic
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`circuit elements will be formed. (Ex. 1006, p. 2)(Ex. 1002, ¶114).
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`Morimoto next teaches forming circuit elements in the top portion of the three-
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`layer structure, to arrive at Fig. 1(a) shown above. (Ex. 1006, p. 2)(Ex. 1002, ¶115).
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`After the microelectronic circuit elements are formed, Morimoto teaches—just like
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`Bertin and the ’678 patent—that the thick substrate layer 11 at the bottom of the
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`semiconductor should be removed. If the layer is removed, however, then the
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`substrate will no longer be supporting the circuit elements. For that reason,
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`Morimoto teaches first bonding the stack to a second or “supporting” substrate:
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`“Next, as shown in FIG. 1(b), a supporting silicon substrate 16 is
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`bonded on the insulating film 15 with an epoxy resin or the like….” (Ex.
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`1006, p. 2)(Ex. 1002, ¶116).
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`After the support substrate is bonded, Morimoto teaches removing the layer 11.
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`Morimoto accomplishes this by chemical-mechanical polishing (“CMP”). CMP
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`typically involves used etching (the “chemical” part) together with mechanical action
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`to enhance the etching. This process removes the thick substrate down to the etch-
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`stop layer. (Ex. 1002, ¶117). Morimoto states:
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`“the silicon substrate 11 is polished from the back surface by chemical
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`mechanical polishing. Since the buried oxide film layer 12 is present,
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`chemical mechanical polishing stops at the lower surface of the
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`buried oxide film layer. Accordingly, the silicon substrate 11 would be
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`polished off from the back surface to the lower surface of the buried
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`oxide film layer 12.” (Ex. 1006, p. 2)(emphasis added)(Ex. 1002, ¶117).
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`After bonding to the support substrate (labeled “16” and colored orange) and
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`removal of the substrate 11, the resulting structure is shown in Fig. 1(b) (Ex. 1002,
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`¶¶118-120), reproduced below (left side) with coloring added:
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`Morimoto, after removing layer 11
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`Morimoto, with wiring 17 through 12
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`Just like the ’678 patent, Morimoto’s etch-stop layer 12 is exposed to form electrical
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`connections through the etch-stop layer 12. This is called “backsurface” or
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`“backside” wiring. (Ex. 1002, ¶121). The resulting device is shown in Fig. 1(c) of
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`Morimoto (above, right, highlighting added), where through-holes have been formed
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`in the layer 12, and “back-surface” wiring 17 has been formed. Morimoto states:
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`“Next, as shown in FIG. 1(c), a through-hole is formed in the buried
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`oxide film layer 12, and backsurface wiring 17 is formed therein.” (Ex.
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`1006, p. 2)(Ex. 1002, ¶¶119-120).
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`Morimoto summarizes its disclosure in its “Means for Solving the Problem”:
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`“The method for manufacturing semiconductor devices according to the
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`present invention is characterized by including the steps of:
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`forming an element and wiring on a semiconductor substrate which has
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`a buried insulating layer formed by ion implantation, and bonding a
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`supporting substrate thereon;
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`polishing the back surface of said semiconductor substrate by chemical
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`mechanical polishing to the lower surface of said buried insulating layer;
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`and
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`opening a through-hole at a given position in said buried insulating layer
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`and forming back surface wiring therein.” (Ex. 1006, p. 2) (Ex. 1002,
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`¶121).
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`III. CLAIM CONSTRUCTION
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`The ’678 patent is expired. For an expired patent, the PTAB gives claims “their
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`ordinary and customary meaning, as would be understood by a person of ordinary
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`skill in the art, at the time of the invention, in light of the language of the claims, the
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`specification, and the prosecution history of record”. Cisco Systems, Inc. v. AIP
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`Acquisition, LLC, Case No. IPR2014-00247, Paper 20 (Order on Conduct of
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`Proceedings) at pp. 2-3 (PTAB July 10, 2014).
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`A. Claims 1, 3, 6-7, 11, 13, 15—“Microelectronic Circuit Element”
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`Claims 1, 3, 6-7, 11, 13 and 15 use the term “microelectronic circuit element”. The
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`’678 patent describes this term as follows:
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`“As used herein, the term ‘microelectronic circuit element’ is to be
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`interpreted broadly, and can include active devices and passive structure.
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`For example, the microelectronic circuit element can include many active
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`devices such as transistors. Alternatively, it may be simply a patterned
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`electrical conductor layer that is used as an interconnect between other
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`layers of structure in a stacked three-dimensional device, or may be a
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`sensor element.” (Ex. 1001, 4:43-52).
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`The term “microelectronic circuit element” therefore should mean “active devices or
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`passive structures useful for circuits”. (Ex. 1002, ¶60).
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`B. Claims 1, 11, 13—“Etching,” “Etchable Layer” and “Etch Stop Layer.”
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`Independent claims 1, 11 and 13 use the terms “etching,” “etchable layer” and
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`“etch stop layer.” The Collins Dictionary of Electronics defines “etching” as “the
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`dissolving of material by a chemical process”. (Ex. 1015, p. 152). This is consistent
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`with the ’678 patent’s use of the term. (Ex. 1001, 5:52-6:3)(Ex. 1002, ¶61).
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`The ’678 patent explains the terms “etchable layer” and “etch stop layer” indicate a
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`relative relation to each other in a particular etchant. An “etchable layer” is dissolved
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`relatively rapidly by an etchant, while an “etch-stop layer” is dissolved relatively slowly
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`(or not at all) by the same etchant. (Ex. 1001, 5:52-57)(Ex. 1002, ¶61).
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`C. Claims 1, 3-5, 11-13, 15-18—“Wafer”
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`Claims 1, 3-5, 11-13, 15-18 use the term “wafer”. Wafer appears to have its
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`customary meaning. The ’678 patent explains, however, that a wafer may contain
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`circuit elements. (Ex. 1001, 4:16-18)(Ex. 1002, ¶62). This is in accord with the
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`claims’ use of the term “wafer”, which refers to the structure before, during and after