PATENT APPLICATION SERIAL NO.:._.------ /
`
`S . DEPARTMENT OF COMMERCE
`~ATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
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`C814073 09/20/91 07760041
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`09-0456 140 101
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`650.00CH BU9-91-007
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`PT0-1556
`(5/87)
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`Sir:
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`~V.JV,J.,JUJ/
`
`1
`.~se Docket :-;o. BU9- 91-0 0 7
`
`Date: September 13, 1991
`
`BEST COPY
`
`Inventor: C. L. Bertin et al.
`
`For: THREE-DIMENSIONAL MULTICHIP PACKAGES ANP METHODS OF FABRICATION
`
`Enclosed are:
`
`8
`
`sheets of drawing (s) •
`
`An assigment of the invention to International Business· Machines Corporation.
`
`A certified copy of a - - - - - - . , . . - - - - - - - - - - - - - application.
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`An associate power of attorney.
`
`rn
`rn
`D
`D
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`The . filing fee has been calculated as shown below:
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`(Col. 1
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`FOR:
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`NO. FTI..ED
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`NO. EXTRA
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`BASIC FEE
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`21
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`-20 =
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`X 1
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`. 2
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`X 0
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`D MULTIPLE DEPENDENT c:r..AIM P:RESENTED
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`- 3 =
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`.
`OI'HER THAN A
`SMALL ENTITY
`
`FEE
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`$630.00
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`X 20
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`$ 20.00
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`X 60 = $
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`0
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`+zoo= $
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`enter "0" in Col. 2.
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`I
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`Transaction History Date \ q9l-tA-: \ ~
`Date information retrieved from USPTO Patent
`Application Information Retrieval (PAIR).
`system records at wwV.t.uspto.gov
`
`zero,
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`SUB TOI'AL. $ 650. OO·
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`ASSIGNMENT
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`TOrAL
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`$658.00
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`Please charge my Deposit Account No. 09-0456
`A duplicate copy of this sheet is enclosed.
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`in the axrount of $ 6 5 8 . 0 0
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`The Corrmissioner is hereby authorized to charge payrrent of the following fees
`associated with this ccmmunication or credit any ove:rpayrrent to Deposit Account
`No. 09-04p6
`• A duplicate copy of this sheet is enclosed.
`[L] Any additional filing fees required under 37. CFR §1.16.
`{!] Any patent application processing fees under 37 CFR §1.17.
`
`Respectfully submitted,
`FOR: C. L. Bertin et al.
`
`MARK F. CHADURJIAN
`INTELLECTUAL PROPERTY LAW · BURLINGTON
`IBM CORPORATION
`.
`DEP~ 915 .
`.ESSEX JUNCTION, VERMONT 054521
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`MFC/ml
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`002
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`m 760041
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`lnreapplicationof: C. L. Bertin et al.
`Serial No:
`Group No.:
`\. Filed:·
`Examiner:
`.THREE-DIMENSIONAL MULTICHIP PACKAGES AND METHODS OF
`F
`or:
`FABRICATION
`.
`Commissioner of Patents and Trademarks
`Washington, D.C. 20231
`
`EXPRESS MAIL CERTIFICATE
`"Express Mail" label number __ B_8_9_8_3_5_8_9_7 ___ _
`Date of Deposit
`September 13, 19 91
`
`It' is requested that the date· of deposit·be the filing date.
`
`I hereby certify that the following attached paper or fee
`Application, spe~ification·, drawings and abstract
`Assignment and declaration
`Transmittal sheet and post card
`Information Disclosure Statement
`
`is being deposited ·with the United States Postal Service "Express Mail Post Office to Ad(cid:173)
`dressee" service under 37 CFR 1.10 on the date indicated above and is addressed to the
`Commissioner of Patents and Trademarks, Washington. D.C. 20231.
`Maryann Luisi
`
`(Typod "f?;'' "'m' :1 '"'"" moiU"g p : • l:•l
`
`(Signature
`
`NOTE: Each paper must have its own certificate and the "Express Mail" label number as a part thereof or a Nached
`thereto. When. as here. the certification is presented on a separate sheet, that sheet must (1 J be signed and
`(2) fully Identify and be securely attached to the paper or. fee It accompanies. Identification should in(cid:173)
`clude the sen'al number and filing date of the application as well as /he type of paper being 1!1ed. e. g. com(cid:173)
`plete application, specification and drawings, responses to rejection or refusal, notice of appeal, etc. If the
`sen'al number of the application is not known, the identification should include at/east the name of the mven(cid:173)
`tor(s) and the title of /he invention.
`
`N(J}TE: · The label number need not be placed on each page. II should. however. be placed on the first page of each
`separate document, such as, a new application, amendment, assignment. and transmtNalleNer for a fee.
`along with the certificate of mailing by "Express Mat/. "Although the label number may be on checks, such a
`practice is not reawred. In order not to deface formal drawmgs it is suggested that the label numoer be
`placed on the back of each format drawing or the drawings be accompamed by a set of informal drawmgs on
`which the label number is placed.
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`THREE-DIMENSIONAL MULTICHIP
`PACKAGES AND ME'l'HODS OF FABRICAT~
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`Background of the Invention
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`Technical Field
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`The present invention relates in general to high
`density electronic packaging which permits
`optimization of the number of circuit elements to be
`included in a given volume. More particular, the
`present invention relates to a method for fabricating
`a three-dimensional multichip package having a
`densely stacked array of semiconductor chips
`interconnected at least.partially by means of a
`plurality of metallized trenches in the semiconductor
`chips .
`
`.~·.. Description of the Prior Art
`Since the development of integrated circuit
`technology, computers and computer storage devices
`have been made from wafers of semiconductor material
`comprising a plurality of integrated circuits. After
`a wafer is madeJ the circuits are typically separated
`from each other by dicing the wafer into small chips.
`Thereafter, the chips are bonded to carriers of
`various types, interconnected by wires and packaged.
`Along with being time consuming, costly and
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`unreliable, the process of physically attaching wires
`to interconnect chips often produces undesirable
`signal delays, especially as the frequency of device
`operation increases.
`As an improvement over this traditional
`technology, stack or packages of multiple
`semiconductor chips have become popular, e.g.,
`reference U.S. Patent No. 4,525,921, entitled
`"High-Density Electronic Processing
`Package - Structure and Fabrication." Figure 1
`depicts a typical semiconductor chip stack, generally
`denoted 10, consisting of multiple integrated circuit
`chips 12 which are adhesively secured together. A
`metallization pattern 14 is provided on one or more
`sides of stack 10 for chip interconnections and for
`electrical connection to circuitry external to the
`stack. Metallization pattern 14 includes both
`individual contacts 16 and bussed contacts 18. Stack
`10, with metallization 14 thereon, is positioned on
`the upper surface 21 of a substrate 20 which has its
`own metallization pattern 22 thereon. Although
`superior to the more conventional technique of
`individually placing·chips on a board, substrate or
`multichip carrier, both in terms of reliability and
`circuit performance, this multichip stack approach is
`still susceptible to improvement in terms of density
`and reduction in the length of chip wiring.
`Obviously, any improvements in such package
`characteristics will produce a lower cost, ~ower
`power higher density, reliability and thereby
`providing better performing device.
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`Summary of the Invention
`Briefly described, the present invention
`comprises in one aspect a multichip packaging method
`which includes the initial step of providing an
`integrated circuit device having a first, upper
`surface and a second, lower surface in substantially
`parallel opposing relation. The device, which may
`comprise a semiconductor chip or wafer, has an active
`layer adjacent to the first surface and a substrate
`adjacent to the second surface. The device further
`includes a plurality of metallized trenches therein
`which extend from the first surface through the
`active layer and partially into the substrate. At
`least some of the plurality of metallized trenches
`are in electrical contact with the active layer of
`the integrated circuit device. The packaging method
`further includes affixing this integrated circuit
`device to a carrier such that the second surface
`thereof is exposed, allowing the thinning of the
`substrate of the integrated circuit device until
`exposing at least some of the plurality of metallized
`trenches therein~ Electrical contact can thus be
`made to the active layer of the integrated circuit
`device via the exposed metallized trenches.
`Additional integrated circuit devices are preferably
`added to the stack in a similar manner. As each
`layer of circuit devices is added electrical contact
`to at least some of the exposed metallized trenches
`of the previous layer is made.
`In another aspect of
`the ~resent invention, a novel multichip package
`system, resulting from application of the above
`processing method~ is provided. Specific details of
`the method and the resultant package are described in
`detail and claimed herein.
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`The present invention advantageously produces a
`multichip package having high integrated circuit
`density. Wiring solutions are presented for very
`dense packaging I/O connects, and three-dimensional
`vertical and horizontal wiring is discussed.
`Further, techniques to limit the power dissipation of
`particular functions in a dense multichip package are
`provided.
`In accordance with the processing approach
`of the present invention, a multiple chip package can
`be created in the same space previously required for
`a single integrated circuit chip. Further,
`fabrication of the individual wafers/chips to be
`assembled into the multichip package remain~
`consistent with high volume wafer manufacturing.
`
`Brief Description of the Drawings
`The subject matter which is regarded as the
`present invention is particularly pointed out and
`distinctly claimed in the concluding portion of the
`specification. The invention, however, both as. to
`organization and method of practice, together with
`further objects and advantages there6f, may best be
`understood by reference to the following detailed
`description taken in conjunction with the
`accompanying drawings in which:
`Figure 1 is an exploded perspective view of a
`basic prior art multichip package;
`Figures 2a & 2b illustrate the difference in
`packaging density between a multichip package
`t
`fabricated in accordance with existing techniques
`(Figure 2a) and a multichip package fabricated
`pursuant to the present invention {Figure 2b);
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`Figures 3a-3i are partial cross~sectional
`elevational depictions ot structures obtained at
`various processing steps ~n accordance with one
`multichip package fabrication embodiment pursuant to
`the present invention;
`Figures 4a-4d depict various electrical lead
`wiring options trom or through an integrated circuit
`device pursuant to the present ~nvention;
`Figures Sa & Sb illustrate the different
`requirements in access surface wiring for DRAM and
`SRAM configurations for a multichip package
`constructed in accordance with existing techniques
`{Figure Sa) and for a multichip package constructed
`in accordance with the present invention {Figure Sb);
`and
`
`Figure 6 graphically depicts an example ot the
`difterent integrated circu~t packaging densities
`obtainab~ing Small Outline J Lead {SOJ), Cube.~Rd •
`{Fig. 1~that produced in the present invention
`packaging techniques.
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`Detailed Description of the Invent~0n
`
`Broadly stated, the present invention comprises
`a method for improving the circuit density in a
`multichip package, such as stack 10 depicted in
`Figure 1. Figure 2a depicts a conventional multichip
`stack 30 having two chips, chip l and chip 2. Each
`chip has an active layer 32 which extends within the
`chip~ distance "x", and an overall thickness "y"
`from an
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`upper surface 31 to a lower surface 3.3 thereof. Chip
`thickness 11 Y11 is at least an order of magnitude
`grea.ter than active layer thickness 11 X 11
`For
`example, typically thickness "x" is within the range
`of 5-20 micrometers, while thickness 11 Y 11 is more
`conventionally in the range of 750-850 micrometers
`(30 mils). However, recently the practice is to
`reduce thickness "y" by mechanical thinning of the
`substrate in each chip to approximately 375-425
`micrometers (15 mils) prior to assembly of the
`package. Notwithstanding this mechanical reduction,
`the volume of the useful active silicon, e.g., active
`layers 32, remains much less than that of the total
`silicon. This is because the silicon substrate still
`continues to be used for mechanical support of layer
`32 of the chip during processing.
`In comparison with the package of Figure 2a, the
`semiconductor chips in a package processed pursuant
`to the present invention have only a thin layer of
`substrate for support of the active layer, which is
`illustrated in Figure 2b wherein two thin
`semiconductor chips, chip 1 and chip 2, are shown.
`These chips are stacked in a package 40. The active
`layer 42 of each chip in package 40 has a thickness
`11 x'" which, as shown, is a significant portion of the
`chip thickness "y'". This is in contrast to the
`large size disparity between thickness "x 11 and
`thickness "y" for the conventional package of Figure
`2a. By way of example, thickness "x'" may be in the
`5-20 ~icrometers range, while the overall thickness
`"y'" of each device may be only 20 micrometers or
`less. This means that when the chips are combined in
`a stack configuration a significantly denser
`electronic package is produced than is possible using
`previous stacking techniques for separate integrated
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`In essence, processing in accordance
`circuit chips.
`with the present invention advantageously eliminates
`most of the excess silicon substrate in a silicon
`device after bonding of the device to a growing
`multichip package.
`One example of a package tabrication process
`pursuant to the present invention is described below
`with reference to F~gures 3a-3i.
`Referring f~rst to Figure 3a, processing begins
`with a sem~conductor device SO (preferably comprising
`a wafer) having a substrate 52 and an active layer
`~4, which is typically pos~tioned at least part~ally
`therein.
`(Layer 54 may be totally or partially
`defused into substrate 52 and/or partially or totally
`built up trom substrate 52 using conventional
`semiconductor processing techniques known to those
`skilled in the art.)
`Layer 54 is adjacent to a
`first, upper planar surface 56 ot device SO. A
`second, lower planar surface ~~ ot device 50 is
`positioned substantially parallel to tirst planar
`surface 56. A dielectric layer 60, for example,
`Sio2 , is grown over active layer ~4 ot device 50.
`Although var~able, substrate 52 th~cKness will
`typicalLy be approximately 7~u-~~O micrometers (15
`mils) prior to ·creat~on ot a multichip package.
`In
`comparison, the thickness of active layer 54 may be
`in the range of 4-6 micrometers, While the thickness
`of insulating Layer 60 Will vary, e.g., W~th the
`number o~ metallization levels already built upon
`acti~e layer ~4. Layer 54 may comprise any
`conventional bipolar, CMOS, NMOS, PMOS, etc.,
`circuitry.
`Pursuant to the invention, a standard wafer is
`modified during manu~acture by placing a bur~ed etch
`stop 53 below the surface ot the substrate. The etch
`stop can
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`comprise an N+ layer 53 in a P subst~ate 52 or a P+
`layer 53 in an N substrate 52, both of which can be
`fabricated by any one of several means known to those
`skilled in the art.
`Shown in exaggerated size in Figure 3b are thin,
`deep trenches 62 defined in integrated circuit device
`50. Trenches 62 are configured to extend slightly
`through etch stop layer 53 into substrate 52.
`In a
`preferred embodiment, deep trenches 62 will each have
`a high aspect ratio of approximately 20:1, which
`means, for example, that thin trenches 62 will
`preferably have a width of 1 micrometer for a 20
`micrometer deep trench.
`(As described below, the
`high aspect ratio trenches 62 will ultimately
`advantageously serve to define very small
`interconnect dimensions.) Trenches 62 can be
`fabricated pursuant to the techniques described in
`u.s. Patent No. 4,717,448, entitled:
`"Reactive Ion
`Etch Chemistry for Providing Deep Vertical Trenches
`in Semiconductor Substrates," which is hereby
`incorporated herein py reference. Deep trenches 62
`are positioned in the integrated circuit device 50
`where electrical through connections between devices
`are desired. once the multichip package is assembled.
`The trench sidewalls are oxidized to provide
`isolation from the bulk silicon (such that the
`trenches can be used for wiring without shorting the
`devices), with doped polysilicon or other conductor
`64 (see Figure 3c). The device, including wiring
`level~, can next be completed using standard
`processing techniques, with the layout of the devices
`(circuits) being modified so that the area 61 (see
`Figure 3d) where polysilicon filled trenches are
`positioned remains clear of circuitry and_wiring
`embedded within completed oxidation/connecting
`metallization ·layer 63.
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`Reterring to Figure 3e, deep trenches 62 are
`next reetched to remove polysilicon plugs o4, using
`techniques known in the·a~t. The trenches 62 are
`then filled W1th an appropriate metal bb, e.g.,
`tungsten Au, Cu, aLuminum or other su1taoLe metal, by
`a chemical vapor deposition CVD process, plating or
`other appropriate means. Metallized trenches 66 W1Ll
`extend at least s11ghtly through etch stop layer 53.
`Contact pads b~ of gold, copper or other appropriate
`metal are then deposited so that they will
`interconnect the appropriate wir1ng· \not shown) on
`the chip to the vertically disposed wiring 66 in
`trenches 62. The Lntegrated circuit chips are then
`tested, the wafers diced and the good chips are
`selected. Alternatively, the wafers may be left
`undiced depending upon the processing path chosen.
`1r sufficient redundancy LS ouilt into the structure
`so as to produce essentLally a 100% yield or good
`chips, then the ~~afers will reJna~n undiced. Whether
`the wafers are to be diced or remain und1ced,
`however, they are preferably tLrst mechanically
`thinned, for example, to at least 375-4UU micrometers
`(15 mils) L.e~, if not already accomplished.
`Assuming that the chips are separated, the first
`integrated c1rcuit chip 50 to be incorporated into
`the mul·tichip package is flipped over and bonded to a
`suitable carrier 70 such that the protective surtace
`63 o~ chip 50 is disposed adjacent the upper surface
`11 of carrier 70 (see Figure 3f). Chip 50 is
`adhesively bonded·to carrier 70 by use of a suitable
`adhesive material 73, such·as a polyimide.
`(As an
`alternative to carrier 70, chip 50 could oe bonded to
`a base integrated circuit chip (not shown) which
`would have contacts mirroring the pos1tions of pads
`68 of device 50 and a th1ckness sufficient to support
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`Joining of
`the package, at least during assembly.
`integrated circuit chip 50 to such a base chip could
`be by Au to Au thermal compression bonding or other
`sui table 'means.)
`Next, the exposed second surface 58 of chip 50
`(Fig. 3f) is etched in a suitable selective chemical
`etch such as ethylenediamine, pyrocatechol, water
`solution, or 200:1 nitric acid/HF solution. See
`co-pending U.S. Patent Application entitled "Three
`Dimensional Semiconductor Structure Formed from
`Planar Layers," S.N. 656,902, filed Feb. 15, 1991,
`Continuation of S.N. 427,679, filed Oct. 26, 1989.
`The chemical etch is selective so that etching ceases
`when etch stop layer 53 is reached (Fig. 3g).
`Further, the etchant is selected so as not to etch
`metal 66 deposited within deep trenches 62. The
`chemical etch removes only the silicon wafer down to
`etch stop 53 (see Figure 3g). As shown in Figure 3h,
`an appropriate photo-definable polyimide 80 or other
`bonding compound is then applied and etched to
`partially reveal the metallized trenches 66 in chip
`50. Prior to complete curing of the polymer, Au is
`plated electrolessly and selectively on the
`metallized trench connections to form pads 82.
`aluminum is used to metallize the trenches, a
`suitable diffusion barrier (not shown), such as Cr,
`is plated on the Al prior to Au plating. The
`stacking process is repeated by the respective
`addition of integrated circuit devices (see, e.g.,
`Figur~ 3i) one on.top of the other, each having its
`active layer -5-zt-positioned adjacent to the last
`thinned exposed surface of the stack with contact
`pads 68 contacting at least some of the exposed
`metallized trenches 66 therein. Bonding of each chip
`layer is such that the polymer and Au to Au bonding
`preferably take place simultaneously.
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`Should full wafer stacking be used, the process
`is essentially the.same. The wafers are subsequently
`diced into separate multichip packages at an
`appropriate point in the process, either when the
`package is complete or when the cumulative yield is
`such as to make further stacking uneconomical.
`It will be observed that a significant advantage
`is attained pursuant to the fabrication process set
`forth, i.e., the elimination of excess silicon
`substrate material from the separately constructed
`integrated circuit devices as the multichip package
`is assembled, without interfering with the active
`silicon layers thereon. The removed silicon is
`single crystal silicon and the fabrication of
`individual integrated circuit devices remains
`consistent with high volume semiconductor wafer
`manufacturing. As described below, multichip
`packages constructed pursuant to this processing
`technique achieve the greatest possible silicon
`volumetric density for separately fabricated
`integrated circuit devices. The device thicknesses
`are adjusted to more closely reflect the active
`surface and depth actually used so
`that package density is more closely linked to
`feature depth. -
`Figures 4a-4d depict several examples of
`integrated circuit chip connection options for a
`multichip package constructed pursuant to the present
`invention.
`In Figure 4a, horizontal connecting leads
`92 extend to a planar side surface 94 of chip 90 to
`provide electrical connection between side surface 94
`and selected pads 96 on the surface of chip 90. Once
`multiple chips are assembled in a stack, at least
`some of which may include horizontal extending leads
`92, a pattern of metallization can be deposited on
`the edge surface of the stack to define connects to
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`individual electrical pads in the chip, and/or
`multiple selected electrical pads located on one or
`more of the integrated circuit chips.
`By utilizing the metallized trench approach of
`the present invention, multiple layers of integrated
`circuit chips, such as chip 90, can be vertically
`interconnected via metallized trenches, e.g.,
`trenches 98 in Figure 4b. Trenches 98, constructed
`as described above in connection with Figures 3a-3i,
`are positioned to extend through the respective chip
`90. Alternatively, a mixture of vertically and
`horizontally extending interconnecting leads can be
`used.
`In such a mixed interconnecting circuitry
`application, the horizontal leads 92 can extend to
`one or more edge surface.s 94 of the chip 90 (Figure
`4c), and/or only extend between selected pads in a
`single chip (Figure 4d). The scale of wirability
`between integrated circuit chips in the multichip
`package is believed to comprise a significant
`improvement over state of art package wiring. The
`dimensions of the vertical interconnections between
`integrated circuit chips are at least an order of
`magnitude smaller than any prior "gross" vertical
`connection wiri~g technique.
`One factor to consider in devising a
`horizontal/vertical interconnection scheme is the
`amount of space that will be available on the edge
`surfaces of the completed multichip package. Figure
`Sa pantially depicts several semiconductor chips 100
`arranged in a conventional multichip package. Each
`chip 100 has several electrical leads 102 extending
`therefrom to at least one side surface of the
`package. Traditionally, T-shaped electrical
`junctions are formed in the access plane (i.e., at
`least one planar side surface of the multichip
`package having the pattern of chip interconnecting
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`metallization thereon (not shown)), to provide good
`electrical junctions with the leads brought out to
`that side surface from the respective integrated
`circuit chips 100. This is accomplished by
`depositing conductor pads 104 of uniform size on top
`of the access plane so that each pad intersects with
`an end of an electrical lead 102 brought out from the
`respective integrated circuit chips 100.
`In many applications, planar side wiring is in
`the form of stripes (or buses) 10S extending
`perpendicular to the planes of the chips. Each
`stripe 10S crosses the junctions between a plurality
`of chips where it makes electrical contact with the
`T-shaped junctions on the chips.
`In many other
`applications, unique I/O junctions 106 are required
`for making individual co.ntacts on separate integrated
`circuit chips 100.
`In the multichip DRAM, SRAM,
`EPROM, or other integrate circuits or combination
`thereof package of Figure Sa, sufficient space is
`available on the chips for readily providing these
`I/0 contacts 106 within the access plane. For
`example, typical spacing between adjacent T-junctions
`of the same integrated circuit chip is approximately
`.OS millimeters (2 mils), while T-junction spacing
`between adjacent chips is approximately .375
`millimeters (15 mils).
`Examples of access plane sizing for both DRAM
`and SRAM multichip packages assembled pursuant to the
`present invention are depicted in Figure Sb. As
`shownt the spacing between electrical leads 110
`brought out from adjacent integrated circuit chips
`112 in both DRAM arid SRAM configurations is
`significantly reduced from the spacing between these
`leads in Figure Sa. For example, in a DRAM
`application, such spacing may be approximately 20
`micrometers (.02 millimeters) and for a SRAM
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`application, spacing may drop down to 10 micrometers
`(.01 millimeters).
`In order to form. discrete I/O
`contact pads 114, therefore, it is necessary to
`spread out laterally the T-shaped electrical
`junctions to allow room for the unique I/0 contacts.
`This in turn limits the number of stripes (or buses)
`116 which can extend perpendicular to the planes of
`the integrated circuit chips.
`The invention overcomes this problem by
`utilizing the metallized trenches for bussing. That
`is, in addition to forming simple chip-to-chip
`interconnections, the trenches can be arranged to
`provide bussing between non-adjacent chips.
`In
`effect, we have added an additional wiring plane that
`reduces the constraints imposed by the thinness of
`the chips on chip edge wiring.
`In designing chips
`for the cube of the invention, circuit placement etc.
`must be optimized for through-chip wireability.
`However, the resulting decrease in circuit density is
`more that compensated by introducing an entirely new
`wiring plane. The invention will actually enhance
`performance, because no~ each circuit can be only 30
`\liD (the thickness of the chip) distant from
`interdependent circuitry arranged ~n an ab~tting
`chip, as opposed to up to 3000 llm distant from
`interdependent circuitry on the same chip. So,
`instead of designing each chip independently,
`circuits can be placed on different chips to reduce
`transmission delays by the stacking and through-chip
`wiring techniques of the invention.
`• Table 1 and Figure 6 set forth an example of the
`significant dens~ty advantages obtained by
`constructing a multichip module in accordance with
`the present invention.
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`Package
`Type
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`Density 3
`{Mbits/in )
`
`Ratio
`
`SOJ
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`Cube
`
`128
`
`2,484
`
`Invention
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`46,620
`
`1
`
`19
`
`364
`
`TABLE 1
`
`SRAM
`
`Density
`(Mbits/in3 )
`
`Ratio
`
`DRAM/SRAM Ratio
`Storage Density
`
`24
`
`427
`
`15,993
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`1
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`18
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`In this example, the first package comprises
`DRAM or SRAM chips assembled with SOJ technology, the
`second package comprises DRAM or SRAM chips mounted
`in a "Cube" using tech~ology such as that described
`in U.S. Patent No. 4,525,921, entitled "High-Density
`Electronic Processing Package - Structure and
`Fabrication," and the third package comprises DRAM or
`SRAM chips mounted in an assembly pursuant to the
`present invention. The configurations used were a 4
`MBit DRAM scaled from 0.8-0.6 micrometer Ground Rules
`(G.R.) and a 1 Mbit. SRAM in 0.6 micrometer G.R. For
`both DRAMs and SRAMs, the Cube packaging produced a
`density improvement of more than an order of
`magnitude over the SOJ package, while the present
`invention improved storage density by more than two
`orders of magnitude over the SOJ package.
`For the present invention the active surface
`depth effects the final packaging leverage. A DRAM
`package with a 10 micrometer depth for metallized
`trenches plus the surrounding region, requires 20
`micrometers with a·guardband.
`In comparison, a SRAM
`package, with 1-2 micrometers for devices, is assumed
`to need no more than 10 micrometers in total depth.
`The storage density of SRAM packages improves
`significantly for present invention technology in
`comparison with that obtainable with SOJ or Cube
`approaches. This is an indication that the ultimate
`silicon density is being approached using the
`pr~sent invention.
`Another measure of storage density leverage is
`to estimate the .storage density for packages of
`approximately the same height. Assuming a package
`height equal to the package width, then.for a DRAM
`that is 8.98 millimet~rs, a two chip high SOJ is 7.12
`millimeters. Further assuming that both the Cube and
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`Present invention packages will be approximately
`square, then the following functional comparison (as
`shown in Table 2) for 4M DRAMs can be obtained:
`
`Package Type
`
`TABLE 2
`
`2 Chip (SOJ)
`32 chip (Cube)
`512 chip (Invention)
`
`Storage
`Density
`
`lMByte
`16MByte
`256Mbyte
`
`One further consideration to be addressed in
`connection with the present invention is that the
`power dissipation per unit volume increases with
`packaging density. Clearly, a multichip package
`fabricated pursuant to the present invention will
`have a greater power density than most previous
`multichip packages. Also, since not all chips are
`selected at a given time, standby power is
`extremely important. For example, in a DRAM
`package, perhaps only 1/16 or 1/32 chips may be
`selected for particular applica~ions. Therefore,
`reducing standby power can be very significant.
`One possible technique to lowering power
`dissipation is to improve retention time and
`reduce refresh requirements. Also, with high
`densities, Flash-EPROM chips can be added to the
`stack so that address locations which change
`infrequently can have zero power dissipation data
`stored in Flash-EPROM cells.
`Lastly, a multichip package constructed
`pursuant to the present invention is compact and a
`good thermal conductor. The package could be
`cooled with a cold tip and should be consistent
`with low temperature operation, e.g., in liquid
`nitrogen.
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`While the invention has been described in
`detail herein in accordance with certain preferred
`embodiments thereof, many modifications and
`changes therein may be ~ffected by those skilled
`in the art. Accordingly, it is intended by the
`appended claims to cover all such modifications
`'
`and changes as fall within the true spirit and
`scope of the invention.
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