'
`
`Ulllted States Patent [19]
`Bertin et a1.
`
`[54] THREE-DIMENSIONAL MULTICHIP
`PACKAGES AND METHODS 0]:
`FABRICATION
`
`[75] Inventors: Claude L. Bertin; Paul A. Farm, Sr.,
`both of South Burlington; Howard L.
`Kalter, Colchester; Gordon A. Kelley,
`Jr., Essex Junction; Willem B. van
`der Hoeveu, Jericho; Francis R.
`White, Essex, all of Vt.
`.
`-
`"31 Ass‘gm' lc‘fmfatgff 8, “i238 whine‘
`m ’
`’
`'
`'
`[21] App]. No.: 760,041
`[22] Filed:
`Sep. 13, 1991
`
`[51] Int. Cl.5 ....................... .. H01L 29/78- 844C 1/22
`[52] us. (:1. ............................. .. 251/6114; 251/111;
`257/723; 257/725
`[58] Field of Search ..................... .. 357/75, 80,
`
`[56]
`
`References Cited
`
`,
`
`,
`
`Lacom e
`
`.
`
`.
`
`U'S' PATENT POCUMENTS
`HM"; ----------------- u
`l’, 52 5,921 7/1985 :
`n a a],
`29/577 C
`4,612,083 9/1986 Yasumoto =1 .1.
`. 156/633
`“546,627 3/1987 Abernathy et 1 ‘
`29/571
`4,111,448 1/1988 Cox et n. ........... ..
`.. 156/643
`4,807,021 2/1989 Okumura .... ..
`357/75
`4,829,018 5/1989 Wahlstrom
`437/51
`21:11’ 1:1 ---- -
`431/51
`4,954,453 9/1990 Reid ........ ..
`__ 365"“
`4,967,393 10/1990 yokoym et a1.
`351/15
`4,989,063 1/1991 Kolesar, Jr. ..... ..
`5,091,762 2/1992 Watanabe ............................ .. 351/15
`
`,
`
`,
`
`I 0 Ct
`
`.
`
`....
`
`4,954,875 9/1990 Clements ......... ..
`
`357/75
`
`FOREIGN PATENT DOCUMENTS
`0314437 3/1989 European Fat. 011'. .
`
`IIIIIIIIIIIIIIlllllllllllll|||||||I||llllllllllllllllllllllllllllllllllllll
`[11] Patent Number:
`5,202,754
`[45] Date of Patent:
`Apr. 13, 1993
`
`USO0S202754A
`
`0374971 6/ 1990 Europe!!! Flt OfT- -
`3233195 3/1983 Fed. Rep. of Germany .
`58-43554 3/ I983 Japan .
`60-79763 5/1985 Japan .
`61-22660 1/1986 Japan .
`1326758 8/1973 United Kingdom .
`
`OTHER PUBLICATIONS
`Lasky, J. 13., "Wafer Bonding for Silicon-on-Insulator
`Technologies,” Appl. Phys. Lett., vol. 48, No. 1, pp.
`78-80, Jan., 1986.
`Lineback, J. Robert, “3D 1c Packaging Moves Closer
`to Commercial Use," Electronic World News, pp. 15 t
`18, May 21, 1990.
`Primary Examiner-Eugene R. LaRoche
`Am'stant Examiner-Viet Q. Nguyen
`.
`.
`4mm)” 45'8"‘ °’ lam-“c511” 5‘ Rmhmwg
`[57]
`ABSTRACT
`A fabrication method and msultant mmedimensiom
`multichip package having a densely stacked array of
`semiconductor chips interconnected at least partially by
`means of a plurality of metallized trenches are dis
`closed. The fabrication method includes providing an
`integrated circuit chip having high aspect ratio metal
`lmed trenches therem extending from a ?rst surface'to 11
`mi'd surface there.“ .A" ‘m? .smp lay" '5 P'°‘".d°d
`proximate the termination posltion of the metalhzed
`trenches with ‘11¢ scmiconducwr substrate N91“ the
`integrated circuit device is affixed to a carrier such that
`the surface of the supporting substrate is exposed and
`substrate is thinned from the integrated circuit device
`gigggg?'ttguzfb'z?dhze :2
`the active layer of the integrated c1rcu1t_ch1p via the
`e1'Klwwd 1116181111913 trenches- Spw?c d?mls 0f the fab
`rication method and the resultant multichip package are
`set forth.
`
`’
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`6 Claims, 8 Drawing Sheets
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`458
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`SONY 1017
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`
`5,202,754
`
`002
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`

`
`US. Patent
`
`Apr. 1a, 1993
`
`Sheet 2 of 8
`
`5,202,754
`
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`
`US. Patent
`
`Apr. 13, 1993
`
`Sheet 3 of 8
`
`5,202,754
`
`56
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`fig- 2‘:
`
`fig. 3b
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`

`
`U.S. Patent
`
`Apr. 13, 1993
`
`Sheet 4 of 8
`
`005
`
`

`
`US. Patent
`
`Apr. 13, 1993
`
`Sheet 5 of 8
`
`5,202,754
`
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`US. Patent
`
`Apr. 13, 1993
`
`Sheet 6 of 8
`
`5,202,754
`
`82
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`

`
`U.S. Patent
`
`Apr. 13, 1993
`
`Sheet 7 of 3
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`5,202,754
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`Apr. 1a, 1993
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`1
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`5,202,754
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`THREE-DIMENSIONAL MULTICI-IIP PACKAGES
`AND METHODS OF FABRICATION
`
`5
`
`2
`includes affixing this integrated circuit device to a car
`rier such that the second surface thereof is exposed,
`allowing the thinning of the substrate of the integrated
`circuit device until exposing at least some of the plural
`ity of metallized trenches therein. Electrical contact can
`thus be made to the active layer of the integrated circuit
`device via the exposed metallized trenches. Additional
`integrated circuit devices are preferably added to the
`stack in a similar manner. As each layer of circuit de
`vices is added electrical contact to at least some of the
`exposed metalliced trenches of the previous layer is
`made. In another aspect of the present invention, a
`novel multichip package system, resulting from applica
`tion of the above processing method, is provided. Spe
`cifrc details of the method and the resultant package are
`described in detail and claimed herein.
`The present invention advantageously produces a
`multichip package having high integrated circuit den
`sity. Wiring solutions are presented for very dense
`packaging I/O connects, and three-dimensional vertical
`and horizontal wiring is discussed. Further, techniques
`to limit the power dissipation of particular functions in
`a dense multichip package are provided. In accordance
`with the processing approach of the present invention,
`a multiple chip package can be created in the same
`space previously required for a single integrated circuit
`chip. Further, fabrication of the individual wafers/chips
`to be assembled into the multichip package remains
`consistent with high volume wafer manufacturing.
`
`BACKGROUND OF THE INVENTION
`1. Technical Field
`The present invention relates in general to high den
`sity electronic packaging which permits optimization of
`the number of circuit elements to be included in a given
`volume. More particular, the present invention relates
`to a method for fabricating a three-dimensional multi
`chip package having a densely stacked array of semi
`conductor chips interconnected at least partially by
`means of a plurality of metallized trenches in the semi
`conductor chips.
`2. Description of the Prior Art
`Since the development of integrated circuit technol
`ogy, computers and computer storage devices have
`been made from wafers of semiconductor material com
`prising a plurality of integrated circuits. After a wafer is
`made, the circuits are typically separated from each
`other by dicing the wafer into small chips. Thereafter,
`the chips are bonded to carriers of various types, inter
`connected by wires and packaged. Along with being
`time consuming, costly and unreliable, the process of
`25
`physically attaching wires to interconnect chips often
`produces undesirable signal delays, especially as the
`frequency of device operation increases.
`As an improvement over this traditional technology,
`stack or packages of multiple semiconductor chips have
`become popular, e.g., reference US. Pat. No. 4,525,921,
`entitled "High-Density Electronic Processing Package
`BRIEF DESCRIPTION OF THE DRAWINGS
`- Structure and Fabrication." FIG. 1 depicts a typical
`semiconductor chip stack, generally denoted 10, con
`The subject matter which is regarded as the present
`sisting of multiple integrated circuit chips 12 which are
`invention is particularly pointed out and distinctly
`adhesively secured together. A metallization pattern 14
`claimed in the concluding portion of the speci?cation.
`is provided on one or more sides of stack 10 for chip
`The invention, however, both as to organization and
`interconnections and for electrical connection to cir
`method of practice, together with further objects and
`cuitry external to the stack. Metallization pattern 14
`advantages thereof, may best be understood by refer
`includes both individual contacts 16 and bussed
`40
`ence to the following detailed description taken in con
`contacts 18. Stack 10, with metallization l4 thereon, is
`junction with the accompanying drawings in which:
`positioned on the upper surface 21 of a substrate 20
`FIG. 1 is an exploded perspective view of a basic
`which has its own metallization pattern 22 thereon.
`prior art multichip package;
`Although superior to the more conventional technique
`FIGS. 20 & 2b illustrate the difference in packaging
`of individually placing chips on a board, substrate or
`45
`density between a multichip package fabricated in ac
`multichip carrier, both in terms of reliability and circuit
`cordance with existing techniques (FIG. 2a) and a mul
`performance, this multichip stack approach is still sus
`ceptible to improvement in terms of density and reduc
`tichip package fabricated pursuant to the present inven
`tion in the length of chip wiring. Obviously, any im
`tion (FIG. 2b);
`provements in such package characteristics will pro
`FIGS. 30-31’ are partial cross-sectional elevations]
`duce a lower cost, lower power higher density, reliabil~
`depictions or structures obtained at various processing
`ity and thereby providing better performing device.
`steps in accordance with one multichip package fabrica
`tion embodiment pursuant to the present invention;
`SUMMARY OF THE INVENTION
`FIGS. 404d depict various electrical lead wiring
`Brie?y described, the present invention comprises in
`options from or through an integrated circuit device
`one aspect a multichip packaging method which in
`pursuant to the present invention;
`cludes the initial step of providing an integrated circuit
`FIGS. 50 d: 5b illustrate the different requirements in
`device having a ?rst, upper surface and a second, lower
`access surface wiring for DRAM and SRAM con?gu
`surface in substantially parallel opposing relation. The
`rations for a multichip package constructed in accor
`device, which may comprise a semiconductor chip or
`dance with existing techniques (FIG. 5a) and for a mul
`wafer, has an active layer adjacent to the ?rst surface
`tichip package constructed in accordance with the pres
`and a substrate adjacent to the second surface. The
`ent invention (FIG. 5b); and
`device further includes a plurality of metallized
`FIG. 6 graphically depicts an example of the different
`trenches therein which extend from the first surface
`integrated circuit packaging densities obtainable using
`through the active layer and partially into the substrate.
`Small Outline J Lead (50]), Cube (FIG. 1) and that
`At least some of the plurality of metallized trenches are
`in electrical contact with the active layer of the inte
`produced in the present invention packaging tech
`niques.
`grated circuit device. The packaging method further
`
`30
`
`35
`
`50
`
`65
`
`010
`
`

`
`3
`DETAILED DESCRIPTION OF THE
`INVENTION
`Broadly stated, the present invention comprises a
`method for improving the circuit density in a multichip
`package, such as stack 10 depicted in FIG. 1. FIG. 2a
`depicts a conventional multichip stack 30 having two
`chips, chip 1 and chip 2. Each chip has an active layer
`32 which extends within the chip a distance “x”, and an
`overall thickness “y" from an upper surface 31 to a
`lower surface 33 thereof. Chip thickness "3!” is at least
`an order of magnitude greater than active layer thick
`ness “x”. For example, typically thickness “:r" is within
`the range of 5-20 micrometers, while thickness "y” is
`more conventionally in the range of 750-850 microme
`ters (30 mils). However, recently the practice is to re
`duce thickness "3!” by mechanical thinning of the sub
`strate in each chip to approximately 375-425 microme
`ters (l5 mils) prior to assembly of the package. Notwith
`standing this mechanical reduction, the volume of the
`useful active silicon, e. g., active layers 32, remains much
`less than that of the total silicon. This is because the
`silicon substrate still continues to be used for mechani
`cal support of layer 32 of the chip during processing.
`In comparison with the package of FIG. 2a, the semi
`conductor chips in a package processed pursuant to the
`present invention have only a thin layer of substrate for
`support of the active layer, which is illustrated in FIG.
`2b wherein two thin semiconductor chips, chip 1 and
`chip 2, are shown. These chips are stacked in a package
`40. The active layer 42 of each chip in package 40 has a
`thickness "x'" which, as shown, is a signi?cant portion
`of the chip thickness “y'”. This is in contrast to the large
`size disparity between thickness “x” and thickness “y”
`for the conventional package of FIG. 20. By way of
`example, thickness “x'” may be in the 5-20 micrometers
`range, while the overall thickness "y'" of each device
`may be only 20 micrometers or less. This means that
`when the chips are combined in a stack con?guration a
`signi?cantly denser electronic package is produced than
`is possible using previous stacking techniques for sepa
`rate integrated circuit chips. In essence, processing in
`accordance with the present invention advantageously
`eliminates most of the excess silicon substrate in a sili
`con device after bonding of the device to a growing
`45
`multichip package.
`One example of a package fabrication process pursu
`ant to the present invention is described below with
`reference to FIGS. 30-31‘.
`Referring ?rst to FIG. 3a, processing begins with a
`semiconductor device 50 (preferably comprising a wa
`fer) having a substrate 52 and an active layer 54, which
`is typically positioned at least partially therein. (Layer
`54 may be totally or partially defused into substrate 52
`and/or partially or totally built up from substrate 52
`using conventional semiconductor processing tech
`niques known to those skilled in the art.) Layer 54 is
`adjacent to a ?rst, upper planar surface 56 or device 50.
`A second, lower planar surface 58 or device 50 is posi
`tioned substantially parallel to ?rst planar surface 56. A
`dielectric layer 60, for example, SiOg, is grown over
`active layer 54 of device 50. Although variable, sub
`strate S2 thickness will typically be approximately
`750-800 micrometers (15 mils) prior to creation of a
`multichip package. In comparison, the thickness of 65
`active layer 54 may be in the range of 4-6 micrometers,
`while the thickness of insulating layer 60 will vary, e.g.,
`with the number or metallization levels already built
`
`5,202,754
`4
`upon active layer 54. Layer 54 may comprise any con
`ventional bipolar, CMOS, NMOS, PMOS, etc., cir
`cuitry.
`Pursuant to the invention, a standard wafer is modi
`?ed during manufacture by placing a burred etch stop
`53 below the surface of the substrate. The etch stop can
`comprise an N+ layer 53 in a P substrate 52 or a P+
`layer 53 in an N substrate 52, both of which can be
`fabricated by any one of several means known to those
`skilled in the art.
`Shown in exaggerated size in FIG. 3b are thin, deep
`trenches 62 de?ned in integrated circuit device 50.
`Trenches 62 are con?gured to extend slightly through
`etch stop layer 53 into substrate 52. In a preferred em
`bodiment, deep trenches 62 will each have a high aspect
`ratio of approximately 20:1, which means, for example,
`that thin trenches 62 will preferably have a width of l
`micrometer for a 20 micrometer deep trench. (As de
`scribed below, the high aspect ratio trenches 62 will
`ultimately advantageously serve to de?ne very small
`interconnect dimensions.) Trenches 62 can be fabri
`cated pursuant to the techniques described in US. Pat.
`No. 4,717,448, entitled: “Reactive Ion Etch Chemistry
`for Providing Deep Vertical Trenches in Semiconduc
`tor Substrates,” which is hereby incorporated herein by
`reference. Deep trenches 62 are positioned in the inte
`grated circuit device 50 where electrical through con
`nections between devices are desired once the multichip
`package is assembled.
`The trench sidewalls are oxidized to provide isolation
`from the bulk silicon (such that the trenches can be used
`for wiring without shorting the devices), with doped
`polysilicon or other conductor 64 (see FIG. 3c). The
`device, including wiring levels, can next be completed
`using standard processing techniques, with the layout of
`the devices (circuits) being modi?ed so that the area 61
`(see FIG. 3d) where polysilicon ?lled trenches are posi
`tioned remains clear of circuitry and wiring embedded
`within completed oxidation/connecting metallization
`layer 63.
`Referring to FIG. 3e, deep trenches 62 are next
`reetched to remove polysilicon plugs 64, using tech
`niques known in the art. The trenches 62 are then ?lled
`with an appropriate metal 66, e.g., tungsten Au, Cu,
`aluminum or other suitable metal, by a chemical vapor
`deposition CVD process, plating or other appropriate
`means. Metallized trenches 66 will extend at least
`slightly through etch stop layer 53. Contact pads 68 of
`gold, copper or other appropriate metal are then depos
`ited so that they will interconnect the appropriate wir
`ing (not shown) on the chip to the vertically disposed
`wiring 66 in trenches 62. The integrated circuit chips
`are then tested, the wafers diced and the good chips are
`selected. Alternatively, the wafers may be left undiced
`depending upon the processing path chosen. If suffi
`cient redundancy is built into the structure so as to
`produce essentially a 100% yield or good chips, then
`the wafers will remain undiced. Whether the wafers are
`to be diced or remain undiced, however, they are pref
`erably ?rst mechanically thinned, for example, to at
`least 375-400 micrometers (15 mils) i.e., if not already
`accomplished.
`Assuming that the chips are separated, the ?rst inte
`grated circuit chip 50 to be incorporated into the multi
`chip package is ?ipped over and bonded to a suitable
`carrier 70 such that the protective surface 63 of chip 50
`is disposed adjacent the upper surface 71 of carrier 70
`(see FIG. 3}). Chip 50 is adhesively bonded to carrier 70
`
`25
`
`35
`
`011
`
`

`
`5.
`
`25
`
`5,202,754
`5
`6
`extending leads 92, a ‘pattern of metallization can be
`by use of a suitable adhesive material 73, such as a poly
`imide. (As an alternative to carrier 70, chip 50 could be
`deposited on the edge surface of the stack to de?ne
`bonded to a base integrated circuit chip (not shown)
`connects to individual electrical pads in the chip, and
`which would have contacts mirroring the positions of
`/or multiple selected electrical pads located on one or
`pads 68 of device 50 and a thickness sufficient to sup
`more of the integrated circuit chips.
`port the package, at least during assembly joining of
`By utilizing the metallized trench approach of the
`present invention, multiple layers of integrated circuit
`integrated circuit chip 50 to such a base chip could be
`by Au to Au thermal compression bonding or other
`chips, such as chip 90, can be vertically interconnected
`suitable means.)
`via metallized trenches, e.g., trenches 98 in FIG. 4b.
`Next, the exposed second surface 58 of chip 50 (FIG.
`Trenches 98, constructed as described above in connec
`3]) is etched in a suitable selective chemical etch such as
`tion with FIGS. 30-31‘, are positioned to extend through
`ethylenediamine, pyrocatechol, water solution, or 20021
`the respective chip 90. Alternatively, a mixture of verti
`cally and horizontally extending interconnecting leads
`nitric acid/HF solution. See co-pending U.S. patent
`application entitled “Three Dimensional Semiconduc
`can be used. In such a mixed interconnecting circuitry
`tor Structure Formed from Planar Layers," Ser. No.
`application, the horizontal leads 92 can extend to one or
`656,902, filed Feb. 15, I991, continuation of Ser. No.
`more edge surfaces 94 of the chip 90 (FIG. 40), and/or
`427,679, ?led Oct. 26, I989. The chemical etch is selec
`only extend between selected pads in a single chip
`tive so that etching ceases when etch stop layer 53 is
`(FIG. 4d). The scale of wirability between integrated
`circuit chips in the multichip package is believed to
`reached (FIG. 33). Further, the etchant is selected so as
`not to etch metal 66 deposited within deep trenches 62.
`comprise a signi?cant improvement over state of art
`20
`The chemical etch removes only the silicon wafer down
`package wiring. The dimensions of the vertical inter
`to etch stop 53 (see FIG. 3g). As shown in FIG. 3h. an
`connections between integrated circuit chips are at least
`appropriate photo-de?nable polyimide 80 or other
`an order of magnitude smaller than any prior “gross"
`bonding compound is then applied and etched to par
`vertical connection wiring technique.
`tially reveal the metallized trenches 66 in chip 50. Prior
`One factor to consider in devising a horizontal/verti
`to complete curing of the polymer, Au is plated electro
`cal interconnection scheme is the amount of space that
`lessly and selectively on the metallized trench connec
`will be available on the edge surfaces of the completed
`multichip package. FIG. 5a partially depicts several
`tions to form pads 82. If aluminum is used to metallize
`the trenches, a suitable diffusion barrier (not shown),
`semiconductor chips 100 arranged in a conventional
`such as Cr, is plated on the Al prior to Au plating. The
`multichip package. Each chip 100 has several electrical
`stacking process is repeated by the respective addition
`leads 102 extending therefrom to at least one side sur
`face of the package. Traditionally, T~shaped electrical
`of integrated circuit devices (see, e.g., FIG. 31‘) one on
`top of the other, each having its active layer positioned
`junctions are formed in the access plane (i.e., at lent one
`adjacent to the last thinned exposed surface of the stack
`planar side surface of the multichip package having the
`pattern of chip interconnecting metallization thereon
`with contact pads 68 contacting at least some of the
`exposed metallized trenches 66 therein. Bonding of each
`(not shown», to provide good electrical junctions with
`chip layer is such that the polymer and Au to Au bond
`the leads brought out to that side surface from the re
`ing preferably take place simultaneously.
`spective integrated circuit chips 100. This is accom
`Should full wafer stacking be used, the process is
`plished by depositing conductor pads 104 of uniform
`essentially the same. The wafers are subsequently diced
`size on top of the access plane so that each pad inter—
`into separate multichip packages at an appropriate point
`sects with an end of an electrical lead 102 brought out
`in the process, either when the package is complete or
`from the respective integrated circuit chips 100.
`when the cumulative yield is such as to make further
`In many applications, planar side wiring is in the form
`stacking uneconomical.
`of stripes (or buses) 105 extending perpendicular to the
`It will be observed that a signi?cant advantage is
`planes of the chips. Each stripe 105 crosses the junctions
`attained pursuant to the fabrication process set forth,
`between a plurality of chips where it makes electrical
`i.e., the elimination of excess silicon substrate material
`contact with the T-shaped junctions on the chips. In
`from the separately constructed integrated circuit de
`many other applications, unique I/O junctions 106 are
`vices as the multichip package is assembled, without
`required for making individual contacts on separate
`interfering with the active silicon layers thereon. The
`integrated circuit chips 100. In the multichip DRAM,
`removed silicon is single crystal silicon and the fabrica
`SRAM, EPROM, or other integrate circuits or combi
`tion of individual integrated circuit devices remains
`nation thereof package of FIG. 5a, sufficient space is
`consistent with high volume semiconductor wafer man
`available on the chips for readily providing these I/O
`ufacturing. As described below, multichip packages
`contacts 106 within the access plane. For example, typi
`constructed pursuant to this processing technique
`cal spacing between adjacent T-junctions of the same
`achieve the greatest possible silicon volumetric density
`integrated circuit chip is approximately 0.05 millimeters
`for separately fabricated integrated circuit devices. The
`(2 mils), while T-junction spacing between adjacent
`chips is approximately 0.375 millimeters (15 mils).
`device thicknesses are adjusted to more closely re?ect
`the active surface and depth actually used so that pack
`Examples of access plane sizing for both DRAM and
`age density is more closely linked to feature depth.
`SRAM multichip packages assembled pursuant to the
`FIGS. 404d depict several examples of integrated
`present invention are depicted in FIG. 5b. As shown,
`circuit chip connection options for a multichip package
`the spacing between electrical leads 110 brought out
`constructed pursuant to the present invention. In FIG.
`from adjacent integrated circuit chips 112 in both
`4a, horizontal connecting leads 92 extend to a planar
`DRAM and SRAM con?gurations is signi?cantly re
`side surface 94 of chip 90 to provide electrical connec
`duced from the spacing between these leads in FIG. 5a.
`tion between side surface 94 and selected pads 96 on the
`For example, in a DRAM application, such spacing
`surface of chip 90. Once multiple chips are assembled in
`may be approximately 20 micrometers (0.02 millime
`ters) and for a SRAM application, spacing may drop
`a stack, at least some of which may include horizontal
`
`35
`
`40
`
`45
`
`60
`
`65
`
`012
`
`

`
`7
`down to 10 micrometers (0.01 millimeters). In order to
`form discrete I/O contact pads 114, therefore, it is nec
`essary to spread out laterally the T-shaped electrical
`junctions to allow room for the unique 1/0 contacts.
`This in turn limits the number of stripes (or buses) 116
`which can extend perpendicular to the planes of the
`integrated circuit chips.
`The invention overcomes this problem by utilizing
`the metallized trenches for bussing. That is, in addition
`to forming simple chip-to-chip interconnections, the
`trenches can be arranged to provide bussing between
`non-adjacent chips. In effect, we have added an addi
`tional wiring plane that reduces the constraints imposed
`by the thinness of the chips on chip edge wiring. In
`designing chips for the cube of the invention, circuit
`placement etc. must be optimized for through-chip
`wireability. However, the resulting decrease in circuit
`density is more that compensated by introducing an
`entirely new wiring plane. The invention will actually
`enhance performance, because now each circuit can be
`only 30 pm (the thickness of the chip) distant from
`interdependent circuitry arranged on an abutting chip,
`as opposed to up to 3000 um distant from interdepen
`dent circuitry on the same chip. So, instead of designing
`each chip independently, circuits can be placed on dif
`ferent chips to reduce transmission delays by the stack
`ing and through-chip wiring techniques of the inven
`tion.
`Table l and FIG. 6 set forth an example of the signi?
`cant density advantages obtained by constructing a
`multichip module in accordance with the present inven
`tion.
`
`25
`
`TABLE I
`
`Package
`Type
`so:
`one
`Invention
`
`DRAM
`Ra-
`Density
`tio
`(Mbits/in’)
`1
`128
`am 19
`‘6,620
`364
`
`SRAM
`Ra-
`Density
`(Maia/m1) tio
`24
`r
`42'!
`1s
`15,993
`666
`
`35
`
`DRAM/SRAM
`Ratio
`Storage
`Density
`5.3/1
`5.11/1
`2.9/1
`
`45
`
`In this example, the ?rst package comprises DRAM
`or SRAM chips assembled with SOJ technology, the
`second package comprises DRAM or SRAM chips
`mounted in a "Cube” using technology such as that
`described in US. Pat. No. 4,525,921, entitled “High
`Density Electronic Processing Package - Structure and
`Fabrication,” and the third package comprises DRAM
`or SRAM chips mounted in an assembly pursuant to the
`present invention. The con?gurations used were a 4
`MBit DRAM scaled from 0.8-0.6 micrometer Ground
`Rules (G.R.) and a 1 Mbit SRAM in 0.6 micrometer
`(3.11. For both DRAMs and SRAMs, the Cube packag
`ing produced a density improvement of more than an
`order of magnitude over the SOJ package, while the
`present invention improved storage density by more
`than two orders of magnitude over the SOJ package.
`For the present invention the active surface depth
`effects the ?nal packaging leverage. A DRAM package
`with a 10 micrometer depth for ‘metallized trenches plus
`the surrounding region, requires 20 micrometers with a
`guardband. ln comparison, a SRAM package, with l-2
`micrometers for devices, is assumed to need no more
`than 10 micrometers in total depth. The storage density
`65
`of SRAM packages improves signi?cantly for present
`invention technology in comparison with that obtain
`able with SOJ or Cube approaches. This is an indication
`
`$5
`
`5,202,754
`8
`that the ultimate silicon density is being approached
`using the present invention.
`Another measure of storage density leverage is to
`estimate the storage density for packages of approxi
`mately the same height. Assuming a package height
`equal to the package width, then for a DRAM that is
`8.98 millimeters, a two chip high SOJ is 7.12 millime
`ters. Further assuming that both the Cube and Present
`invention packages will be approximately square, then
`the following functional comparison (as shown in Table
`2) for 4M DRAMs can be obtained:
`TABLE 2
`
`Package Type
`2 Chip (SOJ)
`32 chip (Gabe)
`512 chip (Invention)
`
`Storage
`D?m'tlf
`IM Byte
`16M Byte
`256M byte
`
`One further consideration to be addressed in connec
`tion with the present invention is that the power dissipa
`tion per unit volume increases with packaging density.
`Clearly, a multichip package fabricated pursuant to the
`present invention will have a greater power density
`than most previous multichip packages. Also, since not
`all chips are selected at a given time, standby power is
`extremely important. For example, in a DRAM pack
`age, perhaps only l/l6 or l/32 chips may be selected
`for particular applications. Therefore, reducing standby
`power can be very signi?cant.
`One possible technique to lowering power dissipation
`is to improve retention time and reduce refresh require
`ments. Also, with high densities, Flash-EPROM chips
`can be added to the stack so that address locations
`which change infrequently can have zero power dissi
`pation data stored in Flash-EPROM cells.
`Lastly, a multichip package constructed pursuant to
`the present invention is compact and a good thermal
`conductor. The package could be cooled with a cold tip
`and should be consistent with low temperature opera
`tion, e.g., in liquid nitrogen.
`_
`While the invention has been described in detail
`herein in accordance with certain preferred embodi
`ments thereof, many modi?cations and changes therein
`may be effected by those skilled in the art. Accordingly,
`it is intended by the appended claims to cover all such
`modi?cations and changes as fall within the true spirit
`and scope of the invention.
`What is claimed is:
`1. A multichip package comprising:
`a carrier having an upper surface;
`a ?rst integrated circuit device having a ?rst surface
`and a second surface in substantially parallel oppos
`ing relation, said integrated circuit device having
`an active layer adjacent said ?rst surface and a
`substrate adjacent said second surface, the thick
`ness of said ?rst device from said ?rst surface to
`said second surface being less than thirty microme
`ters, said ?rst device further including a plurality of
`metallized trenches therein extending from said
`first surface to said second surface thereof, each of a
`said metallized trenches having a high aspect ratio
`of depth to width of approximately twenty to one,
`at least some of said plurality of metallized trenches
`being in electrical contact with the active layer of
`said ?rst integrated circuit device, said ?rst inte
`grated circuit device being disposed on said carrier
`
`013
`
`

`
`5,202,754
`10
`thereof being less than thirty micrometers, each of said
`with said ?rst surface of said device opposing said
`additional integrated circuit devices further including a
`upper surface of said carrier; and
`plurality of metallized trenches therein extending from
`a second integrated circuit device having a ?rst sur
`said ?rst surface to said second surface thereof, at least
`face and a second surface in substantially parallel
`some of said plurality of metallized trenches in at least
`opposing relation, said second