United States Patent [191
`Wittkower
`
`(54]
`
`[75}
`
`IMPLANTATION PROFILE CONTROL
`WITH SURFACE SPUTTERING
`Inventor: Andrew B. Wittkower, Rockport,
`Mass.
`IBIS Technology Corporation,
`Danvers, Mass.
`[21] Appl. No.: 342,484
`Apr. 24, 1989
`[22] Filed:
`Int. CJ,S .••.••••..........•..•....•.............•.• HOlL 21/ 265
`(51)
`[52] u.s. Cl ......................................... 148/ 33; 437/24;
`437/26; 437/62; 148/DIG. 158
`[58) Field of Search ....................... 437/24, 26, 61, 62;
`148/33, DIG. 158; 204/192.37, 192.25;
`250/492.21
`
`[73] Assignee:
`
`[56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,033,788 7/1977 Hunsperger et al. ................ 148/ 1.5
`4,241,359 12/1980 Izumi et al ............................ 357/49
`4,394,180 7/1983 Deamaley et al. .................. 148/1.5
`4,452,646 6/1984 Zuleeg ................................. 148/1.5
`4,704,302 11/1987 Bruel et al. ........................... 427/38
`
`FOREIGN PATENT DOCUMENTS
`2581795 11/1986 France .................................. 437/24
`0031971 3/1978 Japan ..................................... 437/61
`0059090 5/1979 Japan ..................................... 437/24
`
`llli~IIHIIIIMRIID
`US005080730A
`[11] Patent Number:
`(45] Date of Patent:
`
`5,080,730
`Jan. 14, 1992
`
`020885 I 11/ 1984 Japan ..................................... 437/62
`
`OTHER PUBLICATIONS
`"Sputter Etch Removal Rates of Insulators, Semicon·
`ductors, and Conductors", Larry L. Fritz, Solid State
`Technology, Dec. 1971, pp. 43-48.
`"Nucleation and Growth of Si02 Precipitates in SOV(cid:173)
`SIMOX Related Materials- Dependence Upon Damage
`and Atomic Oxygen Profll~s", Nuclear instruments and
`methods in Physics research, Section B (Beam interac(cid:173)
`tions with materials and Atoms) Mar. 1989, vol. B39,
`No. 1-4, Hemment et al., pp. 210-214.
`·
`Primary Examiner-Olik Chaudhuri
`Assistant Examiner-Ourmafd Ojan
`Allomey, Agent, or Firm-Weingarten, Schurgin,
`Gagnebin & Hayes
`ABSTRACf
`[57]
`An ion implantation process for producing a buried
`insulating layer of silicon dioxide in a silicon substrate
`which takes advantage of the effects of surface erosion
`and sputtering inherent to the ion implantation process.
`The process a!Jows the production of an insulating layer
`buried within a silicon semiconductor wherein the
`width of the insulating layer can be contoured by con(cid:173)
`trolling the beam energy during implantation.
`
`8 Claims, 3 Drawing Sheets
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`U.S. Patent
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`Jan. 14, 1992
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`Sheet 1 of 3
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`5,080,730
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`U.S. Patent
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`Jan. 14, 1992
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`Sheet 2 of 3
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`5,080,730
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`11
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`BEAN SOURCE
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`FIG . . 3A
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`U.S. Patent
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`Jan. 14, 1992
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`Sheet 3 of 3
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`5,080,730
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`1
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`5,080,730
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`IMPLANTATION PROFILE CONTROL WITH
`SURFACE SPUTIERING
`
`FIELD OF THE INVENTION
`This invention relates to a process used in semicon(cid:173)
`ductor production and, more particularly, relates to a
`process for contouring an insulating layer formed in a
`semiconductor substrate by ion implantation.
`BACKGROUND OF THE INVENTION
`Ion implantation is a process in which atomic parti(cid:173)
`cles are introduced into a substrate for the purpose of
`changing the electrical or chemical properties of the
`substrate. This process uses high energies to accelerate 15
`ions which enter the surface and are slowed down by
`electronic or nuclear collisions with the substrate
`atoms, and come to rest some small distance below the
`surface. Modem semiconductor technology is one field
`in which ion implantation is particularly useful and 20
`wherein implanted ions are used to alter the conductiv-
`ity of the base material as well as to form buried insulat(cid:173)
`ing layers. One object, in the case of buried insulating
`layers, is the minimization of the volume of electrically
`active semiconductor material to reduce parasitic ef- 25
`fects such as device-to-device effects (known as latch(cid:173)
`up), leakage capacitance, resistance, etc. and to mini(cid:173)
`mize sensitivity to radiation.
`In the early 1980's, a process known as separation by
`implanted oxygen or SIMOX was developed in which a 30
`high-dose of oxygen ions are implanted into a solid
`monocrystalline silicon substrate, making it possible to
`form a buried layer of silicon dioxide SiOz). The resul(cid:173)
`tant layer dielectrically isolates circuit elements, en(cid:173)
`abling the fabrication of smaller, closer and faster cir- 35
`cuits which are immune to the noted parasitic and radia(cid:173)
`tion effects which cause latch-up and add to circuit
`capacitance.
`Using the SIMOX process, oxygen ions are implanted
`into silicon at a constant beam energy between 150 and 40
`200 keV at a dose of approximately 1.6 X tots
`ions/cm2. After implantation, the material is annealed
`to form the chemically bonded silicon dioxide. A typi(cid:173)
`cal anneal cycle involves heating the substrate to ap(cid:173)
`proximately 1300 degrees for six hours. This annealing 45
`phase redistributes the oxygen ions which are implanted
`in a roughly Gaussian profile with respect to the most
`probable depth (range) such that the silicon/silicon
`dioxide boundary on either side of the silicon dioxide
`layer becomes markedly more abrupt, thus forming a 50
`sharp and well-defmed region centered at the most
`probable depth.
`During implantation, incoming high-speed oxygen
`ions sputter silicon ions from the surface resulting in
`surface erosion. Due to the effect of this surface erosion, ss
`the original surface of the silicon layer is displaced,
`causing ions implanted toward the end of the implant
`cycle to come to rest at a depth deeper than ions im(cid:173)
`planted at the start of the implant cycle. In practice, this
`erosion effect is magnified when a surface layer of sili- 60
`con dioxide is provided to protect surface features be(cid:173)
`cause silicon dioxide erodes more rapidly than silicon
`during implantation. As a result of the variation in im(cid:173)
`plantation depth of oxygen ions, a broader band of sili(cid:173)
`con oxide layer is created. This, in tum, increases the 65
`minimal acceptable dose of oxygen ions required to
`create the silicon dioxide layer, thereby causing even
`greater surface damage and longer processing times.
`
`2
`SUMMARY OF THE INVENTION
`The present invention relates to a process for produc(cid:173)
`ing a buried insulating layer, typically of silicon dioxide
`S (SiOz) or silicon nitride (Si3N4), within a silicon sub(cid:173)
`strate in a manner which advantageously regulates the
`implantation energies in response to the surface erosion
`to produce a thinner, low dosage insulating layer suit(cid:173)
`able for typical low voltage use, or a thicker, more even
`10 layer in a semiconductor substrate wherein the thick(cid:173)
`ness of the buried insulative layer is determined by
`controlling the beam energy used to implant ions into
`the silicon layer as a function of surface erosion. The
`silicon layer erodes at a rate which is dependent on the
`density of the ions being implanted into the silicon. The
`peak ion distribution is maintained at a constant position
`by reducing the beam energy and corresponding pene(cid:173)
`tration by an amount corresponding to the depth of
`erosion. This more rapidly achieves the ion density
`required to fully form an oxide barrier with less expo(cid:173)
`sure of the substrate to ion implantation effects. The
`oxide barrier thus formed, while thinner, provides pro(cid:173)
`tection for most semiconductor applications which are
`typically low voltage applications.
`Conversely, by increasing the beam energy over the
`implantation period, the peak of the ion implantation
`distribution occurs at progressively deeper depths, ad(cid:173)
`vantageously benefited by the surface erosion which
`allows the distribution to shift naturally. In this case, the
`oxide barrier is formed over a greater depth to provide
`additional insulative protection in high voltage applica-
`tions.
`The process for producing a buried insulating layer
`according to the present invention is advantageous for
`producing an active component of an integrated circuit
`positioned on crystalline silicon material above an insu-
`lating layer. This technique produces a radiation hard(cid:173)
`ened material and also dielectrically isolates circuit
`elements enabling smaller, closer and faster circuits to
`be fabricated with a marked reduction in stray capaci(cid:173)
`tance and an increase in the operating speed of the cir-
`cuits. Additionally, the material shows great promise
`for mixed application such as BI-CMOS circuits which
`combine power and logic on the same chip.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention will be more fully understood from the
`following detailed description taken in conjunction
`with the accompanying drawings in which:
`Figs. lA to lB are diagrammatic representations
`showing a prior art ion implantation process for produc(cid:173)
`ing a buried insulating layer in a semiconductor sub(cid:173)
`strate at different stages in the process;
`FIG. lC is a graph of ion concentration with respect
`to the depth of deposition according to the prior art;
`FIG. 2A is a diagrammatic representation of a modi(cid:173)
`fied ion implantation process for producing a narrowed
`buried insulating layer according to a first embodiment
`of the invention;
`FIG. 2B is an energy profile diagram showing the
`energy tapering according to the first embodiment of
`the invention;
`FIGS. 3A and 3B are graphs showing the Gaussian
`distribution of the ions with respect to the distance from
`the top face of the silicon layer in the first embodiment
`of the invention;
`FIG. 4A is a diagrammatic representation of ion im(cid:173)
`plantation for producing a widened buried insulating
`
`005
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`3
`layer according to a second embodiment of the inven(cid:173)
`tion;
`FIG. 4B is an energy profile diagram showing energy
`increasing with time according to the second embodi(cid:173)
`ment of the invention; and
`FIG. 5 is a graph showing the Gaussian distribution
`of the ions with respect to distance from the top face of
`the silicon layer in the second embodiment of the inven(cid:173)
`tion.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`The present invention contemplates energy control
`during oxygen or nitrogen ion implantation to produce
`a narrowed or a widened insulating layer in a silicon 15
`substrate. According to the prior art, as shown in FIG.
`1A, an initially uniform silicon layer 10 is bombarded
`with oxygen ions generated by a beam source 16
`wherein the oxygen ions travel through the silicon crys-
`tal structure 10 and come to rest in the crystal matrix of 20
`silicon atoms. Since the purpose of the implantation
`process is to create a buried layer of silicon dioxide
`(Si02), two oxygen atoms are implanted for each silicon
`atom to achieve the appropriate chemical structure.
`The oxygen ions come to rest as a broadened band 14 25
`buried in the silicon in a roughly Gaussian distribution
`with respect to depth where the depth is dependent
`upon the ion beam energy used to project the oxygen
`atoms into the silicon layer. Annealing subsequently
`forms a silicon dioxide layer having sharpened bound- 30
`aries.
`FIG. 1B shows the surface erosion resulting from the
`oxygen implantation on the silicon layer 10. The dotted
`line 18 represents the original top face of the silicon
`layer before ion implantation. As ions are bombarded 35
`against the surface of the silicon, the top face 18 of the
`silicon layer 12 is eroded or sputtered such that the top
`of the silicon layer progressively retreats toward a
`lower level 20. The effect of the erosion is that ions
`implanted in the course of an implant cycle come to rest 40
`at progressively deeper depths within the silicon layer
`and farther from the original top face 18 than the ions
`implanted at the start of the implant cycle.
`FIG. 1B also shows an additional characteristic of the
`prior art ion implantation process in that small islands 45
`22 of silicon dioxide may be formed in layer 14 and just
`above due to ions which are deposited in the tail of the
`Gaussian distribution to form a chemical bond outside
`of the sharpened Gaussian distribution formed during
`annealing. This is an undesirable phenomenon which 50
`alters the electrical conductivity characteristics of the
`silicon semiconductor layer.
`FIG. 1C shows the broadened Gaussian distribution
`of oxygen ions that would result from an ion implanta(cid:173)
`tion using constant. Under this prior art arrangement, it 55
`can be seen that the ion concentration is distributed
`over a broad Gaussian depth distribution 30.
`In simunary, the net effect of this surface erosion is
`that the distribution of ions is spread over a wide range
`which causes the buried silicon dioxide layer to be 60
`thicker and also creates islands of silicon dioxide depos-
`its outside of the insulating layer to be formed. Addi(cid:173)
`tionally, the minimum acceptable dose of ions necessary
`to create a quality insulating layer is high since the
`chemical bonding of the insulating layer must be 65
`achieved over a broader range.
`The present invention is adapted to controllably re(cid:173)
`duce or increase the beam energy during ion implanta-
`
`5,080,730
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`4
`tion. Such controlled variation in beam energy permits
`specific contouring of the width of the buried insulator
`layer band. Moreover, by compensating for the known
`effects of surface erosion, greater regulation of the im-
`5 plantation process is achieved.
`FIG. 2A is a diagramatic sectional view of a first
`embodiment of the present invention wherein the ap(cid:173)
`plied beam energy from source 16 is controllably de(cid:173)
`creased by an energy control17 to decrease the implan-
`10 tation depth such that the peak of the ion distribution is
`maintained at the same depth despite the existence of
`surface erosion. Thus, after annealing, a buried 9 silicon
`dioxide layer 24 forms as a thin strata of insulating mate-
`rial which dielectrically separates the former silicon
`semiconductor 10 into two newly formed layers 28 and
`26. The energy decrease with time and ion sputtering is
`shown in FIG. 2B.
`FIG. 3A shows the effect of reducing beam energy
`with time, as surface 18 is eroded to a surface 20'. In
`FIG. 3B a three dimensional graph shows the roughly
`Gaussian distribution proflles 34a, b, c, d which repre-
`sent the ion concentration at different times as the beam
`energy is decreased during the implantation cycle. By
`using ion beam energy control to perform this energy
`reduction, it can be seen that the peak ion concentration
`can be limited to a very narrow range 32 within the
`silicon substrate as the surface 18 gradually recedes due
`to erosion thereof.
`As an illustration of the first embodiment of the pres(cid:173)
`ent invention, a beam energy of 150 keV will erode
`silicon at a rate of approximately 34/1017 ions/cm2.
`Further, it is inherent in this ion implantation process
`that ions are implanted at a peak depth of approximately
`19 A!keV. Thus, the depth of the peak of the ion distri(cid:173)
`bution can be maintained at a constant level by reducing
`the implant voltage by approximately 1.8 keV /1017
`ions/cm2 applied. For example, if a normal dose of ions
`is approximately 1.6 X 1Q18 ions/cm2, a controlled re(cid:173)
`duction of approximately 28.8 keV over the period of
`implantation will result in a constant peak depth distri(cid:173)
`bution at a level approximately 2850 A below the origi-
`nal top face of the silicon layer: This embodiment also
`allows processing time to be reduced from approxi(cid:173)
`mately five hours to approximately four hours.
`In a second embodiment of the present invention, as
`shown in FIG. 4A, and using the same relationships
`regarding erosion rate and peak depth, the process de(cid:173)
`scribed above is altered to form a thicker silicon dioxide
`band 40 by controllably increasing the beam energy
`used to implant ions. An increase in the beam energy, as
`illustrated in FIG. 4B, advantageously positions the
`peak distribution of ions at increasingly greater depths
`due to the combined effects of the increase in beam
`energy plus the surface erosion. For example, by in(cid:173)
`creasing the beam energy from 150 keV to 170 keV
`over the course of an implantation cycle, the peak distri-
`bution depth of the implanted ions is increased from a
`level 2850 A below the original top face of the silicon
`layer to a level 3230" A below the eroded top face of the
`silicon layer. At a dose of 1.6 X 1Q18 ions/cm2, this
`eroded top face sits at a level 544 A lower than the
`original top face. Thus, the peak distribution of ions lies
`in a band ranging from 2850 A to 3774 A below the
`original top face of the silicon layer.
`This second embodiment of the invention is further
`illustrated in FIG. 5 which shows the progressively
`deeper distribution curves in which the ions are im(cid:173)
`planted. This creates a far wider range 36 of distribution
`
`006
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`5,080,730
`
`5
`and a far wider insulating layer. This wide insulating
`layer supports a higher voltage for high voltage appli(cid:173)
`cations.
`While the invention has been illustrated for oxygen
`implantation, it is to be understood that nitrogen or
`other implantable ions may be substituted. It will fur(cid:173)
`ther be appreciated that the embodiments described are
`illustrative only and are not to limit the invention, the
`scope of which is defined only in t.he following claims. 10
`I claim:
`1. A process for producing a buried insulation form(cid:173)
`ing implant layer disposed within a silicon substrate,
`comprising the steps of:
`implanting ions into a silicon substrate, from a source 15
`of controllable ion energy;
`simultaneously eroding a surface layer of said silicon
`substrate through which said implanting ions pass;
`and
`reducing the ion energy in compensation for erosion
`occurring in said eroding step to reduce the depth
`of ion penetration with respect to the surface ero(cid:173)
`sion of said substrate.
`2. The process of claim 1 wherein the silicon is of 25
`semiconductor grade.
`
`6
`3. The process of claim 1 wherein the implant is se(cid:173)
`lected from the group comprising oxygen and nitrogen.
`4. The process of claim 1 further including the step of
`annealing said substrate to create a continuous insulat-
`5 ing layer from the implant layer.
`5. A process for producing a buried insulation form(cid:173)
`ing implant layer disposed with a silicon substrate, com(cid:173)
`prising the steps of:
`implanting ions into a silicon substrate from a source
`of controllable ion energy;
`simultaneously eroding a surface layer of said silicon
`substrate through which said implanting ions pass;
`and
`increasing the ion energy in compensation for erosion
`occurring in said eroding step to increase the depth
`of ion penetration with respect to the surface ero-
`sion of said substrate.
`·
`6. The process of claim 5 wherein the silicon is semi(cid:173)
`conductor grade.
`7. The process of claim 5 wherein the implant is se(cid:173)
`lected from the group consisting of oxygen and nitro(cid:173)
`gen.
`8. The process of claim 5 which further includes the
`steps of annealing said substrate to create a continuous
`insulating layer from the implant layer.
`* * * * *
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`007
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`

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`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`: 5, 080,730
`PATENT NO.
`January 14, 1992
`DATED
`INVENTOR(S) : Andrew B. Wittkower
`It is certified that error appears in the above·identified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`Page 1 of 2
`
`On the Title page, item [ 56 ] , above the Abstract,
`Examiner-Ourmafd Ojan" should read ·· --Assistant
`Ourmazd Ojan--.
`
`"Assistant
`Examiner-
`
`Column 1, line 33, "dioxide Si02) 11 should read
`--dioxide (Si02) - - .
`Column 2, line 43, "application" should read
`--applications--.
`
`Column 3, line 55, "using constant" should read --using
`the prior art of Figs. 1A-1B where the beam energy remains
`constant--.
`
`Column 4, line 6, "diagramatic" should read
`--diagrammatic--.
`
`Column 4, line 12, "buried 9 silicon" should read
`--buried silicon--.
`
`Column 4, line 31, 1134/1017 ions/crn2" should read
`--34A/1017 ions/cm2
`- - .
`
`Column 4, line 37, "ions/crn2 applied. For" should read
`--ionsfcm2• For--.
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`: 5, 080, 7 30
`PATENT NO.
`January 14, 1992
`DATED
`INVENTOR(S) : Andrew B. Wi ttkower
`
`Page 2 of 2 .
`
`It is certified that error appears in the above-identifie(f'patent and that said Letters Patent is hereby
`corrected as shown below:
`
`Column 6, line 24, "s teps" shoul d read --s t ep--.
`
`Signed and Sealed this
`
`Twentieth Day of July, 1993
`
`Attest:
`
`Attesting Officer .
`
`Acting Commissioner of Patents and Trademarks
`
`MICHAEL K. KI.RK