United States Patent !191
`Miura et al.
`
`(11] Patent Number:
`(4~] Date of Patent:
`
`5,066,993
`Nov. 19, 1991
`
`[54] SEMICONDUCTOR DEVICE HAVING
`SEMICONDUCTOR-ON-INSULATOR
`STRUCTURE
`
`[7~) Inventors: Takao Miura, Tokyo; Kazunori
`Imaok.a, Komae, both of Japan
`
`[73] Assignee: Fujitsu Um.itecl, Kawasaki, Japan
`
`[22] Filed:
`
`(21) Appl. No.: 447,524
`Dec. 7, 1989
`Foreign Application Priority Data
`(30]
`Dec. 8, 1988 [JP]
`Japan ................................ 63·310458
`
`[5 1]
`Int. a.s ............................................. HOIL 29178
`[52] u.s. a ........................................ 357/ 23.7; 357/2;
`357/4; 357/23.45
`[58) Field of Search ....................... 357/23.7, 23.15, 2,
`357/ 4
`
`[56}
`
`Re.ferences Cited
`U.S. PATENT DOCUMENTS
`4,297,782 11/1981 Ito .................................... 3S0/23.1~
`4,758,529 7/1988
`Ipri ..................................... 357/23.7
`4,778,773 10/1988 Sukegawa .......................... 357/ 23.7
`4,788,1 57 11/1988 Nakamura .......................... 357/23.7
`4,8 10,664 3/1989 Kamins eta! ...................... 357/23.7
`4,864,377 9/1989 Widdershoven ................... 357/23.7
`4,880,753 I 1/1989 Meakin et al ...................... 357/23.7
`
`FOREIGN PATENT DOCUMENTS
`26570 3/1969 Japan .
`186612 8/ 1989 Japan .
`
`OTHER PUBLICATIONS
`Wang et al., "The Effect of Ion Implantation on Oxide
`Charge in MOS Devices", IEEE Transactions on Nu·
`clear Science, vol. NS-22, No. 6, D ec. 1975 Merely
`
`Relates to Studies on Electron Traps Introduced into
`the Oxide by Implantation of AI+ ions.
`Curtis, Jr., et al., "Physical Mechanisms of Radiation
`Hardening of MOS Devices by Ion Implantation",
`IEEE Transactions on Nuclear Science, vol. NS-22,
`No. 6, Dec. 1975 Simply Relates to Studies on AI·
`+ Ion-Implanted MOS Capacitors.
`DiMaria et al., "Location of Trapped Charge in
`Aluminium-Implanted Si02", IBM J. Res. Develop.
`vol. 22, No.3, May 1978.
`.
`Young et al., "Characterization of Electron Traps in
`Aluminum-Implanted SiC!", IBM J. Res. Develop.
`vol. 22, No. 3, May 1978 Merely Relate to Studies on
`Electron Trapping Behavior of Si02 Implanted with
`Al.
`Lasky et al., "Silicon-On-Insulator (SOl) by Bonding
`and Etch- Back", IEDM 85, pp. 684-687 1985.
`Hamaguchi et al., "Novel LSI/SOl Wafer Fabrication
`Using Device Layer Transfer Technique", lEDM 85,
`pp. 688-691 1985 Simply Relate to Studies on SOl
`Structions.
`Primary Examiner-Rolf Hille
`Assistant Examiner- Tan Ho
`Auorney, Agent, or firm-Staas & Halsey
`[57]
`ABSTRACT
`A method of producing a semiconductor-on-insulator
`structure generates a first fixed charge in an insulator
`layer of a base substrate. A n active substrate which is
`made of a semiconductor is bonded on the insulator
`layer of the base substrate to thereby generate a second
`flXed charge at an interface of the insulator layer and the
`active substrate. The first and second fixed charges
`have mutually opposite polarities. A portion of the
`active substrate is removed to form the active substrate
`to an arbitrary thickness.
`
`8 Oaims, 9 Drawina Sheets
`
`001
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`SONY 1012
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`

`
`U.S. Patent
`
`Nov. 19, 1991
`
`Sheet 1 of 9
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`5,066,993
`
`FIG. IA
`PRIOR ART
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`U.S. Patent
`
`Nov. 19, 1991
`
`Sheet 2 of 9
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`5,066,993
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`U.S. Patent
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`Nov. 19, 1991
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`Sheet 3 of 9
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`U.S. Patent
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`Nov. 19, 1991
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`U.S. Patent
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`Nov. 19, 1991
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`U.S. Patent
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`Nov. 19, 1991
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`Sheet 7 of 9
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`U.S. Patent
`
`Nov. 19, 1991
`
`Sheet 8 of 9
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`5,066,993
`
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`
`U.S. Patent
`
`Nov. 19, 1991
`
`Sheet 9 of 9
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`5,066,993
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`
`1
`
`5,066,993
`
`SEMICONDUCTOR DEVICE HAVING
`SEMICONDUCTOR-ON-INSULATOR
`STRUCTURE
`
`2
`such as boron (B) is injected into the interface on the
`side of the active substrate 41, so as to prevent the gen(cid:173)
`eration of negative charges in the active substrate 41.
`However, according to the method shown in FIG. 3,
`5 there is a problem in that a control device for control(cid:173)
`BACKGROUND OF THE INVENTION
`ling the semiconductor device becomes bulky and com(cid:173)
`plex because of the need to add the voltage source 44
`The present invention generally relates to methods of
`producing semiconductor-on-insulator structures and
`for applying the negative voltage to the base substrate
`semiconductor devices having the semiconductor-on(cid:173)
`40. For example, in the case of a complementary metal
`insulator structure, and more particularly to a method 10
`oxide semiconductor (CMOS) device, there is a need to
`of producing a semiconductor-on-insulator structure
`provide two bias voltages for the p-channel n-channel
`such as a silicon-on-insulator (SOl) structure and a
`transistors.
`semiconductor device having such a semiconductor-on(cid:173)
`On the other hand, according to the method shown in
`insulator structure.
`FIG. 4, there is a problem in that it is difficult to adjust
`The SOl technology wa~ proposed as a method of 15
`a threshold voltage of the MOSFET due to the injected
`forming an insulator layer between two single crystal
`impurity ions. In addition, there is also a problem in that
`semiconductor layers for the purpose of producing
`the p-type impurity a diffuses into the active substrate
`high-speed elements and semiconductor devices which
`41 and varies the threshold voltage of the gate g when
`are uneasily affected by alpha-rays. As methods of pro(cid:173)
`a thermal process is carried out to form elements on the
`ducing the SOl structure, there are the silicon on sap- 20
`active substrate 41. Hence, it is virtually impossible to
`phire (SOS) technique, the laser melt technique, the
`make an active substrate which is sufficiently thin and
`wafer bonding technique and the like. However, ac(cid:173)
`does not contain the diffused p-type impurity a.
`cording to the SOS technique and the laser melt tech(cid:173)
`nique, it is difficult to form a perfect single crystal layer
`In order to eliminate the above described problems, a
`on the insulator layer. For this reason, there is much 25
`bonding method was proposed in a Japanese Laid-Open
`attention on the wafer bonding technique.
`Patent Application No. 1-186612. According to this
`FIGS. 1A and 1B are diagrams for explaining a con(cid:173)
`proposed method, the SOl structure is formed as shown
`ventional bonding technique. As shown in FIG. 1A, the
`in FIGS. SA through SE. The surface of an active sub(cid:173)
`surface of one of a base substrate 40 and an active sub(cid:173)
`strate 51 is covered by a Si02layer 53 as shown in FIG.
`strate 41 is covered by a silicon dioxide (Si02) layer 42. 30
`SA. On the other hand, the surface of a base substrate 61
`In this example, the Si02 layer 42 covers the base sub(cid:173)
`is covered by a Si02layer 63 as shown in FIG. SB. The
`strate 40. The active substrate 41 is bonded on the base
`thickness of the Si02layer 63 is greater than that of the
`substrate 40 having the Si02layer 42 as indicated by an
`Si02layer 53. A negative fixed charge nfc is formed in
`arrow. Thereafter, the active substrate 41 is subjected to
`the Si02layer 53 by injecting aluminum (Al) ions or the
`lapping and polishing processes so as to remove a por- 35
`like as shown in FIG. SC. Then, as shown in FIG. SD,
`tion of the active substrate 41 indicated by a phantom
`the active substrate 51 and the base substrate 61 are
`line in FIG. lB. As a result, the remaining active sub(cid:173)
`bonded together so that the Si02 layer 63 of the base
`strate 41 on the Si02layer 42 of the base substrate 40 has
`substrate 61 makes contact with the Si02layer 53 which
`a thickness of approximately 5 microns.
`has the negative fixed charge nfc. As a result, the posi(cid:173)
`When using the SOl structure shown in FIG. lB to 40
`tive charge within the Si02layer 53 is eliminated. The
`make a metal oxide semiconductor field effect transistor
`(MOSFET), a gate electrode g of the MOSFET is
`structure shown in FIG. SD is then formed into the
`formed on the base substrate 40 via an insulator layer 43
`structure shown in FIG. SE by polishing the top portion
`as shown in FIG. 2. Then, two n-type regions are
`of the active substrate 51.
`formed in the active substrate 41 to form a source s and 45
`But according to this proposed method, the Si02
`a drain d of the MOSFET.
`layer 53 is formed on the active substrate 51 by a ther-
`But molecules which lack oxygen such as SiO and
`mal oxidation, and the formed Si02Jayer 53 only has a
`thickness in the range of 0.4 micron to 1.0 micron. For
`Si203 molecules exist within the Si02layer 42 which is
`this reason, when the Al ions are injected into the Si02
`provided between the base substrate 40 and the active
`substrate 41. For this reason, a positive interface state 50 layer 53 at a high energy, the AI ions easily penetrate
`the Si02 layer 53 and reach the active substrate 51.
`occurs at the Si02 interface, and an inversion and a
`depletion state easily occur at the interface on the side When the AI ions are injected into the active substrate
`of the active substrate 41. When such inversion and
`51, there are problems in that the characteristics of
`depletion state occur, an electron transition naturally
`elements such as transistors formed on the active sub-
`occurs between the source s and the drain d of the 55
`MOSFET and causes an erroneous operation of the
`strate 51 change and the performance of the semicon-
`MOSFET.
`ductor device becomes poor. These problems become
`In order to prevent the above described erroneous
`notable especially when the active substrate 51 is made
`operation of the MOSFET, it is necessary to prevent
`thin since a large portion of the active substrate 51 is
`the inversion and depletion state from occurring in the 60 damaged by the AI ions which penetrated the Si02layer
`53.
`Si02 layer 42.
`FIG. 3 shows one conventional method of preventing
`In order to prevent the AI ions from penetrating the
`Si02 layer 53, it is possible to consider reducing the
`the inversion and depletion state from occurring in the
`Si02layer 42. In FIG. 3, a negative voltage is applied to
`energy at which the AI ions are injected. To prevent the
`the base substrate 40 from a voltage source 44.
`65 penetration of the AI ions, the energy must be reduced
`FIG. 4 shows another conventional method. of pre-
`to 10 keV or less, but at such a small energy the injec-
`venting the inversion and depletion state from occur-
`tion coefficient becomes greatly reduced and it becomes
`ring in the Si02layer 42. In FIG. 4, a p-type impurity a
`difficult to adjust the ion injection quantity.
`
`011
`
`

`
`25
`
`3
`SUMMARY OF THE INVENTION
`Accordingly, it is a general object of the present
`invention to provide a novel and useful method of pro(cid:173)
`ducing a semiconductor-on-insulator structure and a 5
`semiconductor device having such a semiconductor-on(cid:173)
`insulator structure, in which the problems described
`above are eliminated.
`Another and more specific object of the present in(cid:173)
`vention is to provide a method of producing a semicon- I 0
`ductor-on-insulator structure comprising the steps of
`generating a first fixed charge in an insulator layer of a
`base substrate, bonding an active substrate which is
`made of a semiconductor op the insulator layer of the
`base substrate, thereby generating a second fixed charge 15
`at an interface of the insulator layer and the active sub(cid:173)
`strate, where the first and second fixed charges have
`mutually opposite polarities, and removing a portion of
`the active substrate to form the active substrate to an
`arbitrary thickness. According to the method of the 20
`present invention, it is possible to effectively prevent
`the back channel and provide an active substrate which
`can be used to form elements which have designed
`characteristics. Further, the bonding strength between
`the active substrate and the insulator layer is large and
`extremely satisfactory.
`Still another object of the present invention is to
`provide a method of producing a semiconductor-on(cid:173)
`insulator structure comprising the steps of generating a 30
`first fixed charge in a first insulator layer of a base sub(cid:173)
`strate, bonding an active substrate which is made of a
`semiconductor and has a second insulator layer on the
`base substrate so that the first and second insulator
`layers make contact with each other, thereby generat- 35
`ing a second fixed charge at an interface of the second
`insulator layer and the active substrate, where the first
`and second fixed charges having mutually opposite
`polarities, and removing a portion ofat least the active
`substrate to form the active substrate to an arbitrary 40
`thickness. According to the method of the present in(cid:173)
`vention, it is possible to effectively prevent the back
`channel and provide an active substrate which can be
`used to form elements which have designed characteris-
`tics.
`A further object of the present invention is to provide
`a semiconductor-on-insulator structure comprising a
`base substrate having an insulator layer at least on a
`surface portion thereof, where the insulator layer in(cid:173)
`cludes impurities which are distributed with a predeter- 50
`mined density distribution in which an impurity density
`is dependent on a distance from a surface of the insula(cid:173)
`tor layer and having a first fixed charge and a surface
`portion of the insulator layer has an impurity density
`which corresponds approximately to a maximum impu- 55
`rity density in the predetermined density distribution,
`an active substrate which is made of a semiconductor
`and is bonded on the insulator layer of the base sub(cid:173)
`strate, thereby generating a second fixed charge at an
`interface of the insulator layer and the active substrate, 60
`where the first and second fixed charges have mutually
`opposite polarities. According to the semiconductor(cid:173)
`on-insulator structure of the present invention, it is
`possible to effectively prevent the back channel and
`provide an active substrate which can be used to form 65
`elements which have designed characteristics. Further,
`the bonding strength between the active substrate and
`the insulator layer is large and extremely satisfactory.
`
`45
`
`5,066,993
`
`4
`Another object of the present invention is to provide
`a semiconductor-on-insulator structure comprising a
`base substrate having a first insulator layer at least on a
`surface portion thereof, where the first insulator layer
`includes impurities which are distributed with a prede(cid:173)
`termined density distribution in which an impurity den(cid:173)
`sity is dependent on a distance from a surface of the first
`insulator layer and having a first fixed charge and a
`surface portion of the first insulator layer has an impu(cid:173)
`rity density which corresponds approximately to a max(cid:173)
`imum impurity density in the predetermined density
`distribution, an active substrate which is made of a
`semiconductor and having a second insulator layer,
`where the active substrate is bonded on the base sub(cid:173)
`strate so that the first and second insulator layers make
`contact with each other, thereby generating a second
`fixed charge at an interface of the second insulator layer
`and the active substrate, and the first and second fixed
`charges have mutually opposite polarities. According
`to the semiconductor-on-insulator structure of the pres(cid:173)
`ent invention, it is possible to effectively prevent the
`back channel and provide an active substrate which can
`be used to form elements which have designed charac(cid:173)
`teristics.
`Other objects and further features of the present in(cid:173)
`vention will be apparent from the following detailed
`description when read in conjunction with the accom(cid:173)
`panying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1A and 1B are cross sectional views for ex(cid:173)
`plaining a conventional bonding technique;
`FIG. 2 is a cross sectional view showing an example
`of a MOSFET which uses the SOl structure shown in
`FIG. 1B;
`FIG. 3 is a cross sectional view for explaining one
`conventional method of preventing the inversion and
`depletion state from occurring in a Si02 layer;
`FIG. 4 is a cross sectional view for explaining another
`conventional method of preventing the inversion and
`depletion state from occurring in a Si02 layer;
`FIGS. SA through SE are cross sectional views for
`explaining a proposed method of forming a SOl struc(cid:173)
`ture;
`FIGS. 6A through 6F are cross sectional views for
`explaining a first embodiment of a method of producing
`a semiconductor-on-insulator structure according to the
`present invention;
`FIG. 7 is a graph for explaining diffusion of AI in a
`Si02layer;
`FIGS. 8A through SC show data for explaining bond(cid:173)
`ing states of Si021Si, Si/Si and Si02fSi02, respectively;
`FIGS. 9A through 9E are cross sectional views for
`explaining a second embodiment of the method of pro(cid:173)
`ducing a semiconductor-on-insulator structure accord(cid:173)
`ing to the present invention;
`FIG. 10 is a cross sectional view showing the the
`semiconductor-on-insulator structure which
`is pro(cid:173)
`duced by the second embodiment on an enlarged scale;
`FIG. 11 is a cross sectional view showing a MOS(cid:173)
`FET which is formed by use of the semiconductor-on(cid:173)
`insulator structure shown in FIG. 10;
`FIGS. 12A through 12C are cross sectional views for
`explaining a third embodiment of the method of produc(cid:173)
`ing a semiconductor-on-insulator structure according to
`the present invention; and
`FIG. 13 is a cross sectional view for explaining a
`modification of the first embodiment of the method of
`
`012
`
`

`
`5
`producing an embodiment of the semiconductor-on(cid:173)
`insulator structure according to the present invention.
`
`5
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`A description will be given of a first embodiment of
`the method of producing a semiconductor-on-insulator
`structure according to the present invention, by refer(cid:173)
`ring to FIGS. 6A through 6F. FIG. 6A shows an active
`substrate 14 which is made of a p-type silicon (Si), and 10
`FIG. 6B shows a base substrate 12 which is made of a
`p-type or n-type Si. The base substrate 12 is subjected to
`a thermal oxidation to form a Si02 layer 13 on the sur(cid:173)
`face of the base substrate 12 as shown in FIG. 6C. For
`example, the Si02layer 13 has a thickness in the range 15
`of 0.5 micron to 2.0 microns.
`Next, aluminum (AI) ions are injected on one surface
`of the Si02 layer 13 as shown in FIG. 6D so as to gener(cid:173)
`ate a negative fixed charge nfc within the Si02layer 13.
`The active substrate 14 is then bonded onto the base 20
`substrate 12 so that the surface of the active substrate 14
`makes contact with the Si02 layer 13 which has the
`negative fixed charge nfc as shown in FIG. 6E. There(cid:173)
`after, the active substrate 14 is polished to a desired
`thickness as shown in FIG. 6F. For example, the de- 25
`sired thickness is in the range of 0.1 micron to 10 mi(cid:173)
`crons.
`In FIG. 6F, the positive charge is generated at the
`interface between the active substrate 14 and the Si02
`layer 13, because no AI ions diffuse into the active sub- 30
`strate 14. As a result, the inversion and depletion state
`are prevented from occurring at the interface of the
`active substrate 14 and the Si02 layer 13. The effect of
`preventing a back channel is large because there is no
`Si02 layer covering the active substrate 14 which 35
`would affect the field of the Si02 layer 13.
`FIG. 7 shows a graph for explaining diffusion of AI in
`the Si02 layer 13. In FIG. 7, the ordinate indicates the
`AI density and the abscissa indicates the depth of the
`Si02 layer 13 by taking the surface of the Si02 layer 13 40
`which makes contact with the active substrate 14 as
`zero depth. A curve I is obtained by AI ion implantation
`to the Si02 layer 13 which has a thickness of 400 nm at
`an injection energy of 90 keV, an injection density of
`1 X l015cm-2and an injection angle of7'. A curve II is 45
`obtained after an annealing step which is carried out in
`an nitrogen (N2) gas at 1050' C. for 600 minutes. As may
`be seen from FIG. 7, the curves I and II and approxi(cid:173)
`mately the same, and it is confirmed that the AI ions
`within the Si02 layer 13 do not diffuse into the active 50
`substrate 14 even after the annealing step is carried out.
`The active substrate 14 is bonded onto the Si02 layer
`13 by a thermal process. FIG. 8A shows a bonding
`strength between a Si02layer and the Si layer. The data
`is obtained for the Si02 layer which has a thickness of 55
`500 nm and the thermal process is carried out in a N2 gas
`for 2 hours. A first sample is made up of a Si substrate
`and a Si02 layer formed on one surface of the Si sub(cid:173)
`strate. A second sample is made up of a Si substrate. The
`first and second samples are bonded so that the Si02 60
`layer of the first sample makes contact with one surface
`(Si layer) of the second sample. The data is obtained by
`fixing the free (Si) surface of the first sample on a first
`base by an epoxy adhesive agent, fixing the free (Si)
`surface of the second sample on a second base by an 65
`epoxy adhesive agent, and pulling at least on~ of the
`first and second bases so as to separate them from each
`other. The black circular marks indicate a separation
`
`5,066,993
`
`6
`which occurs at the interface of the Si02layer and the
`Si layer, and white circular marks indicate a separation
`which occurs at the interface of the Si layer and the
`epoxy adhesive agent.
`FIG. 8B shows a bonding strength between a Si layer
`and a Si layer, and FIG. 8C shows a bonding strength
`between a Si02 layer and a Si02layer. The data shown
`in FIGS. 8B and 8C are obtained under the same condi(cid:173)
`tions as in FIG. 8A. Although the bonding strength
`between the two Si layers is small and unsatisfactory, it
`can be seen that the bonding strength is sufficiently
`large for the cases shown in FIGS. 8A and 8C and very
`large in the case shown in FIG. 8A.
`Next, a description will be given of a second embodi(cid:173)
`ment of the method of producing the semiconductor(cid:173)
`on-insulator structure according to the present inven(cid:173)
`tion, by referring to FIGS. 9A through 9E. In FIGS.
`9A through 9E, those parts which are essentially the
`same as those corresponding parts in FIGS. 6A through
`6F are designated by the same reference numerals.
`FIG. 9A shows the active substrate 14 which is made
`of the p-type Si and is covered by the Si02 layer 15.
`FIG. 9B shows the base substrate 12 which is made of a
`p-type or n-type Si and is covered by a Si02 layer 13.
`The Si02 layers 13 and 15 are formed by a thermal
`oxidation. For example, the Si02 layer 15 has a thick(cid:173)
`ness in the range of 0.04 micron to 0.1 micron and the
`Si02layer 13 has a thickness in the range of 0.5 micron
`to 2.0 microns.
`Next, AI ions are injected on one surface of the Si02
`layer 13 as shown in FIG. 9C so as to generate a nega(cid:173)
`tive fixed charge nfc within the Si02 layer 13. The
`negative fixed charge nfc is generated by a damage and
`the like within the Si02layer 13. The active substrate 14
`is then bonded onto the base substrate 12 so that the
`surface of the Si02 layer 15 makes contact with the
`Si02layer 13 which has the negative fixed charge nfc as
`shown in FIG. 9D. The bonding is achieved by apply(cid:173)
`ing a field in the state where the Si02 layer 15 makes
`contact with the Si02 layer 13 which has the negative
`fixed charge nfc, and the Si02 layers 15 and 13 are
`bonded by the Vander Waals force. Thereafter, a top
`portion of the active substrate 14 is removed by a me(cid:173)
`chanical polishing or a chemical etching as shown in
`FIG. 9E. For example, the active substrate 14 is formed
`to a desired thickness which is in the range of 0.1 mi(cid:173)
`cron to 10 microns.
`FIG. 10 shows a semiconductor-on-insulator struc(cid:173)
`ture which is produced by the second embodiment on
`an enlarged scale. The positive charge is generated in
`the Si02 layer 15 due to the SiO and Sjz03 molecules
`because the AI ions are not injected into the Si02 layer
`15. On the other hand, the negative fixed charge nfc is
`generated in the Si02 layer 13 due to the AI ions, and
`the negative fixed charge nfc cancels the field which is
`generated by the positive charge within the Si02 layer
`15. In other words, fixed charges of opposite polarities
`are generated with respect to the interface states of the
`two Si02 layers 13 and 15. Therefore, no charge is
`induced at the interface between the active substrate 14
`and the Si02 layer portion (13 and 15), and it is possible
`to prevent the inversion and depletion state from occur(cid:173)
`ring at this interface. Because the thickness of the Si02
`layer 15 is small, the field of the fixed charge acting on
`the active substrate 14 is large.
`FIG. 11 shows a MOSFET which is formed by use of
`the semiconductor-on-insulator structure shown
`in
`FIG. 10. The MOSFET has a source 18, a drain 19 and
`
`013
`
`

`
`7
`a gate electrode 20. The semiconductor-on-insulator
`structure prevents the natural generation of an inver(cid:173)
`sion layer and a depletion layer from being formed
`between the source 18 and the drain 19. Hence, the
`normal operation of the MOSFET is guaranteed.
`Next, a description will be given of a third embodi(cid:173)
`ment of the method of producing the semiconductor(cid:173)
`on-insulator structure according to the present inven(cid:173)
`tion, by referring to FIGS. 12A through 12C. In FIGS.
`12A through 12C, those parts which are essentially the 10
`same as those corresponding parts in FIGS. 9A through
`9E are designated by the same reference numerals, and
`a description thereof will be omitted. FIG. 12A shows
`the active substrate 14 having the Si02 layer 15. FIG.
`12B shows the base substrate 12 having a glass layer 33 15
`which has a positive fixed charge pfc. For example, the
`glass layer 33 contains 65 weight percent of zinc oxide
`(ZnO), 21.5 weight percent of boron dioxide (B02) and
`13.5 weight percent of silicon dioxide (Si02), and an
`annealing step is carried out after the glass layer 33 is 20
`coated on the base substrate 12. In this embodiment, the
`glass layer 33 has a thickness of 5000 A or greater, and
`the Si02layer 15 has a thickness of 500 A or greater so
`as to prevent P, B and Zn from diffusing into the active
`substrate 14 during a thermal process which is carried 25
`out in a later stage of the production process.
`The substrates 14 and 12 shown in FIGS. 12A and
`I2B are then subjected to a bonding process to produce
`the semiconductor-on-insulator structure shown in
`FIG. 12C. As a result, a negative charge is induced at 30
`the interface between the active substrate 14 and the
`Si02 layer 15. Hence, it is possible to obtain effects
`which are substantially the same as those obtainable in
`the first and second embodiments.
`Instead of using the glass layer 33 which has the 35
`above described composition, it is possible to use a
`phospho-silicate glass (PSG) layer which contains 8
`weight percent of phosphorous (P). Such a PSG layer
`may be deposited on the base substrate 12 by a chemical
`vapor deposition (CVD).
`FIG. 13 is a cross sectional view for explaining a
`modification of the first embodiment of the method of
`producing an embodiment of the semiconductor-on(cid:173)
`insulator structure according to the present invention.
`In this modification, the Si02 layer 13 having the nega- 45
`tive fixed charge nfc is polished to a predetermined
`thickness as indicated by a phantom line in FIG. 13
`before bonding the substrates 14 and 12. The predeter(cid:173)
`mined thickness is selected so that the AI density at the
`polished surface of the Si02 layer 13 is approximately a 50
`maximum in FIG. 7.ln other words, a certain thickness
`of the Si02 layer 13 having the negative fixed charge
`nfc is removed so that the surface portion contains an
`AI density corresponding to a peak portion of the depth
`(distance) versus AI density curve shown in FIG. 7.
`Therefore, the embodiment of the semiconductor-on(cid:173)
`insulator structure is characterized in that the negative
`fixed charge is large at the interface between the Si02
`layer 13 and the active substrate 14. Hence, the effect of
`preventing the back channel is extremely satisfactory. 60
`This modification can be applied similarly to the
`second embodiment of the method.
`In the first and second embodiments of the method,
`ion implantation is used to inject the AI ions into the
`Si02 layer 13. However, it is possible to submerge the 65
`base substrate 12 which has the Si02 layer 13 into a
`solution
`including 1000 ppm
`to 10000 ppm of
`polyaluminum chloride [Ab(OH)nCL6- n]m so as to
`
`40
`
`55
`
`5,066,993
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`5
`
`8
`generate the negative fixed charge in the Si02 layer 13,
`where 1 ~ n ~ 5 and m ~ 10. It is also possible to generate
`the negative fixed charge by a CVD, an electron cycro(cid:173)
`tron resonance (ECR) plasma CVD and the like.
`In addition, the generation of the negative fixed
`charge is not limited to injecting Al ions into the Si02
`layer 13. For example, it is possible to inject other ele(cid:173)
`ments such as calcium (Ca), potassium (K), tin (Sn) and
`the like.
`Moreover, when the active substrate 14 is made of an
`n-type semiconductor and negative charge is generated
`at the interface between the active substrate 14 and the
`Si02 layer 15, it is necessary to inject elements into the
`Si02 layer 13 of the base substrate 12 so that the positive
`charge is generated in the Si02 layer 13 when produc(cid:173)
`ing the stacked structure of the base substrate 12 and the
`Si02 layer 13.
`In addition, the structure to which the active sub(cid:173)
`strate 14 is bonded need not necessarily have the semi(cid:173)
`conductor/insulator structure. The only requirement is
`that the base substrate structure has at least an insulator
`layer, and the entire base substrate structure may be
`made of an insulator.
`The bonding process is of course not limited to the
`thermal process. For example, it is possible to employ as
`the bonding method a process which applies an electro(cid:173)
`static pulse to the substrate.
`Further, the present invention. is not limited to these
`embodiments, but various variations a