United States Patent £19J
`Kusunoki
`
`[54] MULTI·LAYER TYPE SEMICONDUCI'OR
`DEVICE WITH SEMICONDUCI'OR
`ELEMEI'o'T LAYERS STACKED IN OPPOSITE
`DIRECTIONS AND MANUFACI'URING
`METHOD THEREOF
`
`[75)
`
`Inventor:
`
`Shiae111 Kuunoki, Hyogo, Japan
`
`[73) Assignee: Mitsubishi Denki Kabushiki Kaisba,
`Tokyo, Japan
`
`[21] Appl. No.: 585,462
`
`[22) Filed:
`
`Sep. 20, 1990
`
`Foreign Application Priority Data
`[30]
`Sep. 22, 1989 [JP)
`Japan .................................. 1-247156
`
`lilt. 0.5 ...................... H01L 27/14; HOIL 31/00
`[51]
`[52) u.s. a ......................................... 359/72; 359/48;
`257/72; 257/84
`[58] Field of Search ................ 357/30 D, 30 G , 30 H,
`357/30 K, 49, 59 F, 71 , 59 E, 23.7, 75, 49;
`359n2
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,272,880 6/1981 Pashley ............................. 357/59 F
`4,651,001 3/1987 Harada et al. .................... 357/30 D
`4,870,475 9/1989 Endo et al ............................ 357/71
`4,899,204 2/1990 Ro~n et al ....................... 357/30 D
`4,939,568 7/1990 Kato et al ............................. 357/49
`
`OTHER PUBLICATIONS
`Furukawa, "Silicon-on-Insulator: Its Technology and
`Applications".
`Maszara eta!, "Wafer Bonding for SOl", Mat. Res. Soc.
`Symp. Proc., vol. 107 (1988), pp. 489-494.
`Nishimura et al, "Three Dimensional IC for High Per(cid:173)
`formance Image Signal Processor", Procee(!.ings of the
`
`lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll
`5,189,500
`Feb. 23, 1993
`
`US005189500A
`[11] Patent Number:
`[45) Date of Patent:
`
`Internadona/ Electron Devices Meeting (1987),
`IEDM-
`pp. I ll-114.
`.
`Ahn et a!, "Dissolution and Disintegration of Uniform
`Si02 Layers During Direct Silicon Wafer Bonding",
`Mat Res. Soc. Symp. Proc., vol. 107, pp. 501-506.
`Furukawa et a!, "Applications of the Silicon Wafer
`Direct-BOnding Technique to Electron Devices", Ap(cid:173)
`plied Surface Science 41/42 (1989), pp. 627-632.
`Primary Examiner-Andrew J. James
`Assistant Examiner-Sara W. Crane
`Attorney, Agent, or Firm-Lowe, Price, LeBlanc &
`Becker
`
`ABSTRACT
`[57]
`A multi-layer type semiconductor device is disclosed, in
`which a plurality of semiconductor layers are formed in
`vertically opposite directions. The multi-layer type
`semiconductor device is obtained by forming a first
`semiconductor layer, an insulating layer and a second
`semiconductor layer in the mentioned order on a main
`surface of a first substrate, forming a semiconductor
`device by using the second semiconductor layer as a
`base, with an exposed surface thereof directed upward,
`forming an insulating falm on the semiconductor device,
`attaching a second substrate to the insulating ftlm, thin·
`ning the first substrate to expose the first semiconductor
`layer, and forming a further semiconductor device by
`using the frrst semiconductor layer as a base, with an
`exposed surface of the f1rst semiconductor layer di·
`rected upward. A single- chip type image forming sys(cid:173)
`tem or sensing system may be provided by employing,
`as the semiconductor devices, a sensing device such as
`a photosensor, a pressure sensor or the like, a processing
`circuit for processing a signal received from the sensor,
`and a display device for displaying results of the pro·
`cessing. A large number of pads may be provided by
`arranging the pads on opposite surfaces of a chip.
`
`15 Claims, 24 Drawing Sheets
`
`001
`
`SONY 1011
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 1 of 24
`
`5,189,500
`
`FIG.1A
`
`FIG.1E
`
`708a
`1o9a FIG.1F 7o9a
`
`FIG.lB
`
`/
`I-
`V//////////////~ ~'
`1-
`
`708a
`
`711
`
`'111
`
`:: f~~t FIG.1H
`~703bl= ==::::~~~~~f~c
`L
`
`FIG.lC
`
`002
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 2 of 24
`
`5,189,500
`
`. FIG.11
`
`FIG.1L
`
`FIG. 1M
`
`714
`
`FIG.1J
`703b 704b 702
`705
`701 b { t-7-"T'"""T""7"""7"""7""7"""7""7'"""-7-T-~.,...4
`702
`L1 {~~
`70S a
`709a
`711
`701c{
`
`~-------'
`
`FIG.1K
`
`70Sb
`
`L2
`
`L1 {~~~~=t-71
`......_ ______ __. ~'{~--------'
`
`003
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 3 of 24
`
`5,189,500
`
`BOla{~~~~:
`
`FIG.2B
`r-_-_-__ -_-__ -_-_-__ -_-_-__ -Ln
`815
`L2
`>h-?'7""7""7'"rrr.;:,.:::r.,;..:;.:;..;;..:;..:;.:r L1
`SOla ~~~~~~[;~ib
`"-------~ fK>3
`800
`
`FlG.2C
`
`FlG.2E
`
`FIG.2F
`E
`~
`
`FIG.2D
`
`,-79
`
`+
`0
`
`FIG. 3
`
`814
`
`00
`0
`
`004
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 4 of 24
`
`5,189,500
`
`FIG.4A
`
`FIG.4B
`
`THE PHOTOSENSOR LAYER
`DETECTS THE LIGHT . ENTERING
`THE TRANSPARENT SUBSTRATE
`L
`ELECTRIC SIGNAL IS
`DIGITALIZED BY AN
`A/0 CONVERTER
`~ .
`LOGIC OPERATIONS
`ARE PERFORMED
`~
`THE SIGNAL OBTAINED BY
`LOGIC OPERATIONS ARE
`CONVERTED JNTO AN
`
`ANALOG SIGNAL •
`
`THE UQUJD CRYSTAL DISPLAY
`DISPLAYS AN IMAGE BASED
`ON THE SIGNAL
`
`005
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 5 of 24
`
`5,189,500
`
`FIG.5
`
`FlG.6
`
`8)6
`
`819
`
`BRIGHT
`
`;
`
`DARK
`
`FIG.7
`
`a o ~
`bo --1.
`
`FIG. SA
`p
`L1
`11 12
`21 22
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`'
`t
`I
`t
`
`I
`I
`t
`I
`
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`
`L
`----- -- -
`---- -t --t-
`~~~~·~
`I
`I
`---- -t -4 --
`
`816
`
`lm
`2m
`
`I
`t
`t
`
`Rm
`
`FIG.8B
`
`006
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 6 of 24
`
`5,189,500
`
`FIG.9
`
`A
`
`c
`
`8
`
`FIG.11
`
`8
`
`A
`
`FIG.10
`85
`
`95
`
`OUT
`
`65c
`
`c
`l
`
`II
`
`0
`
`1
`
`LIGHT INPUT
`DETECTION
`C IRCUJT OUTPUT
`
`NAND OUTPUT
`INVERTER
`OUTPUT
`
`· Lt
`
`1
`
`0
`
`1
`
`0
`
`1
`
`0
`
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`
`1
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`0
`
`1
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`
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`
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`
`0
`
`l
`
`NOR INPUT
`
`NOR OUTPUT
`
`SWJTHING
`CIRCUIT
`ll QUID CRYSTAL
`DISPLAY
`
`1
`
`1
`
`1
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`. 0
`
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`0
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`
`DARK
`
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`
`007
`
`

`

`FIG.12
`
`95
`r----- - -- --~~ .
`VDDo--.----------------------------~--~-------------+------~
`
`I
`I
`I
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`
`I l ___ j_ ___ J
`
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`
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`PIXEL A
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`,..--------- - -
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`:
`I
`I
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`I
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`?'
`N
`JN
`""'"
`IC
`IC
`~
`
`PIXEL B
`
`008
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 8 of 24
`
`5,189,500
`
`FIG.13A
`
`lOb
`
`11a
`
`·
`
`XIV
`
`14a
`
`FIG.13B
`
`n
`
`Di
`
`XIV
`
`GND
`
`009
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 9 of 24
`
`5,189,500
`
`FIG.13C
`
`FIG.13D
`
`Voo
`
`XV
`
`010
`
`

`

`I
`
`FIG.14
`F1614
`
`XV
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`30m
`3‘“ I.“ 6ND
`FIRST =--—
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`LAYER {W_‘.....“I'm
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`320
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`819
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`

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`L!
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`
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`
`FIG.15
`
`XIV
`
`r
`
`Tr10
`
`819
`
`. XIV
`
`012
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 12 of 24
`
`5,189,500
`
`FIG.16
`
`FIG.17A
`
`,sob
`
`~~
`
`801b
`.....- ~
`-
`816
`}81 5
`827
`818
`'-...
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`FIG.18
`r------L..25
`'t----1'80d
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`..... -8 01b
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`...... -8 01b
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`FIG.17B /
`
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`·FIG.19
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`81
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`822
`
`-
`
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`\j-35
`
`013
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 13 of 24
`
`5,189,500
`
`FIG.20A
`
`,.-90a
`901b
`I" .....
`922
`..::
`--- -------------
`}
`915
`f- -- --- - -- - -- ---- -
`--- ------ --- ----
`902
`/ / / / / / / / / / / / / / / /
`1-
`904b
`903
`'-
`
`FIG.208
`
`FlG.20E
`
`FIG.20C
`
`FIG.20F
`
`901b
`
`014
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 14 of 24
`
`5,189,500
`
`FIG.2·1A
`
`FIG.21B
`
`FIG.21C
`
`RADIATION
`
`---------------~---
`p
`
`015
`
`

`

`~ •
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`FIG.22A
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`
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`tOO a
`
`FIG.22B
`
`1031a
`
`1031a
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`
`1015a,b
`
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`1031a
`
`V
`1017a
`101%:
`(1029a)
`(10298)
`
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`
`_
`FIG.22C
`FIG.22C
`1011b
`} 1001d[1001 i
`1015a 10113 10313
`M3. \1003
`1030b 1031b
`100a
`100
`
`- - ~ ~~~+-~~--~~--~~
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`1
`
`
`
`~~==±=====r--r----~~~--1030a
`
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`} 1001c}
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`1013101.";
`
`100j01 c 1013 1014
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`G
`
`F
`F
`
`016
`016
`
`

`

`FIG.23A
`F lG.23A
`
`/ 1001c
`1028a
`/r1028~
`_/‘°23.b
`1001*-
`[028a
`1_oz_3d
`100m
`1923::
`[L—-1] 25:13]
`D~-~1'---______ __,_[~]]
`
`FIG.23B
`FIG-.233
`'
`
`1029b
`1001c
`10293
`'
`1031b
`1001d
`1031a
`1029b
`1001c
`—‘_I— I
`
`FIG.23C
`FlG.23C _
`
`/1001c
`i029b
`=1029a
`1029b
`1001c
`10293
`103“
`1031b
`100d
`j1031;i
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`
`FIG.23D
`FlG.230
`1031 b /1001 d
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`—I-!I
`
`l
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`
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`
`FIG.23E
`FlG.23E
`1031b
`1031a
`-------.,...L-,..-----r-L.-...,...} 1001d
`~;..a..._--+----_,1---'--fl'-'-1} 1001 c
`1029 b
`. 1030b
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`1030b
`1029b
`
`
`
`017
`01?
`
`oos‘ast‘s
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 17 of 24
`
`5,189,500
`
`FIG.23F
`
`FIG. 23G
`
`101la
`1017a
`1002 .
`~~:::!:=:~======:~::=:=:::=::====:::::=:*-, 004b
`
`FIG.23H
`1011a
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`1011b
`
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`t;::;=i=;.::;:;:;::;::;;:::;:;::;:;:;:;:;:;::r;::r;::t.~~, 004b
`1017a~~~~::=::::::::::::=::=:=:~~l-1017b
`1029a
`1029b
`
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`1031a
`1031b
`1030b
`
`lOOa/ 1031a 1011a 1015a 1031b 1030b lOllb
`
`018
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 18 of 24
`
`5,189,500.
`
`FIG.24A
`BACKGROUND ART
`
`FIG.24E
`
`BACKGROl.t-lD
`ART
`
`FIG.24F BACKGR~D
`109a
`ART
`
`FlG.24B
`BACKGROUND ART
`
`t'lJ;m722ZZ~2ZlZlliiZ?lllZ!Z?ZZ2'2.1-103a
`v /////////// ///;_~--~~
`
`FIG.24G BACKGROJ~T
`
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`
`FIG.24C
`BACKGROUND ART
`
`103a
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`
`11~1:tr~\g~a FIG.24H BACKGR~Jr
`101c{ ~ff(////W/1/ff-Jns~
`
`019
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 19 of 24
`
`5,189,500
`
`F 1 G. 241 BACKGROLW ART
`
`1"//d///////////.l',//////// //////////////////////~
`
`FIG.24K
`BACKGROI..I'Jb AAT
`/
`
`10
`113
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`
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`
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`20~ t 216
`217
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`
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`BACKGROUND ART
`
`r=-_-:_-_---~=:~=~----_- }215
`-- - ---:----------
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`
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`B
`FIG.26B
`-·
`BACKGROLN> ART
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`321
`
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`
`217
`
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`
`/
`
`215
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 20 of 24
`
`5,189,500
`
`FIG.26C
`BACKGROUND ART
`
`FIG.26D
`BACKGRCXJND ART
`
`40 FIG. 27 BACKGRo..ND ART
`417
`
`15
`"I
`
`I
`
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`
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`
`FIG.28A
`BACKGRCU-JD .ART
`
`:~=~~-------=~~~---~~~ }415
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`
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`BACKGROJND ART
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`
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`
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`50/
`FIG.28B
`BACKGROUND ART
`/416
`417
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`
`FIG.28D
`BACKGRO\J'iD ART
`/522
`
`517
`
`1501
`
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`
`021
`
`

`

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`FIG.31
`BAC.KGRCU'40 ART
`25
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`FIG.29
`BACKGRC1J'.ID ART
`
`FIG.30
`BACKGROUND ART
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`FIG.32 BACKGROUND ART
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`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 23 of 24
`
`5,189,500
`
`F 1G.34 A BACKGROLND ART
`617a
`/
`
`60
`
`612
`(601a)
`
`C -·
`
`FlG.34B BACKGROUND ART
`
`FIG.34C
`60"
`
`024
`
`

`

`U.S. Patent
`
`Feb. 23, 1993
`
`Sheet 24 of 24
`
`5,189,500.
`
`FIG.35A BACKGROUND NU
`
`..._____, _____ _..;_ ___ }-__, 601a
`
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`
`611
`
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`BACKGR\.J\J'iD ART
`
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`~----------3-_, 601a
`FIG.35C
`BACKGROUND ART
`
`FIG.35D B~KGR~D ART
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`BACK~D ART
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`
`025
`
`

`

`1
`
`5,189,500
`
`MULTI-LAYER TYPE SEMICONDUCfOR DEVICE
`WITH SEMICONDUCfOR ELEMENT LAYERS
`STACKED IN OPPOSITE DIRECTIONS AND
`MANUFACfURING METHOD THEREOF
`
`2
`such as of oxygen are injected in high concentration
`into a semiconductor layer to form a buried insulating
`layer. With this method, however, it is difficult to ob(cid:173)
`tain a multi-layer structure, which makes this method
`5 hardly applicable for manufacture of a three-dimen(cid:173)
`sional integrated circuit.
`As another technique of obtaining the SOl structure,
`BACKGROUND OF THE INVENTION
`a wafer direct bonding method is known. Such a
`1. Field of the Invention
`method is presented, for example, in "APPLICA-
`This invention relates to multi-layer type semicon-
`ductor devices, and more particularly to multi-layer 10 TIONS OF THE SILICON WAFER DIRECT-
`type semiconductor devices having semiconductor ele-
`BONDING TECHNIQUE TO ELECTRON DE-
`VICES" by K. Furukawa et al. in 1989 Applied Surface
`ment layers stacked in opposite directions. This inven-
`tion relates also to methods of manufacturing such mul-
`Science 41/42 at pp. 627-632. In the wafer direct bond-
`ti-layer type semiconductor devices. The invention has
`ing method, a wafer having an insulating layer formed
`particular application in the field of image processing 15 on a surface thereof is superposed by a single-crystal
`wafer or a wafer having a single-crystal layer, and the
`system fabricated on a single common multiple layer
`two wafers are heat-treated (annealed) in an atmosphere
`integrated circuit.
`2. Description of the Background Art
`of 600• to 1,000• C. The heat treatment induces an inter-
`An ordinary integrated circuit is formed on a surface
`atomic junction over contacting surfaces, thereby bond-
`of a wafer and has, so to speak, a two-dimensional struc- 20 ing the wafers together. Then the upper wafer is
`ture. As distinct from this, an integrated circuit includ-
`thinned, to complete a semiconductor layer formed on
`ing a plurality of semiconductor layers having semicon-
`the insulating layer. The semiconductor layer obtained
`ductor elements and stacked one upon another is called
`on the insulating layer by the wafer direct bonding
`a three-dimensional integrated circuit. Because of the
`method is, by origin, a product of epitaxy formed on a
`multi-layer structure, the three-dimensional integrated 25 single-crystal silicon substrate. Thus, this semiconduc-
`tor layer has an excellent crystalline property and a
`circuit has the advantage of realizing a very high degree
`of integration and greatly improved functions.
`uniform film thickness, to be suitable for manufacture of
`Generally, the three-dimensional integrated circuit
`a three-dimensional integrated circuit.
`includes semiconductor layers and insulating layers
`A multi-layer type semiconductor device manufac-
`stacked alternately, with each semiconductor layer 30
`having active elements formed therein. With the inte-
`tured by the above wafer direct bonding method and
`forming the background of this invention will be de-
`grated circuit having active elements formed in the
`scribed next.
`respective semiconductor layers formed on the insulat-
`FIGS. 24A through 24K are sectional views showing
`ing layers, the elements have only a small excess capac-
`ity, and hence a further advantage of enabling high 35 a process of manufacturing the multi-layer type semi-
`speed operation of these elements.
`conductor device forming the background of this inven-
`The technique of forming semiconductor layers, par-
`tion.
`ticularly silicon layers, on insulating layers will be de-
`Referring to FIG. 24A, a first silicon wafer lOla
`scribed next.
`having a thickness of 500 to 600 JLm includes an insulat-
`The technique of providing a structure in which sili- 40 ing layer 102 formed 1,000 to lO,OOOA thick on a surface
`con layers are formed on insulating layers is known as
`region thereof. A second silicon wafer lOlb having a
`SOl (Silicon On Insulator) technique. A silicon layer
`thickness corresponding to that of the first silicon wafer
`formed on an insulating layer is called an SOl layer, and
`lOla includes, formed on a surface region thereof, a
`a structure having silicon layers formed on insulating
`boron-injected layer 103a with boron injected thereinto
`layers an SOl structure. Such a technique is described, 45 in a high concentration on the order of 1 X 102°/cm3 and
`a low concentration epitaxial layer 104a having a thick-
`for example, in an article titled "Silicon-on-Insulator: Its
`Technology and Applications" edited by S.Furukawa
`ness of about S,OOOA. Boron-injected layer 103 is used
`and published by KTK Scientific Publishers in 1985.
`as etchant stopper for a subsequent process. The epitax-
`ial layer 104a is obtained by causing silicon crystals to
`As SOl techniques, methods are known which utilize
`epitaxy. These methods include a liquid phase epitaxy so grow epitaxially on the single-crystal substrate lOlb.
`Referring to FIG. 24B, the two wafers lOla and lOlb
`method such as a melting recrystallization method in
`which a polycrystalline or amorphous semiconductor
`are placed in superposition with the insulating layer 102
`layer formed on an insulating layer is exposed to and
`and epitaxial layer 104a opposed to each other, and are
`melted by energy light such as a laser beam, an electron
`heat-treated in an atmosphere of about 800• C. This heat
`beam or the like, and is thereafter allowed to solidify, a 55 treatment is called annealing. The annealing induces an
`solid phase epitaxy method which causes an amorphous
`interatomic junction over contacting surfaces, which
`semiconductor layer to grow in solid phase, and a vapor
`bonds the two wafers lOla and lOlb together. Next, an
`phase epitaxy method which utilizes graphoepitaxy or
`upper surface of one of the wafers lOlb is coarsely
`polished until its thickness is reduced to 100 JLm. There-
`bridging epitaxy. However, since these methods cause
`silicon crystals to grow on an insulating layer, it is difli- 60 after the wafer lOlb is fmely etched with a mixed liquid
`of hydrofluoric acid and nitric acid until its thickness is
`cult to obtain a single-crystal layer over a large area and
`to control film thickness compared with the case of
`reduced to 10 JLm.
`causing silicon crystals to grow epitaxially on a single-
`Next, the wafer lOlb is etched with an aqueous solu-
`tion of ethylenediamine and pyrocatechol. The etching
`crystallayer.
`As a technique of obtaining the SOl structure, 65 step using this aqueous solution is carried out at a rate of
`SIMOX (Separation by Implanted Oxygen) is known.
`1 JLm/min. for semiconductor regions having a low
`SIMOX is a method of obtaining a structure having
`concentration of boron, whereas the etching progresses
`at a rate of 20Mmin. for regions of higher boron con-
`mutually separated semiconductor layers, in which ions
`
`026
`
`

`

`5,189,500 .
`
`4
`3
`electrically interconnected, as necessary, by conductors
`centration. Consequently, the etching action stops at the
`mounted in through holes 114.
`high concentration boron- injected layer 103a. Thus, as
`The multi-layer type semiconductor device manufac-
`shown in FIG. 24C, the wafer lOlb is removed except
`tured by the above method employs a refractory metal,
`the high concentration boron-injected layer 103a and
`epitaxial layer 104a. Next, to form semiconductor ele- 5 instead of aluminum, for the metal interconnections of
`ments, the boron-injected layer t03a is etched away,
`the first active layer. This is because the metal intercon-
`and a surface thereby exposed is oxidized which is fol-
`nections are exposed to the high temperature when the
`lowed by a step of etching away an oxide fllm. This
`two wafers are bonded by annealing as shown in FIG.
`leaves a thin SOl layer t04a having a thickness on the
`241. Thus, if a third active layer is formed on the second
`order of l,OOOA.
`10 active layer, the aluminum interconnections of the sec-
`Referring to FIG. 240 next, field oxide layers lOSa
`ond active layer L2 are replaced with the refractory
`are formed by LOCOS (Local Oxidation of Silicon) in
`metal interconnections.
`regions of the SOl layer 104a which are to serve as
`In the foregoing multi-layer type semiconductor de-
`isolation regions.
`vice, the active layers are stacked in a fixed direction on
`Referring to FIG. 24E next, a gate insulator fllm 107a 15 the basis of a surface of the semiconductor substrate. If
`is formed by oxidation of the SOl layer 104, and a
`a large number of layers are stacked, a distortion due to
`polysilicon layer is formed on the gate insulator fllm
`the fixed stacking direction becomes apparent, giving
`107a. This polysilicon layer is patterned into a shape of
`rise to the problems of fluctuating a threshold voltage
`N
`·
`· ·
`li d b
`and increasing leakage.
`a gate electrode 106a.
`ext, unpuntles are app e Y 20
`Further, since the active layers are stacked on only
`ion implantation using the gate electrode l06a as a mask
`one surface of the substrate, the active layer close to the
`to form source and drain regions 108a.
`substrate is heated more frequently than the active layer
`Referring to FIG. 24F next, an interlayer insulating
`or layers farther away from the substrate and, therefore,
`fllm 109a is formed over the entire surface, and contact
`is required to have a better heat-resisting property.
`holes 110 are formed through the interlayer insulating 25
`An image· processing system employing the multi-
`fllm 109a.
`layer type semiconductor device manufactured by the
`Referring to FIG. 24G next, refractory metal inter-
`foregoing method will be described next. This image
`connections 111 are formed as electrically connected to
`processing system includes a photodetecting portion for
`the source and drain regions 108a and extending onto
`receiving light from an object, and a display portion for
`the interlayer insulating fllms 109a. The gate electrode 30 displaying a received optical signal as an image.
`In such an image processing system, generally, the
`106a, gate insulator fllm 107a and source and drain
`regions 108a constitute a transistor. Next, an insulating
`photodetecting portion and display portion are formed
`layer lU is formed over the interlayer insulating fllm
`separately for the following reason. It is necessary for
`photodetecting elements to receive light from outside,
`109a and refractory metal interconnections 111.
`. Referring to FIG. 24H next, the insulating layer 112 35 and for display elements to be visible from outside. The
`is flattened for the purpose of superposition. Thereafter
`two types of elements must, therefore, be formed in or
`the flattened insulating layer 112 is superposed by a
`adjacent outwardly exposed positions. If the multi-layer
`semiconductor device 10 shown in FIG. 24K is applied
`third silicon wafer tOle including a high concentration
`boron- injected layer 103b and an epitaxial layer 104b as
`to the image processing system, since the display ele-
`does the second silicon wafer lOlb. The two wafers are 40 ments and photodetecting elements are formed on one
`anneaied in an atmosphere of about soo· c., whereby
`side of the substrate, the substrate must be transparent
`the wafers are bonded together through surfaces of the
`and the display elements are formed closest to the sub-
`insulating layer 112 and epitaxial layer 104b as shown in
`strate and the photodetecting elements remotest there-
`FIG. 241.
`from, or, conversely, the photodetecting elements are-
`Next, as described hereinbefore, the wafer tOle is 45 formed closest to the substrate and the display elements
`thinned by polishing and by etching with the mixed
`remotest therefrom. Since the previously formed active
`liquid of hydrofluoric acid and nitric acid. Further, the
`layers are heated every time a new active layer is
`wafer ethylenediamine and pyrocatechol. Conse-
`formed, the active layer close to the substrate is heated
`quently, as shown in FIG. 24J, the wafer tOle is re-
`more frequently than the active layer or layers farther
`moved except the high concentration boron-injected 50 away from the substrate. Thus, a material having a poor
`heat-resisting property cannot be used for the layer
`layer 103b and epitaxial layer 104b. The epitaxial layer
`104b of the third silicon wafer tOle is used as a second
`close to the substrate.
`SOl layer. Subsequently, to form semiconductor ele-
`If, for example, a sensor comprising an amorphous
`ments, the boron-injected layer 103a is etched away.
`material were formed in the layer close to the substrate,
`Referring to FIG. 24K next, field oxide layers lOSb, a 55 this sensor would be inoperable since the amorphous
`material would become crystallized as a result of the
`gate insulator fllm 107b, a gate electrode 106b, source
`long heat treatment. If a sensor comprising a pn junc-
`and drain regions 108b, an interlayer insulating fllm
`tion were formed in the layer close to the substrate, the
`109b, and metal interconnections 113 comprising alumi-
`num or an aluminum alloy are formed by using the
`position of junction in the pn j\inction would shift or
`second SOl layer 104b as a base, as described with 60 would extend deep into the semiconductor layer as a
`result of the long heat treatment, thereby lowering the
`reference to FIGS. 240 and 24E. The gate electrode
`light absorption efficiency of the sensor. Further, a
`106b, gate insulator fllm 107b and source and drain
`regions 108b constitute a transistor. In this way, a first
`liquid crystal display formed adjacent the substrate
`active layer Ll is formed on the semiconductor sub_-
`would have the liquid crystal destroyed by the heat.
`strate lOla through the insulating layer 102, and a sec- 65
`In order to avoid the above setbacks, a possible con-
`ond active layer L2 on the first active layer Ll through
`sideration is that, for example, an active layer including
`the insulating layer 112. The transistor of the first active
`display elements is formed on one surface of the sub-
`layer Ll and that of the second active layer L2 are
`strate, and an active layer including sensor elements is
`
`027
`
`

`

`5,189,500
`
`6
`5
`formed on the other surface thereof. However, this
`transparent window 321 is attached to the resin member
`construction would require through holes to be formed
`320. Subsequently, pressure in a gap between the
`in the thick substrate in order to electrically intercon(cid:173)
`switching circuit 318 and window 321 is reduced to
`nect the active layers formed on the opposite surfaces of
`introduce the liquid crystal 319 therein.
`the substrate. Since it is difficult to form a plurality of 5
`A sensing system employing the foregoing multi(cid:173)
`through holes in the substrate, this method cannot be
`layer type semiconductor device having the three-di(cid:173)
`applied to the above system which requires a high de(cid:173)
`mensional integrated circuit will be described next. This
`gree of integration. Thus, it is very difficult to apply the
`sensing system includes a sensor provided at an input
`multi-layer type semiconductor device with the SOl
`side for detecting light, pressure, temperature or radia-
`layers stacked only on one surface of the substrate to an
`10 tion, and light emitting elements such as light emitting
`image processing system having a photodetecting por(cid:173)
`piodes at an output side for displaying sensing results.
`tion and a display portion formed on a single chip. Gen(cid:173)
`Such a sensing system is shown in fiG. 27.
`erally, therefore, as shown in FIG. 25, a photodetecting
`In FIG. 27, a sensor portion 40 includes a substrate
`portion 20 and a display portion 30 are fabricated sepa(cid:173)
`401, an insulating layer 402 formed on the substrate 401
`rately and are electrically interconnected through leads
`15 for forming an SOl layer, a three-dimensional inte(cid:173)
`15.
`grated circuit 415 formed of a plurality of active layers
`In FIG. 25, the photodetecting portion 20 includes a
`L1, Ll ... Ln and having a processing circuit for pro-
`substrate 201, an insulating layer 202 formed on the
`cessing information detected by the sensor portion 40,
`and an output circuit 417 having output pads. An output
`substrate 201 for forming an SOl layer, a three-dimen-
`sional integrated circuit 215 formed on the insulating 20 portion 50 includes a substrate 501, display elements 522
`which are red, green and blue light emitting diodes
`layer 202 and having a processing circuit for processing
`an electric signal based on the light received by the
`arranged in matrix form, and an input circuit 517 having
`photodetecting portion 20 and a memory circuit for
`input pads.
`storing data for comparison with the electric signal, a
`This sensing system is manufactured by the following
`photoelectric sensor lUi having photodiodes arranged 25 method. As shown in FIG. l8A, the insulating layer 402
`:~~t~:~:~~?:e~~~t ~~~;:!t!~7 ::~::f ~;?~~
`is formed on the substrate 401, and the three-dimen-
`cludes active layers L1, Ll ... Ln forming, individually
`sional integrated circuit 415 is formed on the insulating
`or in combination, circuits having independent func-
`layer 402. Then, as shown in FIG. 28B, the sensor 416
`tions, and signals are communicated among the layers 30 and the output circuit 417 having the output pads are
`via through holes. The disP.lay portion 30 includes a
`formed.
`substrate 301, a switching circuit 318 having electrodes
`As shown in FIGS. 28C and 280, the display ele-
`for driving a liquid crystal display, an input circuit 317
`ments 522 which are the light emitting diodes arranged
`having input pads, a liquid crystal 319, a resin member
`in matrix form, and the input circuit 517 having the
`320 for sealing the liquid crystal, and a window 321.
`35 input pads are formed on the substrate 501. Next, the
`In the image processing system shown in FIG. 25, the
`output pads 417 and input pads 517 are interconnected
`photoelectric sensor 216 of the photodetecting portion
`by leads 15. This completes the sensing system ha~ing a
`20 receives light traveling in the direction of arrow A
`sensing function and a displaying function.
`The foregoing image processing system or sensing
`from an object, and converts it into an electric signal.
`This electric signal is electrically processed by the 40 system may be classified broadly into two types by a
`difference in displaying mode.
`three-dimensional integrated circuit 215 for contour
`extraction and highlighting, pattern recognition and the
`The first type, as shown in FIG. 29, has a photode-
`tecting portion 20 and a display portion 30 formed of
`like. This electric signal is transferred from the output
`pads 217 of the output circuit such as a shift register
`materials penetrable to light, and a transmitted image of
`through the leads 15 to the input pads 317 of the display 45 an object 25 to be detected and an image based on re-
`suits of processing are superimposed when seen by the
`portion 30. In the display portion 30, the liquid crystal
`319 is driven in response to the signal transferred, to
`naked eye 35. The transmitted image herein refers to an
`display a figure such as of contour lines. The displayed
`image of the object 25 visible through the photodetect-
`figure is visible through the window 321 in th