United States Patent £191
`Poon et al.
`
`(11] Patent Number:
`[45] Date of Patent:
`
`5,064,683
`Nov. 12, 1991
`
`[54) ME'IliOD FOR POLISH PLANARIZING A
`SEMICONDUCI'OR SUBSTRATE BY USING
`A BORON NITRIDE POLISH STOP
`
`(75}
`
`Inventors: Stephen S. Poon; ATgerinos V.
`Gelatos, both of Austin, Tex.
`
`[73)
`
`Assignee: Motorola, Inc., Schaumburg, Dl.
`
`(21)
`
`Appl. No.: 604,855
`
`[22]
`
`Filed:
`
`Oet. 29, 1990
`
`[51)
`[52]
`
`[58]
`
`Int. Cl.' ............................................... BOSD 3/ 06
`u.s. Cl .................................... 427/39; 427 1255.2;
`427/255.7; 427/355; 51/281 R; 51!310
`Field of Search ..................... 51/326, 281 R, 310;
`264/162; 437/225; 427/34, 248.1, 264, 39,
`255.7, 355, 255.2; 501/96
`
`(56]
`
`Refereaces Cited
`U.S. PATENT DOCUMENTS
`4,627,991 12/1986 Seki eta!. ............................. 427/39
`4,671,8S1 6/1987 Beyer el a! ................... -..... 156/ 645
`4,789,648 12/1988 Chow eta! . ........................ 437/225
`4,910,1SS 3/1990 Cote et aJ ... - .......................... 43718
`4,944,836 7/1990 Beyer et aL ......................... 156/ 645
`
`OTHER PUBLICATIONS
`"Properties of the B- Si-N Ceramic Thin Films by Plas(cid:173)
`ma-CVD" Takahiro Nakahigashi et al., Shinku (Vac-
`
`uum), vol. 31, No. 9, pp. 789'-795 (1988) Translation
`provided.
`Primary Examiner- Shrive Beck
`Assistant Examiner-Benjamin L. Utech
`Attorney, Agent, or Firm- Jasper W. Dockrey; Robert
`L. King
`[57)
`ABSTRACT
`In a polish palnarization process using a polishing appa(cid:173)
`ratus and an abrasive slurry, a boron nitride (BN) polish
`stop layer (18) is provided to increase the.polish selec(cid:173)
`tivity. The BN layer deposited in accordance with the
`invention has a hexagonal-close-pack crystal orientation
`and is characterized by chemical inertness and high
`hardness. The BN layer has a negligible polish removal
`rate yielding extremely high polish selectivity when
`used as a polish stop for polishing a number of materials
`commonly used in the fabrication of semiconductor
`devices. In accordance with the invention, a substrate
`(12) is provided having an uneven topography includ(cid:173)
`ing elevated regions and recessed regions. A BN polish
`stop layer (18) is desposited to overlie the substrate (12)
`and a fill material (20, 36) which can be dielectric mate(cid:173)
`rial or a conductive material, is deposited to overlie the
`BN polish stop (18) and the recessed regions of the
`substrate. The fill material is then polished bade until
`the BN polish stop is reached resulting in the formation
`of a planar surface (38).
`
`11 Claims, 2 Drawina Sheets
`
`001
`
`SONY 1009
`
`

`
`U.S. Patent
`
`Nov. 12, 1991
`
`Sheet 1 of 2
`
`5,064,683
`
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`

`
`U.S. Patent
`
`Nov. 12, 1991
`
`Sheet 2 of 2
`
`5,064,683
`
`12
`
`FIG.3
`
`12
`
`FIG.4
`
`003
`
`

`
`1
`
`5,064,683
`
`METHOD FOR POLISH PLANARIZING A
`SEMICONDUCTOR SUBSTRATE BY USING A
`BORON NITRIDE POLISH STOP
`
`2
`the passivation layer from the most elevated regions.
`However, the polish time cannot be extended indefi(cid:173)
`nitely or layers underlying the passivation layer can be
`damaged. The polish selectivity can be defined as the
`5 ratio of the removal rate of an overlying layer to that of
`an underlying layer. The polish selectivity must be
`maximized in order to improve the edge to edge polish
`rate uniformity and the ultimate ability of the polish
`process to form a planar surface. One technique used to
`increase polishing selectivity, described in U.S. Pat. No.
`4,944,836 to K. Beyer, adjusts the composition and pH
`of the slurry solution depending upon the polish charac(cid:173)
`teristics of the particular material to be polished and the
`underlying layer. More commonly, a hard, thin film
`referred to as a polish stop layer is deposited to overlie
`the uneven surface of the substrate prior to depositing
`the passivation layer. The polish stop layer underlying
`the passivation layer is more resistant to abrasive re-
`moval than the passivation layer. During polishing,
`when the polish stop overlying the most elevated sur-
`face regions of the substrate is exposed, the removal rate
`of material from the substrate declines and ideally stops
`altogether as all of the elevated portions of the polish
`stop layer become exposed. If the polish stop material is
`sufficiently resistant to abrasive removal and chemically
`unreactive with the components in the slurry, the pol(cid:173)
`ishing time can be extended for a long enough period to
`uniformly polish the passivation layer without damag-
`ing underlying layers.
`While potentially offering wide versatility and a high
`degree of uniformity, the polish process must be con(cid:173)
`trolled to avoid damaging underlying layers. Although
`previous investigators have adjusted various elements
`of the polishing process to increase the polish selectiv(cid:173)
`ity, such as the slurry composition and the polish pad
`material, the preferred method remains the use of a
`polish stop layer. A variety of polish stop materials have
`been reported including silicon nitride, alumina and
`magnesium oxide with silicon nitride being the most
`widely used. For example, the use of silicon nitride is
`described in U.S. Pat. No. 4,671,851 to K. Beyer eta!.
`The polish stop material must be chemically inert, have
`high hardness and have deposition and removal charac(cid:173)
`teristics which are compatible with existing process
`techniques. While materials such as silicon nitride and
`alumina are well characterized and widely used in semi(cid:173)
`conductor fabrication, they lack the necessary charac(cid:173)
`teristics needed for a highly selective polish process.
`
`10
`
`30
`
`FIELD OF THE INVENTION
`This invention relates in general to a method for
`fabricating a semiconductor device, and more particu(cid:173)
`larly to a method for polish planarizing a semiconductor
`substrate with an improved polish stop.
`BACKGROUND OF THE INVENTION
`In order to build faster and more complex integrated
`circuits, semiconductor manufacturers have increased
`the number of components in the integrated circuit 15
`while reducing the overall size of the circuit. The small
`circuit size requires multiple overlying conductive lay(cid:173)
`ers to electrically interconnect the vast number of com(cid:173)
`ponents within the integrated circuit. As successive
`layers of conductors and dielectric materials are depos- 20
`ited over previously defined structures, the surface
`topography can become uneven. To be manufactured
`reliably, the conductive layers need to be deposited, and
`an interconnect pattern defined on a smooth, planar
`surface. A planarization process is typically performed 25
`after the deposition of a dielectric passivation layer to
`reduce the topographic contrast of the passivation
`layer. A conductive layer is then deposited on a smooth,
`even surface and the interconnect pattern reliably de(cid:173)
`fined using conventional photolithography.
`One method for planarizing the substrate surface
`during integrated circuit fabrication is a polish planari(cid:173)
`zation process. Recently, polishing processes have been
`developed which abrasively removed elevated portions
`of a passivation layer overlying an uneven substrate. In 35
`this process, known as chem-mech polishing, the passiv(cid:173)
`ated surface of the substrate is brought into contact with
`a rotating polish pad in the presence of an abrasive
`slurry. A portion of the passivation layer is then abra(cid:173)
`sively removed by the mechanical action of the polish 40
`pad and the chemical action of the slurry. The slurry
`serves to lubricate the surface and contains a fill mate(cid:173)
`rial such as silica to provide additional abrasive force.
`Additional chemicals are sometimes added to the slurry
`to adjust the pH and to chemically etch the surface of 45
`the layer to be polished. See for example, U.S. Pat. No.
`4,910,155 toW. Cote. Wafer polishing has the advan(cid:173)
`tage of being very versatile and not limited by the par(cid:173)
`ticular material being polished. The polishing technique
`can also be used to remove irregularities from the sur- 50
`face of a silicon substrate.
`A common requirement of all polishing processes is
`that the substrate be uniformly polished. In the case of
`polishing back a passivation layer, it is desirable to pol(cid:173)
`ish the layer uniformly from edge to edge on the sub- 55
`strate. To insure that a planar surface is obtained, the
`passivation layer overlying elevated surface regions
`must be uniformly removed. Uniform polishing can be
`difficult because, typically, there is a strong dependence
`in the polish removal rate with localized variations in 60
`the surface topography of the substrate. For example, in
`substrate areas having a high degree of surface varia(cid:173)
`tion, such as areas having closely spaced adjacent
`trenches, the polishing rate is higher than in areas lack(cid:173)
`ing a high degree of surface contrast, such as areas 65
`having large active device regions. The effect of surface
`topography on the removal rate requires the polishing
`time to be extended beyond that required to just remove
`
`BRIEF SUMMARY OF THE INVENTION
`In practicing the present invention there is provided
`a method for forming a BN polish stop layer in which
`the BN has a hexagonal-close-pack crystal orientation.
`The BN layer has a negligible polish removal rate yield(cid:173)
`ing extremely high polish selectivity when used as a
`polish stop for polishing a number of materials com(cid:173)
`monly used in the fabrication of semiconductor devices.
`In accordance with the invention, a substrate is pro(cid:173)
`vided having an uneven topography including elevated
`regions and recessed regions. A BN polish stop layer is
`deposited to overlie the elevated regions and a fill mate(cid:173)
`rial is deposited to overlie the BN polish stop and the
`recessed regions of the substrate. The fill material is
`polished back until the BN polish stop is reached form(cid:173)
`ing a planar surface.
`
`004
`
`

`
`5,064,683
`
`ss
`
`3
`BRIEF DESCRIPTION OF THE ORA WINGS
`FIGS. 1 and 2 illustrate, in cross section, one embodi(cid:173)
`ment of a planarization process in accordance with the
`invention; and
`FIGS. 3 and 4 illustrate, in cross section, another
`embodiment of a planarization process in accordance
`with the invention.
`It will be appreciated that for simplicity and clarity of
`illustration elements shown in the FIGURES have not 10
`necessarily been drawn to scale. For example, the di(cid:173)
`mensions of some of the elements are exaggerated rela(cid:173)
`tive to each other for clarity. Further, where consid(cid:173)
`ered appropriate, reference numerals have been re(cid:173)
`peated among the FIGURES to indicate corresponding
`elements.
`
`4
`ical etchants such as hydrofluoric acid (HF) and phos(cid:173)
`phoric acid (H3P04).
`A particular advantage of the forming a hexagonal
`BN layer in accordance with the invention is the rela-
`5 tively low deposition temperature used during the de(cid:173)
`position process. The deposition temperature at which
`hexagonal BN is deposited is sufficiently low such that
`unwanted thermally catalyzed dopant diffusion and
`material deformation are avoided. For example, in the
`250° to 400° C. deposition range of hexagonal BN, the
`diffusion of dopants previously introduced into the
`semiconductor substrate will not occur. Furthermore,
`at the deposition temperature of hexagonal BN, materi(cid:173)
`als having low thermal tolerances, such as aluminum or
`15 aluminum-silicon alloys will not soften. In contrast, a
`deposition temperature of about 600° to 9CXt C. is neces(cid:173)
`sary to deposit cubic BN which is detrimental to alumi(cid:173)
`DETAILED DESCRIPTION OF A PREFERRED
`num conductors and can induce dopant diffusion. The
`EMBODIMENT
`low deposition temperature of the hexagonal BN polish
`In a search for suitable semiconductor materials that 20
`stop layer thus enables the use of a polishing process at
`various stages in a semiconductor fabrication process
`can be polished to form a planar surface, it has been
`including after the formation of doped regions and
`discovered that boron nitride (BN) forms an excellent
`metal interconnects.
`polish stop having very good adhesiveness to silicon
`Typically, in a fabrication process in which a planari(cid:173)
`and dielectric materials, such as silicon dioxide. The
`boron nitride can be easily deposited, preferably by 25
`zation step is to be used, the substrate has an uneven
`surface topology characterized by recessed regions and
`plasma-enhanced-chemical-vapor-deposition
`elevated regions. Once the BN polish stop is deposited
`(PECVD), or alternatively, by thermal chemical-vapor(cid:173)
`onto a substrate surface, one or more layers to be plana(cid:173)
`deposition (CVD), to form a continuous layer of high
`rized are deposited to overlie the BN polish stop. The
`hardness on the surface of a substrate. The selected 3
`0
`polishing operation is then preferably carried out in a
`PECVD deposition conditions produce a BN film hav-
`polishing apparatus having a rotating polish wheel with
`ing a hexagonal-close-pack crystal orientation similar to
`a polyurethane polishing pad disposed thereon. One
`that of graphite. Despite the well known softness char(cid:173)
`such commercially available polishing apparatus is the
`acteristics of graphite, the BN film deposited in accor(cid:173)
`"Westech 372" manufactured by Westech Inc. of Phoe(cid:173)
`dance with the invention is characterized by substantial 35
`nix, Ariz. A commercially available slurry comprised of
`resistance to abrasive and chemical removal during a
`colloidal silica suspended in potassium hydroxide
`polishing process. The development of a polish stop
`(KOH) is applied to the polishing pad and the one or
`material that is both chemically unreactive with many
`more layers overlying the BN are removed until the BN
`polish slurry compositions and of high hardness, greatly
`layer is reached. Upon exposure of the BN layer, the
`increases the utility of a polishing process used during 40
`removal of any remaining portions of the substrate, and
`semiconductor device fabrication.
`layers thereon, ceases resulting in a smooth planar sur(cid:173)
`The BN material used to form a polish stop layer is
`face.
`preferably deposited onto a semiconductor substrate in
`The removal rate of hexagonal BN deposited using
`a PECVD reactor such as a Plasma III system manufac(cid:173)
`the PECVD process previously described has been
`tured by ASM of Phoenix, Arizona. The deposition is 45
`measured and compared with other materials com(cid:173)
`carried out by flowing about 100 to 250 standard-cubic(cid:173)
`monly used in semiconductor device fabrication. Under
`centimeters-per-minute (SCCM) of diborane (B2H6),
`standard polishing conditions and a pad pressure rang(cid:173)
`about 500 to I 500 SCCM of ammonia (NH3) and about
`ing from 3 to 10 pounds-persquare-inch (psi), a negligi-
`3000 to 5000 SCCM of a carrier gas such as argon (Ar)
`ble removal rate of BN polish stop has been observed.
`into the reactor. A total gas pressure of about 1 to 3 so
`The other polishing conditions are summarized as fol-
`Torr is maintained and a plasma is created by applying
`lows: platen temperature of38o C.; 15 rpm platen speed;
`about 1500 to 2000 Watts of RF power to the anode
`slurry flow rate about 175 SCCM, (Cabot SCI slurry
`located within the reactor chamber. A substrate temper(cid:173)
`manufactured by Nalco Chemical Co.); 35 rpm carrier
`ature of about 250° to 400° C. is maintained during the
`speed; Suba4/IC60 polish pad, manufactured by Rode!
`deposition.
`Products Corp. of Scottsdale, Ariz. Following the pri(cid:173)
`Infra-Red (IR) spectrographic analysis of BN formed
`mary polish, a KOH and deionized water rinse solution
`using the reactor conditions given above indicates the
`is applied at a secondary platen. The removal rates for
`BN film has a hexagonal-close-pack crystal orientation.
`various materials at pad pressures of 5 and 7 psi and
`It has also been found that at a higher substrate tempera(cid:173)
`polishing times of 3 min. were determined by film thick(cid:173)
`ture and RF power, BN having a cubic crystal orienta- 60
`ness measurements using a Nanospec AFT optical inter-
`tion is obtained. While the cubic form of BN possesses
`ferometer manufactured by Nanospec Inc. The results
`high hardness, it does not have the desirable adhesive
`are presented in Table I.
`properties of the hexagonal-close-pack form of BN.
`TABLE I
`Experiments carried out to determine film characteris-
`tics of hexagonal BN deposited on a silicon substrate 65 ________ ......;::.;;P~A::D.=..::..: ________ _
`REMOVAL
`have shown hexagonal BN to have high hardness and to
`MATERIAL
`PRESSURE (PSI)
`RATE (NM/MIN)
`adhere strongly to silicon. In addition, the hexagonal
`LTO
`BN film is substantially unreactive with common chem-
`L TO
`
`5
`7
`
`79
`103
`
`005
`
`

`
`5
`TABLE !-continued
`PAD
`PRESSURE (PSI)
`s
`7
`s
`s
`s
`s
`*less than detection limit of measurement instrument (+I -0.2 NM)
`
`MATERIAL
`POL YSILICON
`POL YSILICON
`BPSG
`
`REMOVAL
`RATE (NM/MIN)
`
`147
`194
`174
`28
`15
`
`5,064,683
`
`20
`
`6
`electrically isolating two or more active device regions
`in substrate 12. Such a structure may occur, for exam(cid:173)
`ple, in the fabrication of MOS SRAM and DRAM
`devices or microprocessor· devices which include
`S EPROM or EEPROM memory arrays, or other de(cid:173)
`vices using trench isolation structures such as bipolar
`and BiCMOS devices. In the case where fill material 20
`is a conductive or semiconductor material, recess 14
`forms a trench capacitor and substrate 12 forms one
`10 capacitor plate while fill material 20 forms the other
`capacitor plate and dielectric layer 16 and polish stop
`The data presented in Table 1 clearly show that BN,
`deposited in accordance with the invention, is of suffi-
`layer 18 form a capacitor dielectric. While not necessar-
`ily depicting any particular semiconductor device struc-
`cient hardness to withstand an abrasive polish removal
`ture, device structure 10 serves to illustrate the applica-
`process. It is apparent from the experimental data given
`in Table I that BN has a much slower removal rate than 15 tion of the invention to the fabrication of a semiconduc-
`many materials commonly used to fabricate semicon-
`tor device.
`ductor devices. The materials L TO (low temperature
`Device structure 10 is planarized by placing the
`oxide), BPSG and Si3N4 (silicon nitride) are commonly
`structure in a polishing apparatus wherein fill material
`20 is polished back until polish stop layer 18 is reached,
`used to provide electrical insulation. Polysilicon and
`as shown in FIG. 2. The polishing operation forms a
`TiN (titanium nitride) are commonly used to form con-
`ductive elements. In addition, SbN4 (silicon nitride) and
`smooth planar surface with a highly uniform flatness.
`TiN (titanium nitride) have been used as polish stop
`The high polish selectivity obtainable with BN permits
`layers in the prior art. The negligible removal rate of
`the polishing operation to be extended beyond the point
`the BN polish stop has the practical significance of
`where the BN layer is first exposed. The polish time can
`yielding an extremely high removal selectivity to over- 25 be extended for a sufficient amount of time to remove
`lying fill materials such as those listed in Table I.
`all portions of fill material 20 protruding above the
`The selectivity in a polishing operation is determined
`plane of polish stop layer 18. After polishing back fill
`by the ratio of the removal rate of an overlying fill
`material 20, substrate 12 is cleaned in a conventional
`material to that of the polish stop material. For example
`chemical cleaning process such as a solution of hydro-
`at a pad pressure of 5 psi, this computation yields values 30 gen peroxide and ammonium hydroxide followed by a
`solution of hydrochloric acid, hydrogen peroxide and
`ranging from 3.6 to 11.4 for a SbN4 polish stop support-
`ing the fill materials listed in Table I. Conversely, the
`water, in turn followed by a solution of sulfuric acid and
`hydrogen peroxide, or a variation thereof. Upon com-
`same selectivity values computed for BN yield a sub-
`stantially larger value, further illustrating the superior
`pletion of polishing and cleaning, a device element 24
`polish process results which are attainable with a BN 35 has been formed comprising a plug 22 substantially
`polish stop layer deposited in accordance with the in-
`filling recess 14 and separated from substrate 12 by
`vention.
`dielectric layer 16 and polish stop layer 18. As previ-
`It is expected that the process of the invention will be
`applicable to a number of device structures and fabrica-
`ously described, depending upon the particular material
`tion processes where it is desirable to form a planarized 40 forming plug 22, device element 24 can be either a
`surface. Without further elaboration, it is believed that
`trench isolation structure or a trench capacitor.
`one skilled in the art can, using the preceding descrip-
`EXAMPLE II
`tion, utilize the invention to its fullest extent. The fol(cid:173)
`FIG. 3 shows the cross sectional view of device
`lowing preferred specific embodiments are, therefore,
`structure 10, illustrated in FIG. 2, after further process(cid:173)
`to be construed as merely illustrative, and not limitative 45
`ing. Portions of polish stop layer 18 overlying the prin(cid:173)
`of the remainder of the disclosure in any way whatso-
`ciple surface of substrate 12 are removed using a reac(cid:173)
`ever.
`tive ion etch process employing CHF3 and 02 etch
`gases. Portions of dielectric layer 16 underlying the
`removed portions of polish stop layer 18 can also be
`removed by the CHF3 and 02 reactive ion etch, or
`alternatively, by another oxide etching method such as
`a buffered hydrofluoric acid (BOE) chemical etch. A
`gate dielectric layer 26 is formed on the principal sur(cid:173)
`face of substrate 12. Gate dielectric layer 26 can be a
`thermally grown silicon oxide or a silicon oxide-silicon
`nitride (ONO) composite layer formed by thermal oxi(cid:173)
`dation of substrate 12 followed by silicon nitride deposi(cid:173)
`tion and a second thermal oxidation. Transistor gate
`electrodes 28 and 30 are formed on gate dielectric layer
`26 and a passivation layer 32 is deposited to overlie
`gates 28 and 30 and plug 22. Passivation layer 32 can be
`L TO or a doped silicate glass such as PSG, BPSG and
`the like.
`After passivation layer 32 is formed, a second BN
`polish stop layer 34 is deposited to overlie passivation
`layer 32. The low deposition temperature used during
`the formation of second polish stop layer 34 will not
`
`EXAMPLE I
`FIG. 1 illustrates, in cross section, a semiconductor SO
`device structure 10 formed in accordance with one
`embodiment of the invention. Device structure 10 in(cid:173)
`cludes a substrate 12 which can be a semiconductor or
`an insulating body having a recess 14 formed therein. A
`dielectric layer 16 overlies the surface of substrate 12 55
`and recess 14. A BN polish stop layer 18 overlies dielec(cid:173)
`tric layer 16 and separates dielectric layer 16 from a fill
`material 20 overlying polish stop layer 18. Fill material
`20 can be a dielectric material such as L TO deposited
`using tetraethoxysilane (TEOS), silicon oxide doped 60
`with phosphorus (PSG), silicon oxide doped with boron
`and phosphorus (BPSG) and the like. Alternatively, fill
`material 20 can be a semiconductor material such as
`polysilicon doped with either phosphorus or boron, a
`conductive material refractory metal such as tungsten, 65
`titanium, molybdenum, cobalt and silicides thereof, and
`the like. In the case where fill material 20 is a dielectric
`material, recess 14 forms an isolation trench structure
`
`006
`
`

`
`7
`cause the underlying passivation layer to flow or other(cid:173)
`wise thermally deform. Following the deposition of
`second polish stop layer 34, a planarization layer 36 is
`deposited to overlie second polish stop layer 34. Planar(cid:173)
`ization layer 36 can be PECVD deposited Si3N4, or 5
`alternatively, a glass layer such as L TO, PSG, BPSG
`and the like.
`Next, a polishing operation is performed to polish
`back planarizing layer 36 to form a smooth planar sur(cid:173)
`face 38, as shown in FIG. 4. The polishing step leaves 10
`portions 40 of planarization layer 36 in recessed areas
`below the most elevated portions of second polish stop
`34. Because of the low polish removal rate of second
`polish stop layer 34, the polishing operation can be
`continued as long as necessary to remove all protruding 15
`portions of planarization layer 36. Planarized surface 38
`can now be used to support one or more additional
`layers whose reliability is improved when formed on a
`planar surface. For example, via holes can be formed
`through layers 40, 34 and 32 and a metal interconnec- 20
`tion layer deposited on planarized surface 38 to electri(cid:173)
`cally couple various components in device portion 10.
`Thus it is apparent that there has been provided, in
`accordance with the invention, a process for planarizing
`a substrate which fully meets the advantages set forth 25
`above. Although the invention has been described and
`illustrated with reference to specific illustrative embodi(cid:173)
`ments thereof, it is not intended that the invention be
`limited to those illustrative embodiments. Those skilled
`in the art will recognize that variations and modifica- 30
`tions can be made without departing from the spirit of
`the invention. For example, the planarization process
`disclosed herein can be used with different slurry com(cid:173)
`positions and polish pad material than those described.
`It is therefore intended to include within the invention 35
`all such variations and modifications as fall within the
`scope of the appended claims and equivalents thereof.
`We claim:
`1. A method for polish planarizing a substrate com-
`prising:
`providing a substrate having an uneven topography
`including elevated regions and recessed regions;
`providing a boron nitride polish stop on the elevated
`regions by depositing boron nitride on the substrate
`using chemical vapor deposition at a deposition 45
`temperature no greater than substantially four hun(cid:173)
`dred degrees Centigrade;
`depositing a fill material to overlie the boron nitride
`polish stop and the recessed regions; and
`polishing back the fill material until the boron nitride 50
`polish stop is reached.
`2. The method of claim 1 wherein the step of provid(cid:173)
`ing a boron nitride polish stop comprises plasma en(cid:173)
`hanced chemical vapor deposition of boron nitride.
`3. The method of claim 2 wherein the plasma en- 55
`hanced chemical vapor deposition is carried out at se(cid:173)
`lected temperature and bias voltage conditions to form
`
`40
`
`5,064,683
`
`8
`boron nitride having a hexagonal-close-pack crystal
`orientation.
`4. The method of claim 1 wherein the step of polish(cid:173)
`ing comprises polishing with a silica based slurry mate(cid:173)
`rial.
`5. The method of claim 1 wherein the fill material is
`selected from the group consisting of silicon oxide,
`silicon oxide doped with phosphorus and silicon oxide
`doped with boron and phosphorus.
`6. The method of claim 1 wherein the fill material is
`selected from the group consisting of polysilicon, tung(cid:173)
`sten, titanium, molybdenum, cobalt and silicides of
`tungsten, titanium, molybdenum and cobalt.
`7. A method for polishing planarizing a silicon sub(cid:173)
`strate having recessed regions and protruding regions
`comprising the steps of:
`depositing a boron nitride polish stop layer to overlie
`the substrate, the boron nitride polish stop layer
`having a hexagonal-close-pack crystal orientation;
`depositing at least one layer of filler material to over(cid:173)
`lie the boron nitride polish stop layer wherein the
`at least one layer of filler material has a polishing
`removal rate substantially greater than the boron
`nitride polish stop layer;
`placing the substrate in a polishing apparatus wherein
`the substrate is brought into contact with a rotating
`polishing wheel having a polishing pad disposed
`thereon;
`applying a silica slurry suspended in potassium hy(cid:173)
`droxide to the polishing pad; and
`polishing back the at least one layer of filler material
`until the polish stop is reached.
`8. The method of claim 7 wherein the boron nitride
`polish stop layer is deposited by plasma-enhanced(cid:173)
`chemical-vapor-deposition (PECVD).
`9. A method for forming a polish stop layer in a semi(cid:173)
`conductor fabrication process comprising:
`placing a semiconductor substrate in a plasma-
`enhanced-chemical-vapor-deposition
`(PECVD)
`reactor;
`heating the substrate to about 250° to 400° C.;
`flowing B2H6, NH3 and a carrier gas into the
`PECVD reactor;
`applying about 1500 to 2000 Watts ofRF power to an
`anode within the PECVD reactor;
`maintaining a total pressure of about 1 to 3 Torr
`within the reactor; and
`depositing a layer of boron nitride (BN) having a
`hexagonal-close-pack crystal orientation onto the
`semiconductor substrate.
`10. The method of claim 9 wherein the carrier gas is
`selected from the group consisting of argon, nitrogen
`and helium.
`11. The method of claim 9 wherein the flow rate of
`B2H6 is about 100 to 250 SCCM and the flow rate of
`NH3 is about 500 to 1500 SCCM.
`• • • • •
`
`60
`
`65
`
`007